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Rev 90 Rev 97
1 
 
 1 
 
2 
main.elf:     file format elf32-avr
 2 
main.elf:     file format elf32-avr
3 
 
 3 
 
4 
Sections:
 4 
Sections:
5 
Idx Name          Size      VMA       LMA       File off  Algn
 5 
Idx Name          Size      VMA       LMA       File off  Algn
6 
  0 .text         0000047e  00000000  00000000  00000094  2**1
 6 
  0 .text         0000047e  00000000  00000000  00000094  2**1
7 
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
 7 
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
8 
  1 .data         00000002  00800060  0000047e  00000512  2**0
 8 
  1 .data         00000002  00800060  0000047e  00000512  2**0
9 
                  CONTENTS, ALLOC, LOAD, DATA
 9 
                  CONTENTS, ALLOC, LOAD, DATA
10 
  2 .bss          000000ea  00800062  00800062  00000514  2**0
 10 
  2 .bss          000000ea  00800062  00800062  00000514  2**0
11 
                  ALLOC
 11 
                  ALLOC
12 
  3 .stab         00000378  00000000  00000000  00000514  2**2
 12 
  3 .stab         00000378  00000000  00000000  00000514  2**2
13 
                  CONTENTS, READONLY, DEBUGGING
 13 
                  CONTENTS, READONLY, DEBUGGING
14 
  4 .stabstr      00000071  00000000  00000000  0000088c  2**0
 14 
  4 .stabstr      00000071  00000000  00000000  0000088c  2**0
15 
                  CONTENTS, READONLY, DEBUGGING
 15 
                  CONTENTS, READONLY, DEBUGGING
16 
  5 .debug_aranges 00000020  00000000  00000000  000008fd  2**0
 16 
  5 .debug_aranges 00000020  00000000  00000000  000008fd  2**0
17 
                  CONTENTS, READONLY, DEBUGGING
 17 
                  CONTENTS, READONLY, DEBUGGING
18 
  6 .debug_pubnames 0000011d  00000000  00000000  0000091d  2**0
 18 
  6 .debug_pubnames 0000011d  00000000  00000000  0000091d  2**0
19 
                  CONTENTS, READONLY, DEBUGGING
 19 
                  CONTENTS, READONLY, DEBUGGING
20 
  7 .debug_info   000003bf  00000000  00000000  00000a3a  2**0
 20 
  7 .debug_info   000003bf  00000000  00000000  00000a3a  2**0
21 
                  CONTENTS, READONLY, DEBUGGING
 21 
                  CONTENTS, READONLY, DEBUGGING
22 
  8 .debug_abbrev 0000011c  00000000  00000000  00000df9  2**0
 22 
  8 .debug_abbrev 0000011c  00000000  00000000  00000df9  2**0
23 
                  CONTENTS, READONLY, DEBUGGING
 23 
                  CONTENTS, READONLY, DEBUGGING
24 
  9 .debug_line   00000367  00000000  00000000  00000f15  2**0
 24 
  9 .debug_line   00000367  00000000  00000000  00000f15  2**0
25 
                  CONTENTS, READONLY, DEBUGGING
 25 
                  CONTENTS, READONLY, DEBUGGING
26 
 10 .debug_frame  00000070  00000000  00000000  0000127c  2**2
 26 
 10 .debug_frame  00000070  00000000  00000000  0000127c  2**2
27 
                  CONTENTS, READONLY, DEBUGGING
 27 
                  CONTENTS, READONLY, DEBUGGING
28 
 11 .debug_str    000001dc  00000000  00000000  000012ec  2**0
 28 
 11 .debug_str    00000203  00000000  00000000  000012ec  2**0
29 
                  CONTENTS, READONLY, DEBUGGING
 29 
                  CONTENTS, READONLY, DEBUGGING
30 
 12 .debug_loc    00000220  00000000  00000000  000014c8  2**0
 30 
 12 .debug_loc    00000220  00000000  00000000  000014ef  2**0
31 
                  CONTENTS, READONLY, DEBUGGING
 31 
                  CONTENTS, READONLY, DEBUGGING
32 
Disassembly of section .text:
 32 
Disassembly of section .text:
33 
 
 33 
 
34 
00000000 <__vectors>:
 34 
00000000 <__vectors>:
35 
   0:	12 c0       	rjmp	.+36     	; 0x26 <__ctors_end>
 35 
   0:	12 c0       	rjmp	.+36     	; 0x26 <__ctors_end>
36 
   2:	2c c0       	rjmp	.+88     	; 0x5c <__bad_interrupt>
 36 
   2:	2c c0       	rjmp	.+88     	; 0x5c <__bad_interrupt>
37 
   4:	2b c0       	rjmp	.+86     	; 0x5c <__bad_interrupt>
 37 
   4:	2b c0       	rjmp	.+86     	; 0x5c <__bad_interrupt>
38 
   6:	2a c0       	rjmp	.+84     	; 0x5c <__bad_interrupt>
 38 
   6:	2a c0       	rjmp	.+84     	; 0x5c <__bad_interrupt>
39 
   8:	29 c0       	rjmp	.+82     	; 0x5c <__bad_interrupt>
 39 
   8:	29 c0       	rjmp	.+82     	; 0x5c <__bad_interrupt>
40 
   a:	28 c0       	rjmp	.+80     	; 0x5c <__bad_interrupt>
 40 
   a:	28 c0       	rjmp	.+80     	; 0x5c <__bad_interrupt>
41 
   c:	27 c0       	rjmp	.+78     	; 0x5c <__bad_interrupt>
 41 
   c:	27 c0       	rjmp	.+78     	; 0x5c <__bad_interrupt>
42 
   e:	26 c0       	rjmp	.+76     	; 0x5c <__bad_interrupt>
 42 
   e:	26 c0       	rjmp	.+76     	; 0x5c <__bad_interrupt>
43 
  10:	25 c0       	rjmp	.+74     	; 0x5c <__bad_interrupt>
 43 
  10:	25 c0       	rjmp	.+74     	; 0x5c <__bad_interrupt>
44 
  12:	24 c0       	rjmp	.+72     	; 0x5c <__bad_interrupt>
 44 
  12:	24 c0       	rjmp	.+72     	; 0x5c <__bad_interrupt>
45 
  14:	23 c0       	rjmp	.+70     	; 0x5c <__bad_interrupt>
 45 
  14:	23 c0       	rjmp	.+70     	; 0x5c <__bad_interrupt>
46 
  16:	5c c0       	rjmp	.+184    	; 0xd0 <__vector_11>
 46 
  16:	5c c0       	rjmp	.+184    	; 0xd0 <__vector_11>
47 
  18:	21 c0       	rjmp	.+66     	; 0x5c <__bad_interrupt>
 47 
  18:	21 c0       	rjmp	.+66     	; 0x5c <__bad_interrupt>
48 
  1a:	25 c0       	rjmp	.+74     	; 0x66 <__vector_13>
 48 
  1a:	25 c0       	rjmp	.+74     	; 0x66 <__vector_13>
49 
  1c:	1f c0       	rjmp	.+62     	; 0x5c <__bad_interrupt>
 49 
  1c:	1f c0       	rjmp	.+62     	; 0x5c <__bad_interrupt>
50 
  1e:	1e c0       	rjmp	.+60     	; 0x5c <__bad_interrupt>
 50 
  1e:	1e c0       	rjmp	.+60     	; 0x5c <__bad_interrupt>
51 
  20:	1d c0       	rjmp	.+58     	; 0x5c <__bad_interrupt>
 51 
  20:	1d c0       	rjmp	.+58     	; 0x5c <__bad_interrupt>
52 
  22:	1c c0       	rjmp	.+56     	; 0x5c <__bad_interrupt>
 52 
  22:	1c c0       	rjmp	.+56     	; 0x5c <__bad_interrupt>
53 
  24:	1b c0       	rjmp	.+54     	; 0x5c <__bad_interrupt>
 53 
  24:	1b c0       	rjmp	.+54     	; 0x5c <__bad_interrupt>
54 
 
 54 
 
55 
00000026 <__ctors_end>:
 55 
00000026 <__ctors_end>:
56 
  26:	11 24       	eor	r1, r1
 56 
  26:	11 24       	eor	r1, r1
57 
  28:	1f be       	out	0x3f, r1	; 63
 57 
  28:	1f be       	out	0x3f, r1	; 63
58 
  2a:	cf e5       	ldi	r28, 0x5F	; 95
 58 
  2a:	cf e5       	ldi	r28, 0x5F	; 95
59 
  2c:	d4 e0       	ldi	r29, 0x04	; 4
 59 
  2c:	d4 e0       	ldi	r29, 0x04	; 4
60 
  2e:	de bf       	out	0x3e, r29	; 62
 60 
  2e:	de bf       	out	0x3e, r29	; 62
61 
  30:	cd bf       	out	0x3d, r28	; 61
 61 
  30:	cd bf       	out	0x3d, r28	; 61
62 
 
 62 
 
63 
00000032 <__do_copy_data>:
 63 
00000032 <__do_copy_data>:
64 
  32:	10 e0       	ldi	r17, 0x00	; 0
 64 
  32:	10 e0       	ldi	r17, 0x00	; 0
65 
  34:	a0 e6       	ldi	r26, 0x60	; 96
 65 
  34:	a0 e6       	ldi	r26, 0x60	; 96
66 
  36:	b0 e0       	ldi	r27, 0x00	; 0
 66 
  36:	b0 e0       	ldi	r27, 0x00	; 0
67 
  38:	ee e7       	ldi	r30, 0x7E	; 126
 67 
  38:	ee e7       	ldi	r30, 0x7E	; 126
68 
  3a:	f4 e0       	ldi	r31, 0x04	; 4
 68 
  3a:	f4 e0       	ldi	r31, 0x04	; 4
69 
  3c:	02 c0       	rjmp	.+4      	; 0x42 <.do_copy_data_start>
 69 
  3c:	02 c0       	rjmp	.+4      	; 0x42 <.do_copy_data_start>
70 
 
 70 
 
71 
0000003e <.do_copy_data_loop>:
 71 
0000003e <.do_copy_data_loop>:
72 
  3e:	05 90       	lpm	r0, Z+
 72 
  3e:	05 90       	lpm	r0, Z+
73 
  40:	0d 92       	st	X+, r0
 73 
  40:	0d 92       	st	X+, r0
74 
 
 74 
 
75 
00000042 <.do_copy_data_start>:
 75 
00000042 <.do_copy_data_start>:
76 
  42:	a2 36       	cpi	r26, 0x62	; 98
 76 
  42:	a2 36       	cpi	r26, 0x62	; 98
77 
  44:	b1 07       	cpc	r27, r17
 77 
  44:	b1 07       	cpc	r27, r17
78 
  46:	d9 f7       	brne	.-10     	; 0x3e <__SP_H__>
 78 
  46:	d9 f7       	brne	.-10     	; 0x3e <.do_copy_data_loop>
79 
 
 79 
 
80 
00000048 <__do_clear_bss>:
 80 
00000048 <__do_clear_bss>:
81 
  48:	11 e0       	ldi	r17, 0x01	; 1
 81 
  48:	11 e0       	ldi	r17, 0x01	; 1
82 
  4a:	a2 e6       	ldi	r26, 0x62	; 98
 82 
  4a:	a2 e6       	ldi	r26, 0x62	; 98
83 
  4c:	b0 e0       	ldi	r27, 0x00	; 0
 83 
  4c:	b0 e0       	ldi	r27, 0x00	; 0
84 
  4e:	01 c0       	rjmp	.+2      	; 0x52 <.do_clear_bss_start>
 84 
  4e:	01 c0       	rjmp	.+2      	; 0x52 <.do_clear_bss_start>
85 
 
 85 
 
86 
00000050 <.do_clear_bss_loop>:
 86 
00000050 <.do_clear_bss_loop>:
87 
  50:	1d 92       	st	X+, r1
 87 
  50:	1d 92       	st	X+, r1
88 
 
 88 
 
89 
00000052 <.do_clear_bss_start>:
 89 
00000052 <.do_clear_bss_start>:
90 
  52:	ac 34       	cpi	r26, 0x4C	; 76
 90 
  52:	ac 34       	cpi	r26, 0x4C	; 76
91 
  54:	b1 07       	cpc	r27, r17
 91 
  54:	b1 07       	cpc	r27, r17
92 
  56:	e1 f7       	brne	.-8      	; 0x50 <.do_clear_bss_loop>
 92 
  56:	e1 f7       	brne	.-8      	; 0x50 <.do_clear_bss_loop>
93 
  58:	d4 d1       	rcall	.+936    	; 0x402 <main>
 93 
  58:	d4 d1       	rcall	.+936    	; 0x402 <main>
94 
  5a:	10 c2       	rjmp	.+1056   	; 0x47c <_exit>
 94 
  5a:	10 c2       	rjmp	.+1056   	; 0x47c <_exit>
95 
 
 95 
 
96 
0000005c <__bad_interrupt>:
 96 
0000005c <__bad_interrupt>:
97 
  5c:	d1 cf       	rjmp	.-94     	; 0x0 <__heap_end>
 97 
  5c:	d1 cf       	rjmp	.-94     	; 0x0 <__vectors>
98 
 
 98 
 
99 
0000005e <uart_putchar>:
 99 
0000005e <uart_putchar>:
100 
struct str_Exception Exception;
100 
struct str_Exception Exception;
101 
 
 101 
 
102 
// --------------------------------------------------------------------------
 102 
// --------------------------------------------------------------------------
103 
int uart_putchar (char c)
 103 
int uart_putchar (char c)
104 
{
 104 
{
105 
  5e:	8c b9       	out	0x0c, r24	; 12
 105 
  5e:	8c b9       	out	0x0c, r24	; 12
106 
	UDR = c;
 106 
	UDR = c;
107 
	return (0);
 107 
	return (0);
108 
}
 108 
}
109 
  60:	80 e0       	ldi	r24, 0x00	; 0
 109 
  60:	80 e0       	ldi	r24, 0x00	; 0
110 
  62:	90 e0       	ldi	r25, 0x00	; 0
 110 
  62:	90 e0       	ldi	r25, 0x00	; 0
111 
  64:	08 95       	ret
 111 
  64:	08 95       	ret
112 
 
 112 
 
113 
00000066 <__vector_13>:
 113 
00000066 <__vector_13>:
114 
 
 114 
 
115 
// --------------------------------------------------------------------------
 115 
// --------------------------------------------------------------------------
116 
SIGNAL(SIG_UART_TRANS)
 116 
SIGNAL(SIG_UART_TRANS)
117 
{
 117 
{
118 
  66:	1f 92       	push	r1
 118 
  66:	1f 92       	push	r1
119 
  68:	0f 92       	push	r0
 119 
  68:	0f 92       	push	r0
120 
  6a:	0f b6       	in	r0, 0x3f	; 63
 120 
  6a:	0f b6       	in	r0, 0x3f	; 63
121 
  6c:	0f 92       	push	r0
 121 
  6c:	0f 92       	push	r0
122 
  6e:	11 24       	eor	r1, r1
 122 
  6e:	11 24       	eor	r1, r1
123 
  70:	8f 93       	push	r24
 123 
  70:	8f 93       	push	r24
124 
  72:	9f 93       	push	r25
 124 
  72:	9f 93       	push	r25
125 
  74:	ef 93       	push	r30
 125 
  74:	ef 93       	push	r30
126 
  76:	ff 93       	push	r31
 126 
  76:	ff 93       	push	r31
127 
 static unsigned int ptr = 0;
 127 
 static unsigned int ptr = 0;
128 
 unsigned char tmp_tx;
 128 
 unsigned char tmp_tx;
129 
 if(!UebertragungAbgeschlossen)
129 
 if(!UebertragungAbgeschlossen)
130 
  78:	80 91 60 00 	lds	r24, 0x0060
 130 
  78:	80 91 60 00 	lds	r24, 0x0060
131 
  7c:	88 23       	and	r24, r24
 131 
  7c:	88 23       	and	r24, r24
132 
  7e:	d9 f4       	brne	.+54     	; 0xb6 <__vector_13+0x50>
 132 
  7e:	d9 f4       	brne	.+54     	; 0xb6 <__vector_13+0x50>
133 
  {
 133 
  {
134 
   ptr++;                    // die [0] wurde schon gesendet
 134 
   ptr++;                    // die [0] wurde schon gesendet
135 
  80:	80 91 6c 00 	lds	r24, 0x006C
 135 
  80:	80 91 6c 00 	lds	r24, 0x006C
136 
  84:	90 91 6d 00 	lds	r25, 0x006D
 136 
  84:	90 91 6d 00 	lds	r25, 0x006D
137 
  88:	01 96       	adiw	r24, 0x01	; 1
 137 
  88:	01 96       	adiw	r24, 0x01	; 1
138 
  8a:	90 93 6d 00 	sts	0x006D, r25
 138 
  8a:	90 93 6d 00 	sts	0x006D, r25
139 
  8e:	80 93 6c 00 	sts	0x006C, r24
 139 
  8e:	80 93 6c 00 	sts	0x006C, r24
140 
   tmp_tx = TxdBuffer[ptr];
140 
   tmp_tx = TxdBuffer[ptr];
141 
  92:	fc 01       	movw	r30, r24
 141 
  92:	fc 01       	movw	r30, r24
142 
  94:	e9 52       	subi	r30, 0x29	; 41
 142 
  94:	e9 52       	subi	r30, 0x29	; 41
143 
  96:	ff 4f       	sbci	r31, 0xFF	; 255
 143 
  96:	ff 4f       	sbci	r31, 0xFF	; 255
144 
  98:	e0 81       	ld	r30, Z
 144 
  98:	e0 81       	ld	r30, Z
145 
   if((tmp_tx == '\r') || (ptr == MAX_TX_BUF))
 145 
   if((tmp_tx == '\r') || (ptr == MAX_TX_BUF))
146 
  9a:	ed 30       	cpi	r30, 0x0D	; 13
 146 
  9a:	ed 30       	cpi	r30, 0x0D	; 13
147 
  9c:	19 f0       	breq	.+6      	; 0xa4 <__vector_13+0x3e>
 147 
  9c:	19 f0       	breq	.+6      	; 0xa4 <__vector_13+0x3e>
148 
  9e:	84 36       	cpi	r24, 0x64	; 100
 148 
  9e:	84 36       	cpi	r24, 0x64	; 100
149 
  a0:	91 05       	cpc	r25, r1
 149 
  a0:	91 05       	cpc	r25, r1
150 
  a2:	39 f4       	brne	.+14     	; 0xb2 <__vector_13+0x4c>
 150 
  a2:	39 f4       	brne	.+14     	; 0xb2 <__vector_13+0x4c>
151 
    {
 151 
    {
152 
     ptr = 0;
 152 
     ptr = 0;
153 
  a4:	10 92 6d 00 	sts	0x006D, r1
 153 
  a4:	10 92 6d 00 	sts	0x006D, r1
154 
  a8:	10 92 6c 00 	sts	0x006C, r1
 154 
  a8:	10 92 6c 00 	sts	0x006C, r1
155 
     UebertragungAbgeschlossen = 1;
 155 
     UebertragungAbgeschlossen = 1;
156 
  ac:	81 e0       	ldi	r24, 0x01	; 1
 156 
  ac:	81 e0       	ldi	r24, 0x01	; 1
157 
  ae:	80 93 60 00 	sts	0x0060, r24
 157 
  ae:	80 93 60 00 	sts	0x0060, r24
158 
    }
 158 
    }
159 
   UDR = tmp_tx;
159 
   UDR = tmp_tx;
160 
  b2:	ec b9       	out	0x0c, r30	; 12
 160 
  b2:	ec b9       	out	0x0c, r30	; 12
161 
  b4:	04 c0       	rjmp	.+8      	; 0xbe <__vector_13+0x58>
 161 
  b4:	04 c0       	rjmp	.+8      	; 0xbe <__vector_13+0x58>
162 
  }
162 
  }
163 
  else ptr = 0;
 163 
  else ptr = 0;
164 
  b6:	10 92 6d 00 	sts	0x006D, r1
 164 
  b6:	10 92 6d 00 	sts	0x006D, r1
165 
  ba:	10 92 6c 00 	sts	0x006C, r1
 165 
  ba:	10 92 6c 00 	sts	0x006C, r1
166 
  be:	ff 91       	pop	r31
 166 
  be:	ff 91       	pop	r31
167 
  c0:	ef 91       	pop	r30
 167 
  c0:	ef 91       	pop	r30
168 
  c2:	9f 91       	pop	r25
 168 
  c2:	9f 91       	pop	r25
169 
  c4:	8f 91       	pop	r24
 169 
  c4:	8f 91       	pop	r24
170 
  c6:	0f 90       	pop	r0
 170 
  c6:	0f 90       	pop	r0
171 
  c8:	0f be       	out	0x3f, r0	; 63
 171 
  c8:	0f be       	out	0x3f, r0	; 63
172 
  ca:	0f 90       	pop	r0
 172 
  ca:	0f 90       	pop	r0
173 
  cc:	1f 90       	pop	r1
 173 
  cc:	1f 90       	pop	r1
174 
  ce:	18 95       	reti
 174 
  ce:	18 95       	reti
175 
 
 175 
 
176 
000000d0 <__vector_11>:
 176 
000000d0 <__vector_11>:
177 
}
 177 
}
178 
 
 178 
 
179 
// --------------------------------------------------------------------------
 179 
// --------------------------------------------------------------------------
180 
SIGNAL(SIG_UART_RECV)
 180 
SIGNAL(SIG_UART_RECV)
181 
{
 181 
{
182 
  d0:	1f 92       	push	r1
 182 
  d0:	1f 92       	push	r1
183 
  d2:	0f 92       	push	r0
 183 
  d2:	0f 92       	push	r0
184 
  d4:	0f b6       	in	r0, 0x3f	; 63
 184 
  d4:	0f b6       	in	r0, 0x3f	; 63
185 
  d6:	0f 92       	push	r0
 185 
  d6:	0f 92       	push	r0
186 
  d8:	11 24       	eor	r1, r1
 186 
  d8:	11 24       	eor	r1, r1
187 
  da:	2f 93       	push	r18
 187 
  da:	2f 93       	push	r18
188 
  dc:	3f 93       	push	r19
 188 
  dc:	3f 93       	push	r19
189 
  de:	4f 93       	push	r20
 189 
  de:	4f 93       	push	r20
190 
  e0:	5f 93       	push	r21
 190 
  e0:	5f 93       	push	r21
191 
  e2:	6f 93       	push	r22
 191 
  e2:	6f 93       	push	r22
192 
  e4:	7f 93       	push	r23
 192 
  e4:	7f 93       	push	r23
193 
  e6:	8f 93       	push	r24
 193 
  e6:	8f 93       	push	r24
194 
  e8:	9f 93       	push	r25
 194 
  e8:	9f 93       	push	r25
195 
  ea:	af 93       	push	r26
 195 
  ea:	af 93       	push	r26
196 
  ec:	bf 93       	push	r27
 196 
  ec:	bf 93       	push	r27
197 
  ee:	ef 93       	push	r30
 197 
  ee:	ef 93       	push	r30
198 
  f0:	ff 93       	push	r31
 198 
  f0:	ff 93       	push	r31
199 
 static unsigned int crc;
 199 
 static unsigned int crc;
200 
 static unsigned char crc1,crc2,buf_ptr;
 200 
 static unsigned char crc1,crc2,buf_ptr;
201 
 static unsigned char UartState = 0;
 201 
 static unsigned char UartState = 0;
202 
 unsigned char CrcOkay = 0;
 202 
 unsigned char CrcOkay = 0;
203 
 
 203 
 
204 
 SioTmp = UDR;
204 
 SioTmp = UDR;
205 
  f2:	8c b1       	in	r24, 0x0c	; 12
 205 
  f2:	8c b1       	in	r24, 0x0c	; 12
206 
  f4:	80 93 62 00 	sts	0x0062, r24
 206 
  f4:	80 93 62 00 	sts	0x0062, r24
207 
 
 207 
 
208 
	if(buf_ptr >= MAX_RX_BUF)
208 
	if(buf_ptr >= MAX_RX_BUF)
209 
  f8:	50 91 67 00 	lds	r21, 0x0067
 209 
  f8:	50 91 67 00 	lds	r21, 0x0067
210 
  fc:	54 36       	cpi	r21, 0x64	; 100
 210 
  fc:	54 36       	cpi	r21, 0x64	; 100
211 
  fe:	10 f0       	brcs	.+4      	; 0x104 <__vector_11+0x34>
 211 
  fe:	10 f0       	brcs	.+4      	; 0x104 <__vector_11+0x34>
212 
		UartState = 0;
 212 
		UartState = 0;
213 
 100:	10 92 66 00 	sts	0x0066, r1
 213 
 100:	10 92 66 00 	sts	0x0066, r1
214 
	if(SioTmp == '\r' && UartState == 2)
214 
	if(SioTmp == '\r' && UartState == 2)
215 
 104:	80 91 62 00 	lds	r24, 0x0062
 215 
 104:	80 91 62 00 	lds	r24, 0x0062
216 
 108:	8d 30       	cpi	r24, 0x0D	; 13
 216 
 108:	8d 30       	cpi	r24, 0x0D	; 13
217 
 10a:	09 f0       	breq	.+2      	; 0x10e <__vector_11+0x3e>
 217 
 10a:	09 f0       	breq	.+2      	; 0x10e <__vector_11+0x3e>
218 
 10c:	56 c0       	rjmp	.+172    	; 0x1ba <__vector_11+0xea>
 218 
 10c:	56 c0       	rjmp	.+172    	; 0x1ba <__vector_11+0xea>
219 
 10e:	80 91 66 00 	lds	r24, 0x0066
 219 
 10e:	80 91 66 00 	lds	r24, 0x0066
220 
 112:	82 30       	cpi	r24, 0x02	; 2
 220 
 112:	82 30       	cpi	r24, 0x02	; 2
221 
 114:	09 f0       	breq	.+2      	; 0x118 <__vector_11+0x48>
 221 
 114:	09 f0       	breq	.+2      	; 0x118 <__vector_11+0x48>
222 
 116:	51 c0       	rjmp	.+162    	; 0x1ba <__vector_11+0xea>
 222 
 116:	51 c0       	rjmp	.+162    	; 0x1ba <__vector_11+0xea>
223 
	{
 223 
	{
224 
		UartState = 0;
 224 
		UartState = 0;
225 
 118:	10 92 66 00 	sts	0x0066, r1
 225 
 118:	10 92 66 00 	sts	0x0066, r1
226 
		crc -= RxdBuffer[buf_ptr-2];
 226 
		crc -= RxdBuffer[buf_ptr-2];
227 
 11c:	65 2f       	mov	r22, r21
 227 
 11c:	65 2f       	mov	r22, r21
228 
 11e:	77 27       	eor	r23, r23
 228 
 11e:	77 27       	eor	r23, r23
229 
 120:	fb 01       	movw	r30, r22
 229 
 120:	fb 01       	movw	r30, r22
230 
 122:	32 97       	sbiw	r30, 0x02	; 2
 230 
 122:	32 97       	sbiw	r30, 0x02	; 2
231 
 124:	23 e7       	ldi	r18, 0x73	; 115
 231 
 124:	23 e7       	ldi	r18, 0x73	; 115
232 
 126:	30 e0       	ldi	r19, 0x00	; 0
 232 
 126:	30 e0       	ldi	r19, 0x00	; 0
233 
 128:	e2 0f       	add	r30, r18
 233 
 128:	e2 0f       	add	r30, r18
234 
 12a:	f3 1f       	adc	r31, r19
 234 
 12a:	f3 1f       	adc	r31, r19
235 
 12c:	40 81       	ld	r20, Z
 235 
 12c:	40 81       	ld	r20, Z
236 
		crc -= RxdBuffer[buf_ptr-1];
 236 
		crc -= RxdBuffer[buf_ptr-1];
237 
 12e:	cb 01       	movw	r24, r22
 237 
 12e:	cb 01       	movw	r24, r22
238 
 130:	01 97       	sbiw	r24, 0x01	; 1
 238 
 130:	01 97       	sbiw	r24, 0x01	; 1
239 
 132:	dc 01       	movw	r26, r24
 239 
 132:	dc 01       	movw	r26, r24
240 
 134:	a2 0f       	add	r26, r18
 240 
 134:	a2 0f       	add	r26, r18
241 
 136:	b3 1f       	adc	r27, r19
 241 
 136:	b3 1f       	adc	r27, r19
242 
 138:	2c 91       	ld	r18, X
 242 
 138:	2c 91       	ld	r18, X
243 
		crc %= 4096;
 243 
		crc %= 4096;
244 
 13a:	80 91 6a 00 	lds	r24, 0x006A
 244 
 13a:	80 91 6a 00 	lds	r24, 0x006A
245 
 13e:	90 91 6b 00 	lds	r25, 0x006B
 245 
 13e:	90 91 6b 00 	lds	r25, 0x006B
246 
 142:	84 1b       	sub	r24, r20
 246 
 142:	84 1b       	sub	r24, r20
247 
 144:	91 09       	sbc	r25, r1
 247 
 144:	91 09       	sbc	r25, r1
248 
 146:	82 1b       	sub	r24, r18
 248 
 146:	82 1b       	sub	r24, r18
249 
 148:	91 09       	sbc	r25, r1
 249 
 148:	91 09       	sbc	r25, r1
250 
 14a:	9f 70       	andi	r25, 0x0F	; 15
 250 
 14a:	9f 70       	andi	r25, 0x0F	; 15
251 
 14c:	90 93 6b 00 	sts	0x006B, r25
 251 
 14c:	90 93 6b 00 	sts	0x006B, r25
252 
 150:	80 93 6a 00 	sts	0x006A, r24
 252 
 150:	80 93 6a 00 	sts	0x006A, r24
253 
		crc1 = '=' + crc / 64;
 253 
		crc1 = '=' + crc / 64;
254 
 154:	9c 01       	movw	r18, r24
 254 
 154:	9c 01       	movw	r18, r24
255 
 156:	00 24       	eor	r0, r0
 255 
 156:	00 24       	eor	r0, r0
256 
 158:	22 0f       	add	r18, r18
 256 
 158:	22 0f       	add	r18, r18
257 
 15a:	33 1f       	adc	r19, r19
 257 
 15a:	33 1f       	adc	r19, r19
258 
 15c:	00 1c       	adc	r0, r0
 258 
 15c:	00 1c       	adc	r0, r0
259 
 15e:	22 0f       	add	r18, r18
 259 
 15e:	22 0f       	add	r18, r18
260 
 160:	33 1f       	adc	r19, r19
 260 
 160:	33 1f       	adc	r19, r19
261 
 162:	00 1c       	adc	r0, r0
 261 
 162:	00 1c       	adc	r0, r0
262 
 164:	23 2f       	mov	r18, r19
 262 
 164:	23 2f       	mov	r18, r19
263 
 166:	30 2d       	mov	r19, r0
 263 
 166:	30 2d       	mov	r19, r0
264 
 168:	23 5c       	subi	r18, 0xC3	; 195
 264 
 168:	23 5c       	subi	r18, 0xC3	; 195
265 
 16a:	20 93 69 00 	sts	0x0069, r18
 265 
 16a:	20 93 69 00 	sts	0x0069, r18
266 
		crc2 = '=' + crc % 64;
 266 
		crc2 = '=' + crc % 64;
267 
 16e:	8f 73       	andi	r24, 0x3F	; 63
 267 
 16e:	8f 73       	andi	r24, 0x3F	; 63
268 
 170:	38 2f       	mov	r19, r24
 268 
 170:	38 2f       	mov	r19, r24
269 
 172:	33 5c       	subi	r19, 0xC3	; 195
 269 
 172:	33 5c       	subi	r19, 0xC3	; 195
270 
 174:	30 93 68 00 	sts	0x0068, r19
 270 
 174:	30 93 68 00 	sts	0x0068, r19
271 
		CrcOkay = 0;
 271 
		CrcOkay = 0;
272 
		if((crc1 == RxdBuffer[buf_ptr-2]) && (crc2 == RxdBuffer[buf_ptr-1]))
 272 
		if((crc1 == RxdBuffer[buf_ptr-2]) && (crc2 == RxdBuffer[buf_ptr-1]))
273 
 178:	80 81       	ld	r24, Z
 273 
 178:	80 81       	ld	r24, Z
274 
 17a:	28 17       	cp	r18, r24
 274 
 17a:	28 17       	cp	r18, r24
275 
 17c:	29 f4       	brne	.+10     	; 0x188 <__vector_11+0xb8>
 275 
 17c:	29 f4       	brne	.+10     	; 0x188 <__vector_11+0xb8>
276 
 17e:	8c 91       	ld	r24, X
 276 
 17e:	8c 91       	ld	r24, X
277 
 180:	38 17       	cp	r19, r24
 277 
 180:	38 17       	cp	r19, r24
278 
 182:	11 f4       	brne	.+4      	; 0x188 <__vector_11+0xb8>
 278 
 182:	11 f4       	brne	.+4      	; 0x188 <__vector_11+0xb8>
279 
 184:	91 e0       	ldi	r25, 0x01	; 1
 279 
 184:	91 e0       	ldi	r25, 0x01	; 1
280 
 186:	06 c0       	rjmp	.+12     	; 0x194 <__vector_11+0xc4>
 280 
 186:	06 c0       	rjmp	.+12     	; 0x194 <__vector_11+0xc4>
281 
		{
 281 
		{
282 
			CrcOkay = 1;
282 
			CrcOkay = 1;
283 
		}
 283 
		}
284 
		else
284 
		else
285 
		{
285 
		{
286 
			CrcOkay = 0;
286 
			CrcOkay = 0;
287 
			CntCrcError++;
 287 
			CntCrcError++;
288 
 188:	80 91 64 00 	lds	r24, 0x0064
 288 
 188:	80 91 64 00 	lds	r24, 0x0064
289 
 18c:	8f 5f       	subi	r24, 0xFF	; 255
 289 
 18c:	8f 5f       	subi	r24, 0xFF	; 255
290 
 18e:	80 93 64 00 	sts	0x0064, r24
 290 
 18e:	80 93 64 00 	sts	0x0064, r24
291 
 192:	90 e0       	ldi	r25, 0x00	; 0
 291 
 192:	90 e0       	ldi	r25, 0x00	; 0
292 
		}
 292 
		}
293 
		if(!NeuerDatensatzEmpfangen && CrcOkay) // Datensatz schon verarbeitet
 293 
		if(!NeuerDatensatzEmpfangen && CrcOkay) // Datensatz schon verarbeitet
294 
 194:	80 91 63 00 	lds	r24, 0x0063
 294 
 194:	80 91 63 00 	lds	r24, 0x0063
295 
 198:	88 23       	and	r24, r24
 295 
 198:	88 23       	and	r24, r24
296 
 19a:	09 f0       	breq	.+2      	; 0x19e <__vector_11+0xce>
 296 
 19a:	09 f0       	breq	.+2      	; 0x19e <__vector_11+0xce>
297 
 19c:	6c c0       	rjmp	.+216    	; 0x276 <__vector_11+0x1a6>
 297 
 19c:	6c c0       	rjmp	.+216    	; 0x276 <__vector_11+0x1a6>
298 
 19e:	99 23       	and	r25, r25
 298 
 19e:	99 23       	and	r25, r25
299 
 1a0:	09 f4       	brne	.+2      	; 0x1a4 <__vector_11+0xd4>
 299 
 1a0:	09 f4       	brne	.+2      	; 0x1a4 <__vector_11+0xd4>
300 
 1a2:	69 c0       	rjmp	.+210    	; 0x276 <__vector_11+0x1a6>
 300 
 1a2:	69 c0       	rjmp	.+210    	; 0x276 <__vector_11+0x1a6>
301 
		{
 301 
		{
302 
			NeuerDatensatzEmpfangen = 1;
302 
			NeuerDatensatzEmpfangen = 1;
303 
 1a4:	81 e0       	ldi	r24, 0x01	; 1
 303 
 1a4:	81 e0       	ldi	r24, 0x01	; 1
304 
 1a6:	80 93 63 00 	sts	0x0063, r24
 304 
 1a6:	80 93 63 00 	sts	0x0063, r24
305 
			AnzahlEmpfangsBytes = buf_ptr;
 305 
			AnzahlEmpfangsBytes = buf_ptr;
306 
 1aa:	50 93 65 00 	sts	0x0065, r21
 306 
 1aa:	50 93 65 00 	sts	0x0065, r21
307 
			RxdBuffer[buf_ptr] = '\r';
 307 
			RxdBuffer[buf_ptr] = '\r';
308 
 1ae:	fb 01       	movw	r30, r22
 308 
 1ae:	fb 01       	movw	r30, r22
309 
 1b0:	ed 58       	subi	r30, 0x8D	; 141
 309 
 1b0:	ed 58       	subi	r30, 0x8D	; 141
310 
 1b2:	ff 4f       	sbci	r31, 0xFF	; 255
 310 
 1b2:	ff 4f       	sbci	r31, 0xFF	; 255
311 
 1b4:	8d e0       	ldi	r24, 0x0D	; 13
 311 
 1b4:	8d e0       	ldi	r24, 0x0D	; 13
312 
 1b6:	80 83       	st	Z, r24
 312 
 1b6:	80 83       	st	Z, r24
313 
 1b8:	5e c0       	rjmp	.+188    	; 0x276 <__vector_11+0x1a6>
 313 
 1b8:	5e c0       	rjmp	.+188    	; 0x276 <__vector_11+0x1a6>
314 
		}
314 
		}
315 
	}
 315 
	}
316 
	else
 316 
	else
317 
	switch(UartState)
 317 
	switch(UartState)
318 
 1ba:	80 91 66 00 	lds	r24, 0x0066
 318 
 1ba:	80 91 66 00 	lds	r24, 0x0066
319 
 1be:	81 30       	cpi	r24, 0x01	; 1
 319 
 1be:	81 30       	cpi	r24, 0x01	; 1
320 
 1c0:	01 f1       	breq	.+64     	; 0x202 <__vector_11+0x132>
 320 
 1c0:	01 f1       	breq	.+64     	; 0x202 <__vector_11+0x132>
321 
 1c2:	81 30       	cpi	r24, 0x01	; 1
 321 
 1c2:	81 30       	cpi	r24, 0x01	; 1
322 
 1c4:	20 f0       	brcs	.+8      	; 0x1ce <__vector_11+0xfe>
 322 
 1c4:	20 f0       	brcs	.+8      	; 0x1ce <__vector_11+0xfe>
323 
 1c6:	82 30       	cpi	r24, 0x02	; 2
 323 
 1c6:	82 30       	cpi	r24, 0x02	; 2
324 
 1c8:	09 f0       	breq	.+2      	; 0x1cc <__vector_11+0xfc>
 324 
 1c8:	09 f0       	breq	.+2      	; 0x1cc <__vector_11+0xfc>
325 
 1ca:	53 c0       	rjmp	.+166    	; 0x272 <__vector_11+0x1a2>
 325 
 1ca:	53 c0       	rjmp	.+166    	; 0x272 <__vector_11+0x1a2>
326 
 1cc:	35 c0       	rjmp	.+106    	; 0x238 <__vector_11+0x168>
 326 
 1cc:	35 c0       	rjmp	.+106    	; 0x238 <__vector_11+0x168>
327 
	{
 327 
	{
328 
		case 0:
 328 
		case 0:
329 
          if(SioTmp == '#' && !NeuerDatensatzEmpfangen) UartState = 1;  // Startzeichen und Daten schon verarbeitet
 329 
          if(SioTmp == '#' && !NeuerDatensatzEmpfangen) UartState = 1;  // Startzeichen und Daten schon verarbeitet
330 
 1ce:	80 91 62 00 	lds	r24, 0x0062
 330 
 1ce:	80 91 62 00 	lds	r24, 0x0062
331 
 1d2:	83 32       	cpi	r24, 0x23	; 35
 331 
 1d2:	83 32       	cpi	r24, 0x23	; 35
332 
 1d4:	39 f4       	brne	.+14     	; 0x1e4 <__vector_11+0x114>
 332 
 1d4:	39 f4       	brne	.+14     	; 0x1e4 <__vector_11+0x114>
333 
 1d6:	80 91 63 00 	lds	r24, 0x0063
 333 
 1d6:	80 91 63 00 	lds	r24, 0x0063
334 
 1da:	88 23       	and	r24, r24
 334 
 1da:	88 23       	and	r24, r24
335 
 1dc:	19 f4       	brne	.+6      	; 0x1e4 <__vector_11+0x114>
 335 
 1dc:	19 f4       	brne	.+6      	; 0x1e4 <__vector_11+0x114>
336 
 1de:	81 e0       	ldi	r24, 0x01	; 1
 336 
 1de:	81 e0       	ldi	r24, 0x01	; 1
337 
 1e0:	80 93 66 00 	sts	0x0066, r24
 337 
 1e0:	80 93 66 00 	sts	0x0066, r24
338 
		  buf_ptr = 0;
 338 
		  buf_ptr = 0;
339 
		  RxdBuffer[buf_ptr++] = SioTmp;
 339 
		  RxdBuffer[buf_ptr++] = SioTmp;
340 
 1e4:	80 91 62 00 	lds	r24, 0x0062
 340 
 1e4:	80 91 62 00 	lds	r24, 0x0062
341 
 1e8:	80 93 73 00 	sts	0x0073, r24
 341 
 1e8:	80 93 73 00 	sts	0x0073, r24
342 
 1ec:	81 e0       	ldi	r24, 0x01	; 1
 342 
 1ec:	81 e0       	ldi	r24, 0x01	; 1
343 
 1ee:	80 93 67 00 	sts	0x0067, r24
 343 
 1ee:	80 93 67 00 	sts	0x0067, r24
344 
		  crc = SioTmp;
 344 
		  crc = SioTmp;
345 
 1f2:	80 91 62 00 	lds	r24, 0x0062
 345 
 1f2:	80 91 62 00 	lds	r24, 0x0062
346 
 1f6:	99 27       	eor	r25, r25
 346 
 1f6:	99 27       	eor	r25, r25
347 
 1f8:	90 93 6b 00 	sts	0x006B, r25
 347 
 1f8:	90 93 6b 00 	sts	0x006B, r25
348 
 1fc:	80 93 6a 00 	sts	0x006A, r24
 348 
 1fc:	80 93 6a 00 	sts	0x006A, r24
349 
 200:	3a c0       	rjmp	.+116    	; 0x276 <__vector_11+0x1a6>
 349 
 200:	3a c0       	rjmp	.+116    	; 0x276 <__vector_11+0x1a6>
350
350
351 
          break;
 351 
          break;
352 
		case 1: // Adresse auswerten
 352 
		case 1: // Adresse auswerten
353 
		  UartState++;
 353 
		  UartState++;
354 
 202:	82 e0       	ldi	r24, 0x02	; 2
 354 
 202:	82 e0       	ldi	r24, 0x02	; 2
355 
 204:	80 93 66 00 	sts	0x0066, r24
 355 
 204:	80 93 66 00 	sts	0x0066, r24
356 
		  RxdBuffer[buf_ptr++] = SioTmp;
 356 
		  RxdBuffer[buf_ptr++] = SioTmp;
357 
 208:	80 91 62 00 	lds	r24, 0x0062
 357 
 208:	80 91 62 00 	lds	r24, 0x0062
358 
 20c:	e3 e7       	ldi	r30, 0x73	; 115
 358 
 20c:	e3 e7       	ldi	r30, 0x73	; 115
359 
 20e:	f0 e0       	ldi	r31, 0x00	; 0
 359 
 20e:	f0 e0       	ldi	r31, 0x00	; 0
360 
 210:	e5 0f       	add	r30, r21
 360 
 210:	e5 0f       	add	r30, r21
361 
 212:	f1 1d       	adc	r31, r1
 361 
 212:	f1 1d       	adc	r31, r1
362 
 214:	80 83       	st	Z, r24
 362 
 214:	80 83       	st	Z, r24
363 
 216:	85 2f       	mov	r24, r21
 363 
 216:	85 2f       	mov	r24, r21
364 
 218:	8f 5f       	subi	r24, 0xFF	; 255
 364 
 218:	8f 5f       	subi	r24, 0xFF	; 255
365 
 21a:	80 93 67 00 	sts	0x0067, r24
 365 
 21a:	80 93 67 00 	sts	0x0067, r24
366 
		  crc += SioTmp;
 366 
		  crc += SioTmp;
367 
 21e:	20 91 62 00 	lds	r18, 0x0062
 367 
 21e:	20 91 62 00 	lds	r18, 0x0062
368 
 222:	80 91 6a 00 	lds	r24, 0x006A
 368 
 222:	80 91 6a 00 	lds	r24, 0x006A
369 
 226:	90 91 6b 00 	lds	r25, 0x006B
 369 
 226:	90 91 6b 00 	lds	r25, 0x006B
370 
 22a:	82 0f       	add	r24, r18
 370 
 22a:	82 0f       	add	r24, r18
371 
 22c:	91 1d       	adc	r25, r1
 371 
 22c:	91 1d       	adc	r25, r1
372 
 22e:	90 93 6b 00 	sts	0x006B, r25
 372 
 22e:	90 93 6b 00 	sts	0x006B, r25
373 
 232:	80 93 6a 00 	sts	0x006A, r24
 373 
 232:	80 93 6a 00 	sts	0x006A, r24
374 
 236:	1f c0       	rjmp	.+62     	; 0x276 <__vector_11+0x1a6>
 374 
 236:	1f c0       	rjmp	.+62     	; 0x276 <__vector_11+0x1a6>
375
375
376 
    	  break;
 376 
    	  break;
377 
		case 2: //  Eingangsdaten sammeln
 377 
		case 2: //  Eingangsdaten sammeln
378 
		  RxdBuffer[buf_ptr] = SioTmp;
 378 
		  RxdBuffer[buf_ptr] = SioTmp;
379 
 238:	80 91 62 00 	lds	r24, 0x0062
 379 
 238:	80 91 62 00 	lds	r24, 0x0062
380 
 23c:	e3 e7       	ldi	r30, 0x73	; 115
 380 
 23c:	e3 e7       	ldi	r30, 0x73	; 115
381 
 23e:	f0 e0       	ldi	r31, 0x00	; 0
 381 
 23e:	f0 e0       	ldi	r31, 0x00	; 0
382 
 240:	e5 0f       	add	r30, r21
 382 
 240:	e5 0f       	add	r30, r21
383 
 242:	f1 1d       	adc	r31, r1
 383 
 242:	f1 1d       	adc	r31, r1
384 
 244:	80 83       	st	Z, r24
 384 
 244:	80 83       	st	Z, r24
385 
		  if(buf_ptr < MAX_RX_BUF) buf_ptr++;
385 
		  if(buf_ptr < MAX_RX_BUF) buf_ptr++;
386 
 246:	54 36       	cpi	r21, 0x64	; 100
 386 
 246:	54 36       	cpi	r21, 0x64	; 100
387 
 248:	28 f4       	brcc	.+10     	; 0x254 <__vector_11+0x184>
 387 
 248:	28 f4       	brcc	.+10     	; 0x254 <__vector_11+0x184>
388 
 24a:	85 2f       	mov	r24, r21
 388 
 24a:	85 2f       	mov	r24, r21
389 
 24c:	8f 5f       	subi	r24, 0xFF	; 255
 389 
 24c:	8f 5f       	subi	r24, 0xFF	; 255
390 
 24e:	80 93 67 00 	sts	0x0067, r24
 390 
 24e:	80 93 67 00 	sts	0x0067, r24
391 
 252:	02 c0       	rjmp	.+4      	; 0x258 <__vector_11+0x188>
 391 
 252:	02 c0       	rjmp	.+4      	; 0x258 <__vector_11+0x188>
392 
		  else UartState = 0;
 392 
		  else UartState = 0;
393 
 254:	10 92 66 00 	sts	0x0066, r1
 393 
 254:	10 92 66 00 	sts	0x0066, r1
394 
		  crc += SioTmp;
 394 
		  crc += SioTmp;
395 
 258:	20 91 62 00 	lds	r18, 0x0062
 395 
 258:	20 91 62 00 	lds	r18, 0x0062
396 
 25c:	80 91 6a 00 	lds	r24, 0x006A
 396 
 25c:	80 91 6a 00 	lds	r24, 0x006A
397 
 260:	90 91 6b 00 	lds	r25, 0x006B
 397 
 260:	90 91 6b 00 	lds	r25, 0x006B
398 
 264:	82 0f       	add	r24, r18
 398 
 264:	82 0f       	add	r24, r18
399 
 266:	91 1d       	adc	r25, r1
 399 
 266:	91 1d       	adc	r25, r1
400 
 268:	90 93 6b 00 	sts	0x006B, r25
 400 
 268:	90 93 6b 00 	sts	0x006B, r25
401 
 26c:	80 93 6a 00 	sts	0x006A, r24
 401 
 26c:	80 93 6a 00 	sts	0x006A, r24
402 
 270:	02 c0       	rjmp	.+4      	; 0x276 <__vector_11+0x1a6>
 402 
 270:	02 c0       	rjmp	.+4      	; 0x276 <__vector_11+0x1a6>
403
403
404 
		  break;
 404 
		  break;
405 
		default:
405 
		default:
406 
          UartState = 0;
406 
          UartState = 0;
407 
 272:	10 92 66 00 	sts	0x0066, r1
 407 
 272:	10 92 66 00 	sts	0x0066, r1
408 
 276:	ff 91       	pop	r31
 408 
 276:	ff 91       	pop	r31
409 
 278:	ef 91       	pop	r30
 409 
 278:	ef 91       	pop	r30
410 
 27a:	bf 91       	pop	r27
 410 
 27a:	bf 91       	pop	r27
411 
 27c:	af 91       	pop	r26
 411 
 27c:	af 91       	pop	r26
412 
 27e:	9f 91       	pop	r25
 412 
 27e:	9f 91       	pop	r25
413 
 280:	8f 91       	pop	r24
 413 
 280:	8f 91       	pop	r24
414 
 282:	7f 91       	pop	r23
 414 
 282:	7f 91       	pop	r23
415 
 284:	6f 91       	pop	r22
 415 
 284:	6f 91       	pop	r22
416 
 286:	5f 91       	pop	r21
 416 
 286:	5f 91       	pop	r21
417 
 288:	4f 91       	pop	r20
 417 
 288:	4f 91       	pop	r20
418 
 28a:	3f 91       	pop	r19
 418 
 28a:	3f 91       	pop	r19
419 
 28c:	2f 91       	pop	r18
 419 
 28c:	2f 91       	pop	r18
420 
 28e:	0f 90       	pop	r0
 420 
 28e:	0f 90       	pop	r0
421 
 290:	0f be       	out	0x3f, r0	; 63
 421 
 290:	0f be       	out	0x3f, r0	; 63
422 
 292:	0f 90       	pop	r0
 422 
 292:	0f 90       	pop	r0
423 
 294:	1f 90       	pop	r1
 423 
 294:	1f 90       	pop	r1
424 
 296:	18 95       	reti
 424 
 296:	18 95       	reti
425 
 
 425 
 
426 
00000298 <AddCRC>:
 426 
00000298 <AddCRC>:
427 
          break;
 427 
          break;
428 
	}
428 
	}
429 
}
 429 
}
430 
 
 430 
 
431 
// --------------------------------------------------------------------------
 431 
// --------------------------------------------------------------------------
432 
void AddCRC(unsigned int wieviele)
 432 
void AddCRC(unsigned int wieviele)
433 
{
 433 
{
434 
 298:	dc 01       	movw	r26, r24
 434 
 298:	dc 01       	movw	r26, r24
435 
 unsigned int tmpCRC = 0,i;
435 
 unsigned int tmpCRC = 0,i;
436 
 for(i = 0; i < wieviele;i++)
 436 
 for(i = 0; i < wieviele;i++)
437 
 29a:	89 2b       	or	r24, r25
 437 
 29a:	89 2b       	or	r24, r25
438 
 29c:	29 f4       	brne	.+10     	; 0x2a8 <AddCRC+0x10>
 438 
 29c:	29 f4       	brne	.+10     	; 0x2a8 <AddCRC+0x10>
439 
 29e:	20 e0       	ldi	r18, 0x00	; 0
 439 
 29e:	20 e0       	ldi	r18, 0x00	; 0
440 
 2a0:	30 e0       	ldi	r19, 0x00	; 0
 440 
 2a0:	30 e0       	ldi	r19, 0x00	; 0
441 
 2a2:	a0 e0       	ldi	r26, 0x00	; 0
 441 
 2a2:	a0 e0       	ldi	r26, 0x00	; 0
442 
 2a4:	b0 e0       	ldi	r27, 0x00	; 0
 442 
 2a4:	b0 e0       	ldi	r27, 0x00	; 0
443 
 2a6:	11 c0       	rjmp	.+34     	; 0x2ca <AddCRC+0x32>
 443 
 2a6:	11 c0       	rjmp	.+34     	; 0x2ca <AddCRC+0x32>
444 
 2a8:	20 e0       	ldi	r18, 0x00	; 0
 444 
 2a8:	20 e0       	ldi	r18, 0x00	; 0
445 
 2aa:	30 e0       	ldi	r19, 0x00	; 0
 445 
 2aa:	30 e0       	ldi	r19, 0x00	; 0
446 
 2ac:	40 e0       	ldi	r20, 0x00	; 0
 446 
 2ac:	40 e0       	ldi	r20, 0x00	; 0
447 
 2ae:	50 e0       	ldi	r21, 0x00	; 0
 447 
 2ae:	50 e0       	ldi	r21, 0x00	; 0
448 
 2b0:	67 ed       	ldi	r22, 0xD7	; 215
 448 
 2b0:	67 ed       	ldi	r22, 0xD7	; 215
449 
 2b2:	70 e0       	ldi	r23, 0x00	; 0
 449 
 2b2:	70 e0       	ldi	r23, 0x00	; 0
450 
  {
 450 
  {
451 
   tmpCRC += TxdBuffer[i];
 451 
   tmpCRC += TxdBuffer[i];
452 
 2b4:	fa 01       	movw	r30, r20
 452 
 2b4:	fa 01       	movw	r30, r20
453 
 2b6:	e6 0f       	add	r30, r22
 453 
 2b6:	e6 0f       	add	r30, r22
454 
 2b8:	f7 1f       	adc	r31, r23
 454 
 2b8:	f7 1f       	adc	r31, r23
455 
 2ba:	80 81       	ld	r24, Z
 455 
 2ba:	80 81       	ld	r24, Z
456 
 2bc:	28 0f       	add	r18, r24
 456 
 2bc:	28 0f       	add	r18, r24
457 
 2be:	31 1d       	adc	r19, r1
 457 
 2be:	31 1d       	adc	r19, r1
458 
 2c0:	4f 5f       	subi	r20, 0xFF	; 255
 458 
 2c0:	4f 5f       	subi	r20, 0xFF	; 255
459 
 2c2:	5f 4f       	sbci	r21, 0xFF	; 255
 459 
 2c2:	5f 4f       	sbci	r21, 0xFF	; 255
460 
 2c4:	a4 17       	cp	r26, r20
 460 
 2c4:	a4 17       	cp	r26, r20
461 
 2c6:	b5 07       	cpc	r27, r21
 461 
 2c6:	b5 07       	cpc	r27, r21
462 
 2c8:	a9 f7       	brne	.-22     	; 0x2b4 <AddCRC+0x1c>
 462 
 2c8:	a9 f7       	brne	.-22     	; 0x2b4 <AddCRC+0x1c>
463 
  }
 463 
  }
464 
   tmpCRC %= 4096;
 464 
   tmpCRC %= 4096;
465 
 2ca:	3f 70       	andi	r19, 0x0F	; 15
 465 
 2ca:	3f 70       	andi	r19, 0x0F	; 15
466 
   TxdBuffer[i++] = '=' + tmpCRC / 64;
 466 
   TxdBuffer[i++] = '=' + tmpCRC / 64;
467 
 2cc:	c9 01       	movw	r24, r18
 467 
 2cc:	c9 01       	movw	r24, r18
468 
 2ce:	00 24       	eor	r0, r0
 468 
 2ce:	00 24       	eor	r0, r0
469 
 2d0:	88 0f       	add	r24, r24
 469 
 2d0:	88 0f       	add	r24, r24
470 
 2d2:	99 1f       	adc	r25, r25
 470 
 2d2:	99 1f       	adc	r25, r25
471 
 2d4:	00 1c       	adc	r0, r0
 471 
 2d4:	00 1c       	adc	r0, r0
472 
 2d6:	88 0f       	add	r24, r24
 472 
 2d6:	88 0f       	add	r24, r24
473 
 2d8:	99 1f       	adc	r25, r25
 473 
 2d8:	99 1f       	adc	r25, r25
474 
 2da:	00 1c       	adc	r0, r0
 474 
 2da:	00 1c       	adc	r0, r0
475 
 2dc:	89 2f       	mov	r24, r25
 475 
 2dc:	89 2f       	mov	r24, r25
476 
 2de:	90 2d       	mov	r25, r0
 476 
 2de:	90 2d       	mov	r25, r0
477 
 2e0:	83 5c       	subi	r24, 0xC3	; 195
 477 
 2e0:	83 5c       	subi	r24, 0xC3	; 195
478 
 2e2:	47 ed       	ldi	r20, 0xD7	; 215
 478 
 2e2:	47 ed       	ldi	r20, 0xD7	; 215
479 
 2e4:	50 e0       	ldi	r21, 0x00	; 0
 479 
 2e4:	50 e0       	ldi	r21, 0x00	; 0
480 
 2e6:	fd 01       	movw	r30, r26
 480 
 2e6:	fd 01       	movw	r30, r26
481 
 2e8:	e4 0f       	add	r30, r20
 481 
 2e8:	e4 0f       	add	r30, r20
482 
 2ea:	f5 1f       	adc	r31, r21
 482 
 2ea:	f5 1f       	adc	r31, r21
483 
 2ec:	80 83       	st	Z, r24
 483 
 2ec:	80 83       	st	Z, r24
484 
 2ee:	11 96       	adiw	r26, 0x01	; 1
 484 
 2ee:	11 96       	adiw	r26, 0x01	; 1
485 
   TxdBuffer[i++] = '=' + tmpCRC % 64;
 485 
   TxdBuffer[i++] = '=' + tmpCRC % 64;
486 
 2f0:	2f 73       	andi	r18, 0x3F	; 63
 486 
 2f0:	2f 73       	andi	r18, 0x3F	; 63
487 
 2f2:	23 5c       	subi	r18, 0xC3	; 195
 487 
 2f2:	23 5c       	subi	r18, 0xC3	; 195
488 
 2f4:	fd 01       	movw	r30, r26
 488 
 2f4:	fd 01       	movw	r30, r26
489 
 2f6:	e4 0f       	add	r30, r20
 489 
 2f6:	e4 0f       	add	r30, r20
490 
 2f8:	f5 1f       	adc	r31, r21
 490 
 2f8:	f5 1f       	adc	r31, r21
491 
 2fa:	20 83       	st	Z, r18
 491 
 2fa:	20 83       	st	Z, r18
492 
 2fc:	11 96       	adiw	r26, 0x01	; 1
 492 
 2fc:	11 96       	adiw	r26, 0x01	; 1
493 
   TxdBuffer[i++] = '\r';
 493 
   TxdBuffer[i++] = '\r';
494 
 2fe:	a4 0f       	add	r26, r20
 494 
 2fe:	a4 0f       	add	r26, r20
495 
 300:	b5 1f       	adc	r27, r21
 495 
 300:	b5 1f       	adc	r27, r21
496 
 302:	8d e0       	ldi	r24, 0x0D	; 13
 496 
 302:	8d e0       	ldi	r24, 0x0D	; 13
497 
 304:	8c 93       	st	X, r24
 497 
 304:	8c 93       	st	X, r24
498 
  UebertragungAbgeschlossen = 0;
 498 
  UebertragungAbgeschlossen = 0;
499 
 306:	10 92 60 00 	sts	0x0060, r1
 499 
 306:	10 92 60 00 	sts	0x0060, r1
500 
  UDR = TxdBuffer[0];
 500 
  UDR = TxdBuffer[0];
501 
 30a:	80 91 d7 00 	lds	r24, 0x00D7
 501 
 30a:	80 91 d7 00 	lds	r24, 0x00D7
502 
 30e:	8c b9       	out	0x0c, r24	; 12
 502 
 30e:	8c b9       	out	0x0c, r24	; 12
503 
 310:	08 95       	ret
 503 
 310:	08 95       	ret
504 
 
 504 
 
505 
00000312 <SendOutData>:
 505 
00000312 <SendOutData>:
506 
}
 506 
}
507 
 
 507 
 
508 
 
 508 
 
509 
// --------------------------------------------------------------------------
 509 
// --------------------------------------------------------------------------
510 
void SendOutData(unsigned char cmd,unsigned char modul, unsigned char *snd, unsigned char len)
 510 
void SendOutData(unsigned char cmd,unsigned char modul, unsigned char *snd, unsigned char len)
511 
{
 511 
{
512 
 312:	ff 92       	push	r15
 512 
 312:	ff 92       	push	r15
513 
 314:	0f 93       	push	r16
 513 
 314:	0f 93       	push	r16
514 
 316:	1f 93       	push	r17
 514 
 316:	1f 93       	push	r17
515 
 318:	cf 93       	push	r28
 515 
 318:	cf 93       	push	r28
516 
 31a:	df 93       	push	r29
 516 
 31a:	df 93       	push	r29
517 
 31c:	8a 01       	movw	r16, r20
 517 
 31c:	8a 01       	movw	r16, r20
518 
 31e:	72 2f       	mov	r23, r18
 518 
 31e:	72 2f       	mov	r23, r18
519 
 unsigned int pt = 0;
 519 
 unsigned int pt = 0;
520 
 unsigned char a,b,c;
 520 
 unsigned char a,b,c;
521 
 unsigned char ptr = 0;
 521 
 unsigned char ptr = 0;
522 
 
 522 
 
523 
 TxdBuffer[pt++] = '#';               // Startzeichen
 523 
 TxdBuffer[pt++] = '#';               // Startzeichen
524 
 320:	93 e2       	ldi	r25, 0x23	; 35
 524 
 320:	93 e2       	ldi	r25, 0x23	; 35
525 
 322:	90 93 d7 00 	sts	0x00D7, r25
 525 
 322:	90 93 d7 00 	sts	0x00D7, r25
526 
 TxdBuffer[pt++] = modul;             // Adresse (a=0; b=1,...)
 526 
 TxdBuffer[pt++] = modul;             // Adresse (a=0; b=1,...)
527 
 326:	60 93 d8 00 	sts	0x00D8, r22
 527 
 326:	60 93 d8 00 	sts	0x00D8, r22
528 
 TxdBuffer[pt++] = cmd;		       // Commando
 528 
 TxdBuffer[pt++] = cmd;		       // Commando
529 
 32a:	80 93 d9 00 	sts	0x00D9, r24
 529 
 32a:	80 93 d9 00 	sts	0x00D9, r24
530 
 
 530 
 
531 
 while(len)
 531 
 while(len)
532 
 32e:	22 23       	and	r18, r18
 532 
 32e:	22 23       	and	r18, r18
533 
 330:	19 f4       	brne	.+6      	; 0x338 <SendOutData+0x26>
 533 
 330:	19 f4       	brne	.+6      	; 0x338 <SendOutData+0x26>
534 
 332:	a3 e0       	ldi	r26, 0x03	; 3
 534 
 332:	a3 e0       	ldi	r26, 0x03	; 3
535 
 334:	b0 e0       	ldi	r27, 0x00	; 0
 535 
 334:	b0 e0       	ldi	r27, 0x00	; 0
536 
 336:	5d c0       	rjmp	.+186    	; 0x3f2 <SendOutData+0xe0>
 536 
 336:	5d c0       	rjmp	.+186    	; 0x3f2 <SendOutData+0xe0>
537 
 338:	a3 e0       	ldi	r26, 0x03	; 3
 537 
 338:	a3 e0       	ldi	r26, 0x03	; 3
538 
 33a:	b0 e0       	ldi	r27, 0x00	; 0
 538 
 33a:	b0 e0       	ldi	r27, 0x00	; 0
539 
 33c:	60 e0       	ldi	r22, 0x00	; 0
 539 
 33c:	60 e0       	ldi	r22, 0x00	; 0
540 
 33e:	c7 ed       	ldi	r28, 0xD7	; 215
 540 
 33e:	c7 ed       	ldi	r28, 0xD7	; 215
541 
 340:	d0 e0       	ldi	r29, 0x00	; 0
 541 
 340:	d0 e0       	ldi	r29, 0x00	; 0
542 
  {
 542 
  {
543 
   if(len) { a = snd[ptr++]; len--;} else a = 0;
 543 
   if(len) { a = snd[ptr++]; len--;} else a = 0;
544 
 342:	f8 01       	movw	r30, r16
 544 
 342:	f8 01       	movw	r30, r16
545 
 344:	e6 0f       	add	r30, r22
 545 
 344:	e6 0f       	add	r30, r22
546 
 346:	f1 1d       	adc	r31, r1
 546 
 346:	f1 1d       	adc	r31, r1
547 
 348:	90 81       	ld	r25, Z
 547 
 348:	90 81       	ld	r25, Z
548 
 34a:	6f 5f       	subi	r22, 0xFF	; 255
 548 
 34a:	6f 5f       	subi	r22, 0xFF	; 255
549 
 34c:	71 50       	subi	r23, 0x01	; 1
 549 
 34c:	71 50       	subi	r23, 0x01	; 1
550 
   if(len) { b = snd[ptr++]; len--;} else b = 0;
 550 
   if(len) { b = snd[ptr++]; len--;} else b = 0;
551 
 34e:	19 f4       	brne	.+6      	; 0x356 <SendOutData+0x44>
 551 
 34e:	19 f4       	brne	.+6      	; 0x356 <SendOutData+0x44>
552 
 350:	ff 24       	eor	r15, r15
 552 
 350:	ff 24       	eor	r15, r15
553 
 352:	40 e0       	ldi	r20, 0x00	; 0
 553 
 352:	40 e0       	ldi	r20, 0x00	; 0
554 
 354:	0f c0       	rjmp	.+30     	; 0x374 <SendOutData+0x62>
 554 
 354:	0f c0       	rjmp	.+30     	; 0x374 <SendOutData+0x62>
555 
 356:	f8 01       	movw	r30, r16
 555 
 356:	f8 01       	movw	r30, r16
556 
 358:	e6 0f       	add	r30, r22
 556 
 358:	e6 0f       	add	r30, r22
557 
 35a:	f1 1d       	adc	r31, r1
 557 
 35a:	f1 1d       	adc	r31, r1
558 
 35c:	40 81       	ld	r20, Z
 558 
 35c:	40 81       	ld	r20, Z
559 
 35e:	6f 5f       	subi	r22, 0xFF	; 255
 559 
 35e:	6f 5f       	subi	r22, 0xFF	; 255
560 
 360:	71 50       	subi	r23, 0x01	; 1
 560 
 360:	71 50       	subi	r23, 0x01	; 1
561 
   if(len) { c = snd[ptr++]; len--;} else c = 0;
 561 
   if(len) { c = snd[ptr++]; len--;} else c = 0;
562 
 362:	11 f4       	brne	.+4      	; 0x368 <SendOutData+0x56>
 562 
 362:	11 f4       	brne	.+4      	; 0x368 <SendOutData+0x56>
563 
 364:	ff 24       	eor	r15, r15
 563 
 364:	ff 24       	eor	r15, r15
564 
 366:	06 c0       	rjmp	.+12     	; 0x374 <SendOutData+0x62>
 564 
 366:	06 c0       	rjmp	.+12     	; 0x374 <SendOutData+0x62>
565 
 368:	f8 01       	movw	r30, r16
 565 
 368:	f8 01       	movw	r30, r16
566 
 36a:	e6 0f       	add	r30, r22
 566 
 36a:	e6 0f       	add	r30, r22
567 
 36c:	f1 1d       	adc	r31, r1
 567 
 36c:	f1 1d       	adc	r31, r1
568 
 36e:	f0 80       	ld	r15, Z
 568 
 36e:	f0 80       	ld	r15, Z
569 
 370:	6f 5f       	subi	r22, 0xFF	; 255
 569 
 370:	6f 5f       	subi	r22, 0xFF	; 255
570 
 372:	71 50       	subi	r23, 0x01	; 1
 570 
 372:	71 50       	subi	r23, 0x01	; 1
571 
   TxdBuffer[pt++] = '=' + (a >> 2);
 571 
   TxdBuffer[pt++] = '=' + (a >> 2);
572 
 374:	89 2f       	mov	r24, r25
 572 
 374:	89 2f       	mov	r24, r25
573 
 376:	86 95       	lsr	r24
 573 
 376:	86 95       	lsr	r24
574 
 378:	86 95       	lsr	r24
 574 
 378:	86 95       	lsr	r24
575 
 37a:	83 5c       	subi	r24, 0xC3	; 195
 575 
 37a:	83 5c       	subi	r24, 0xC3	; 195
576 
 37c:	fd 01       	movw	r30, r26
 576 
 37c:	fd 01       	movw	r30, r26
577 
 37e:	ec 0f       	add	r30, r28
 577 
 37e:	ec 0f       	add	r30, r28
578 
 380:	fd 1f       	adc	r31, r29
 578 
 380:	fd 1f       	adc	r31, r29
579 
 382:	80 83       	st	Z, r24
 579 
 382:	80 83       	st	Z, r24
580 
 384:	fd 01       	movw	r30, r26
 580 
 384:	fd 01       	movw	r30, r26
581 
 386:	31 96       	adiw	r30, 0x01	; 1
 581 
 386:	31 96       	adiw	r30, 0x01	; 1
582 
   TxdBuffer[pt++] = '=' + (((a & 0x03) << 4) | ((b & 0xf0) >> 4));
 582 
   TxdBuffer[pt++] = '=' + (((a & 0x03) << 4) | ((b & 0xf0) >> 4));
583 
 388:	55 27       	eor	r21, r21
 583 
 388:	55 27       	eor	r21, r21
584 
 38a:	89 2f       	mov	r24, r25
 584 
 38a:	89 2f       	mov	r24, r25
585 
 38c:	99 27       	eor	r25, r25
 585 
 38c:	99 27       	eor	r25, r25
586 
 38e:	83 70       	andi	r24, 0x03	; 3
 586 
 38e:	83 70       	andi	r24, 0x03	; 3
587 
 390:	90 70       	andi	r25, 0x00	; 0
 587 
 390:	90 70       	andi	r25, 0x00	; 0
588 
 392:	82 95       	swap	r24
 588 
 392:	82 95       	swap	r24
589 
 394:	92 95       	swap	r25
 589 
 394:	92 95       	swap	r25
590 
 396:	90 7f       	andi	r25, 0xF0	; 240
 590 
 396:	90 7f       	andi	r25, 0xF0	; 240
591 
 398:	98 27       	eor	r25, r24
 591 
 398:	98 27       	eor	r25, r24
592 
 39a:	80 7f       	andi	r24, 0xF0	; 240
 592 
 39a:	80 7f       	andi	r24, 0xF0	; 240
593 
 39c:	98 27       	eor	r25, r24
 593 
 39c:	98 27       	eor	r25, r24
594 
 39e:	9a 01       	movw	r18, r20
 594 
 39e:	9a 01       	movw	r18, r20
595 
 3a0:	32 95       	swap	r19
 595 
 3a0:	32 95       	swap	r19
596 
 3a2:	22 95       	swap	r18
 596 
 3a2:	22 95       	swap	r18
597 
 3a4:	2f 70       	andi	r18, 0x0F	; 15
 597 
 3a4:	2f 70       	andi	r18, 0x0F	; 15
598 
 3a6:	23 27       	eor	r18, r19
 598 
 3a6:	23 27       	eor	r18, r19
599 
 3a8:	3f 70       	andi	r19, 0x0F	; 15
 599 
 3a8:	3f 70       	andi	r19, 0x0F	; 15
600 
 3aa:	23 27       	eor	r18, r19
 600 
 3aa:	23 27       	eor	r18, r19
601 
 3ac:	82 2b       	or	r24, r18
 601 
 3ac:	82 2b       	or	r24, r18
602 
 3ae:	83 5c       	subi	r24, 0xC3	; 195
 602 
 3ae:	83 5c       	subi	r24, 0xC3	; 195
603 
 3b0:	ec 0f       	add	r30, r28
 603 
 3b0:	ec 0f       	add	r30, r28
604 
 3b2:	fd 1f       	adc	r31, r29
 604 
 3b2:	fd 1f       	adc	r31, r29
605 
 3b4:	80 83       	st	Z, r24
 605 
 3b4:	80 83       	st	Z, r24
606 
 3b6:	fd 01       	movw	r30, r26
 606 
 3b6:	fd 01       	movw	r30, r26
607 
 3b8:	32 96       	adiw	r30, 0x02	; 2
 607 
 3b8:	32 96       	adiw	r30, 0x02	; 2
608 
   TxdBuffer[pt++] = '=' + (((b & 0x0f) << 2) | ((c & 0xc0) >> 6));
 608 
   TxdBuffer[pt++] = '=' + (((b & 0x0f) << 2) | ((c & 0xc0) >> 6));
609 
 3ba:	4f 70       	andi	r20, 0x0F	; 15
 609 
 3ba:	4f 70       	andi	r20, 0x0F	; 15
610 
 3bc:	50 70       	andi	r21, 0x00	; 0
 610 
 3bc:	50 70       	andi	r21, 0x00	; 0
611 
 3be:	44 0f       	add	r20, r20
 611 
 3be:	44 0f       	add	r20, r20
612 
 3c0:	55 1f       	adc	r21, r21
 612 
 3c0:	55 1f       	adc	r21, r21
613 
 3c2:	44 0f       	add	r20, r20
 613 
 3c2:	44 0f       	add	r20, r20
614 
 3c4:	55 1f       	adc	r21, r21
 614 
 3c4:	55 1f       	adc	r21, r21
615 
 3c6:	8f 2d       	mov	r24, r15
 615 
 3c6:	8f 2d       	mov	r24, r15
616 
 3c8:	82 95       	swap	r24
 616 
 3c8:	82 95       	swap	r24
617 
 3ca:	86 95       	lsr	r24
 617 
 3ca:	86 95       	lsr	r24
618 
 3cc:	86 95       	lsr	r24
 618 
 3cc:	86 95       	lsr	r24
619 
 3ce:	83 70       	andi	r24, 0x03	; 3
 619 
 3ce:	83 70       	andi	r24, 0x03	; 3
620 
 3d0:	84 2b       	or	r24, r20
 620 
 3d0:	84 2b       	or	r24, r20
621 
 3d2:	83 5c       	subi	r24, 0xC3	; 195
 621 
 3d2:	83 5c       	subi	r24, 0xC3	; 195
622 
 3d4:	ec 0f       	add	r30, r28
 622 
 3d4:	ec 0f       	add	r30, r28
623 
 3d6:	fd 1f       	adc	r31, r29
 623 
 3d6:	fd 1f       	adc	r31, r29
624 
 3d8:	80 83       	st	Z, r24
 624 
 3d8:	80 83       	st	Z, r24
625 
 3da:	fd 01       	movw	r30, r26
 625 
 3da:	fd 01       	movw	r30, r26
626 
 3dc:	33 96       	adiw	r30, 0x03	; 3
 626 
 3dc:	33 96       	adiw	r30, 0x03	; 3
627 
   TxdBuffer[pt++] = '=' + ( c & 0x3f);
 627 
   TxdBuffer[pt++] = '=' + ( c & 0x3f);
628 
 3de:	8f 2d       	mov	r24, r15
 628 
 3de:	8f 2d       	mov	r24, r15
629 
 3e0:	8f 73       	andi	r24, 0x3F	; 63
 629 
 3e0:	8f 73       	andi	r24, 0x3F	; 63
630 
 3e2:	83 5c       	subi	r24, 0xC3	; 195
 630 
 3e2:	83 5c       	subi	r24, 0xC3	; 195
631 
 3e4:	ec 0f       	add	r30, r28
 631 
 3e4:	ec 0f       	add	r30, r28
632 
 3e6:	fd 1f       	adc	r31, r29
 632 
 3e6:	fd 1f       	adc	r31, r29
633 
 3e8:	80 83       	st	Z, r24
 633 
 3e8:	80 83       	st	Z, r24
634 
 3ea:	14 96       	adiw	r26, 0x04	; 4
 634 
 3ea:	14 96       	adiw	r26, 0x04	; 4
635 
 3ec:	77 23       	and	r23, r23
 635 
 3ec:	77 23       	and	r23, r23
636 
 3ee:	09 f0       	breq	.+2      	; 0x3f2 <SendOutData+0xe0>
 636 
 3ee:	09 f0       	breq	.+2      	; 0x3f2 <SendOutData+0xe0>
637 
 3f0:	a8 cf       	rjmp	.-176    	; 0x342 <SendOutData+0x30>
 637 
 3f0:	a8 cf       	rjmp	.-176    	; 0x342 <SendOutData+0x30>
638 
  }
 638 
  }
639 
 AddCRC(pt);
 639 
 AddCRC(pt);
640 
 3f2:	cd 01       	movw	r24, r26
 640 
 3f2:	cd 01       	movw	r24, r26
641 
 3f4:	51 df       	rcall	.-350    	; 0x298 <AddCRC>
 641 
 3f4:	51 df       	rcall	.-350    	; 0x298 <AddCRC>
642 
 3f6:	df 91       	pop	r29
 642 
 3f6:	df 91       	pop	r29
643 
 3f8:	cf 91       	pop	r28
 643 
 3f8:	cf 91       	pop	r28
644 
 3fa:	1f 91       	pop	r17
 644 
 3fa:	1f 91       	pop	r17
645 
 3fc:	0f 91       	pop	r16
 645 
 3fc:	0f 91       	pop	r16
646 
 3fe:	ff 90       	pop	r15
 646 
 3fe:	ff 90       	pop	r15
647 
 400:	08 95       	ret
 647 
 400:	08 95       	ret
648 
 
 648 
 
649 
00000402 <main>:
 649 
00000402 <main>:
650 
}
 650 
}
651 
 
 651 
 
652 
 
 652 
 
653 
//-----------------------------------------------------------------------------
 653 
//-----------------------------------------------------------------------------
654 
//main
654 
//main
655 
//main execution loop
 655 
//main execution loop
656 
//-----------------------------------------------------------------------------
 656 
//-----------------------------------------------------------------------------
657 
int main(void)
 657 
int main(void)
658 
{
 658 
{
659 
 402:	0f 93       	push	r16
 659 
 402:	0f 93       	push	r16
660 
 404:	1f 93       	push	r17
 660 
 404:	1f 93       	push	r17
661 
 406:	cf 93       	push	r28
 661 
 406:	cf 93       	push	r28
662 
 408:	df 93       	push	r29
 662 
 408:	df 93       	push	r29
663
663
664 
	// int message structures;
 664 
	// int message structures;
665 
	VersionInfo.identifier	= XIDENTIFIER_VERSION;
 665 
	VersionInfo.identifier		= XIDENTIFIER_VERSION;
666 
 40a:	81 e0       	ldi	r24, 0x01	; 1
 666 
 40a:	81 e0       	ldi	r24, 0x01	; 1
667 
 40c:	80 93 6e 00 	sts	0x006E, r24
 667 
 40c:	80 93 6e 00 	sts	0x006E, r24
668 
	VersionInfo.majorversion = MAJORVERSION;
 668 
	VersionInfo.majorversion 	= MAJORVERSION;
669 
 410:	10 92 6f 00 	sts	0x006F, r1
 669 
 410:	10 92 6f 00 	sts	0x006F, r1
670 
	VersionInfo.minorversion = MINORVERSION;
670 
	VersionInfo.minorversion 	= MINORVERSION;
671 
 414:	80 93 70 00 	sts	0x0070, r24
 671 
 414:	80 93 70 00 	sts	0x0070, r24
- 
 
 672
672 
	AnalogData.identifier 	= XIDENTIFIER_ANALOG;
673 
	AnalogData.identifier 		= XIDENTIFIER_ANALOG;
673 
 418:	82 e0       	ldi	r24, 0x02	; 2
 674 
 418:	82 e0       	ldi	r24, 0x02	; 2
674 
 41a:	80 93 3b 01 	sts	0x013B, r24
 675 
 41a:	80 93 3b 01 	sts	0x013B, r24
- 
 
 676
675 
	Exception.identifier 	= XIDENTIFIER_EXCEPTION;
677 
	Exception.identifier 		= XIDENTIFIER_EXCEPTION;
676 
 41e:	10 92 71 00 	sts	0x0071, r1
 678 
 41e:	10 92 71 00 	sts	0x0071, r1
677 
 
 679 
 
678 
	// PORT D - unused right now
680 
	// PORT D - unused right now
679 
	PORTD = 0x10;
681 
	PORTD = 0x10;
680 
 422:	80 e1       	ldi	r24, 0x10	; 16
 682 
 422:	80 e1       	ldi	r24, 0x10	; 16
681 
 424:	82 bb       	out	0x12, r24	; 18
 683 
 424:	82 bb       	out	0x12, r24	; 18
682 
	DDRD  = 0x00;
684 
	DDRD  = 0x00;
683 
 426:	11 ba       	out	0x11, r1	; 17
 685 
 426:	11 ba       	out	0x11, r1	; 17
684 
 
 686 
 
685 
	//Enable TXEN im Register UCR TX-Data Enable & RX Enable
 687 
	//Enable TXEN im Register UCR TX-Data Enable & RX Enable
686 
 
 688 
 
687 
	// USART initialization
 689 
	// USART initialization
688 
	// Communication Parameters: 8 Data, 1 Stop, No Parity
 690 
	// Communication Parameters: 8 Data, 1 Stop, No Parity
689 
	// USART Receiver: On
 691 
	// USART Receiver: On
690 
	// USART Transmitter: On
 692 
	// USART Transmitter: On
691 
	// USART RX/TX interrupt enable
 693 
	// USART RX/TX interrupt enable
692 
	// USART Mode: Asynchronous
 694 
	// USART Mode: Asynchronous
693 
	// USART Baud rate: 57600
695 
	// USART Baud rate: 57600
694 
	UCSRA=0x00;
 696 
	UCSRA=0x00;
695 
 428:	1b b8       	out	0x0b, r1	; 11
 697 
 428:	1b b8       	out	0x0b, r1	; 11
696 
	UCSRB=0xD8;
 698 
	UCSRB=0xD8;
697 
 42a:	88 ed       	ldi	r24, 0xD8	; 216
 699 
 42a:	88 ed       	ldi	r24, 0xD8	; 216
698 
 42c:	8a b9       	out	0x0a, r24	; 10
 700 
 42c:	8a b9       	out	0x0a, r24	; 10
699 
	UCSRC=0x86;
 701 
	UCSRC=0x86;
700 
 42e:	86 e8       	ldi	r24, 0x86	; 134
 702 
 42e:	86 e8       	ldi	r24, 0x86	; 134
701 
 430:	80 bd       	out	0x20, r24	; 32
 703 
 430:	80 bd       	out	0x20, r24	; 32
702 
#ifdef CPUSPEED_20 	//20.000MHz
 704 
#ifdef CPUSPEED_20 	//20.000MHz
703 
	UBRRH=0x00;
 705 
	UBRRH=0x00;
704 
	UBRRL=0x15;
706 
	UBRRL=0x15;
705 
#endif
 707 
#endif
706 
 
 708 
 
707 
#ifdef CPUSPEED_16 	//16.000MHz
 709 
#ifdef CPUSPEED_16 	//16.000MHz
708 
	UBRRH=0x00;
 710 
	UBRRH=0x00;
709 
	UBRRL=0x10;
 711 
	UBRRL=0x10;
710 
#endif
 712 
#endif
711
713
712 
#ifdef CPUSPEED_11059 //11.059MHz
 714 
#ifdef CPUSPEED_11059 //11.059MHz
713 
	UBRRH=0x00;
 715 
	UBRRH=0x00;
714 
 432:	10 bc       	out	0x20, r1	; 32
 716 
 432:	10 bc       	out	0x20, r1	; 32
715 
	UBRRL=0x0B;
 717 
	UBRRL=0x0B;
716 
 434:	8b e0       	ldi	r24, 0x0B	; 11
 718 
 434:	8b e0       	ldi	r24, 0x0B	; 11
717 
 436:	89 b9       	out	0x09, r24	; 9
 719 
 436:	89 b9       	out	0x09, r24	; 9
718 
#endif
 720 
#endif
719 
 
 721 
 
720 
 
 722 
 
721 
	// Enable interrupts
 723 
	// Enable interrupts
722 
	sei();
 724 
	sei();
723 
 438:	78 94       	sei
 725 
 438:	78 94       	sei
724 
 
 726 
 
725 
	NeuerDatensatzEmpfangen = 0;
727 
	NeuerDatensatzEmpfangen = 0;
726 
 43a:	10 92 63 00 	sts	0x0063, r1
 728 
 43a:	10 92 63 00 	sts	0x0063, r1
727 
 43e:	0e e6       	ldi	r16, 0x6E	; 110
 729 
 43e:	0e e6       	ldi	r16, 0x6E	; 110
728 
 440:	10 e0       	ldi	r17, 0x00	; 0
 730 
 440:	10 e0       	ldi	r17, 0x00	; 0
729 
 442:	c1 e7       	ldi	r28, 0x71	; 113
 731 
 442:	c1 e7       	ldi	r28, 0x71	; 113
730 
 444:	d0 e0       	ldi	r29, 0x00	; 0
 732 
 444:	d0 e0       	ldi	r29, 0x00	; 0
731 
 
 733 
 
732 
	// main loop
734 
	// main loop
733 
	while (1)
 735 
	while (1)
734 
	{
 736 
	{
735 
		if(NeuerDatensatzEmpfangen==1) {
 737 
		if(NeuerDatensatzEmpfangen==1) {
736 
 446:	80 91 63 00 	lds	r24, 0x0063
 738 
 446:	80 91 63 00 	lds	r24, 0x0063
737 
 44a:	81 30       	cpi	r24, 0x01	; 1
 739 
 44a:	81 30       	cpi	r24, 0x01	; 1
738 
 44c:	e1 f7       	brne	.-8      	; 0x446 <main+0x44>
 740 
 44c:	e1 f7       	brne	.-8      	; 0x446 <main+0x44>
739 
			switch(RxdBuffer[3])
 741 
			switch(RxdBuffer[3])
740 
 44e:	80 91 76 00 	lds	r24, 0x0076
 742 
 44e:	80 91 76 00 	lds	r24, 0x0076
741 
 452:	81 30       	cpi	r24, 0x01	; 1
 743 
 452:	81 30       	cpi	r24, 0x01	; 1
742 
 454:	19 f0       	breq	.+6      	; 0x45c <main+0x5a>
 744 
 454:	19 f0       	breq	.+6      	; 0x45c <main+0x5a>
743 
 456:	82 30       	cpi	r24, 0x02	; 2
 745 
 456:	82 30       	cpi	r24, 0x02	; 2
744 
 458:	39 f4       	brne	.+14     	; 0x468 <__stack+0x9>
 746 
 458:	39 f4       	brne	.+14     	; 0x468 <__stack+0x9>
745 
 45a:	0d c0       	rjmp	.+26     	; 0x476 <__stack+0x17>
 747 
 45a:	0d c0       	rjmp	.+26     	; 0x476 <__stack+0x17>
746 
			{
 748 
			{
747 
				// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
749 
				// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
748 
				// version request
 750 
				// version request
749 
				case XIDENTIFIER_VERSION:
 751 
				case XIDENTIFIER_VERSION:
750 
					SendOutData('X',0x00,(unsigned char *) &VersionInfo,sizeof(VersionInfo));
 752 
					SendOutData('X',0x00,(unsigned char *) &VersionInfo,sizeof(VersionInfo));
751 
 45c:	23 e0       	ldi	r18, 0x03	; 3
 753 
 45c:	23 e0       	ldi	r18, 0x03	; 3
752 
 45e:	a8 01       	movw	r20, r16
 754 
 45e:	a8 01       	movw	r20, r16
753 
 460:	60 e0       	ldi	r22, 0x00	; 0
 755 
 460:	60 e0       	ldi	r22, 0x00	; 0
754 
 462:	88 e5       	ldi	r24, 0x58	; 88
 756 
 462:	88 e5       	ldi	r24, 0x58	; 88
755 
 464:	56 df       	rcall	.-340    	; 0x312 <SendOutData>
 757 
 464:	56 df       	rcall	.-340    	; 0x312 <SendOutData>
756 
 466:	07 c0       	rjmp	.+14     	; 0x476 <__stack+0x17>
 758 
 466:	07 c0       	rjmp	.+14     	; 0x476 <__stack+0x17>
757 
					break;
759 
					break;
758 
				// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
760 
				// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
759 
				case XIDENTIFIER_ANALOG:
 761 
				case XIDENTIFIER_ANALOG:
760 
					break;
 762 
					break;
761 
				// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
763 
				// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
762 
				default:
764 
				default:
763 
					Exception.errorcode = ERRORCODE_NOTIMPLEMENTED;
 765 
					Exception.errorcode = ERRORCODE_NOTIMPLEMENTED;
764 
 468:	10 92 72 00 	sts	0x0072, r1
 766 
 468:	10 92 72 00 	sts	0x0072, r1
765 
					SendOutData('X',0x00,(unsigned char *) &Exception,sizeof(VersionInfo));
 767 
					SendOutData('X',0x00,(unsigned char *) &Exception,sizeof(VersionInfo));
766 
 46c:	23 e0       	ldi	r18, 0x03	; 3
 768 
 46c:	23 e0       	ldi	r18, 0x03	; 3
767 
 46e:	ae 01       	movw	r20, r28
 769 
 46e:	ae 01       	movw	r20, r28
768 
 470:	60 e0       	ldi	r22, 0x00	; 0
 770 
 470:	60 e0       	ldi	r22, 0x00	; 0
769 
 472:	88 e5       	ldi	r24, 0x58	; 88
 771 
 472:	88 e5       	ldi	r24, 0x58	; 88
770 
 474:	4e df       	rcall	.-356    	; 0x312 <SendOutData>
 772 
 474:	4e df       	rcall	.-356    	; 0x312 <SendOutData>
771 
			}
 773 
			}
772 
			NeuerDatensatzEmpfangen=0;
 774 
			NeuerDatensatzEmpfangen=0;
773 
 476:	10 92 63 00 	sts	0x0063, r1
 775 
 476:	10 92 63 00 	sts	0x0063, r1
774 
 47a:	e5 cf       	rjmp	.-54     	; 0x446 <main+0x44>
 776 
 47a:	e5 cf       	rjmp	.-54     	; 0x446 <main+0x44>
775 
 
 777 
 
776 
0000047c <_exit>:
 778 
0000047c <_exit>:
777 
 47c:	ff cf       	rjmp	.-2      	; 0x47c <_exit>
 779 
 47c:	ff cf       	rjmp	.-2      	; 0x47c <_exit>