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| Rev 273 | Rev 275 | ||
|---|---|---|---|
| Line 20... | Line 20... | ||
| 20 | DDRA = 0x00; |
20 | DDRA = 0x00; |
| 21 | PORTA = 0x00; |
21 | PORTA = 0x00; |
| 22 | // Digital Input Disable Register 0 |
22 | // Digital Input Disable Register 0 |
| 23 | // Disable digital input buffer for analog adc_channel pins |
23 | // Disable digital input buffer for analog adc_channel pins |
| 24 | DIDR0 = 0xFF; |
24 | DIDR0 = 0xFF; |
| 25 | // external reference, adjust data to the right |
25 | // external reference AREF, adjust data to the right |
| 26 | ADMUX &= ~((1 << REFS1)|(1 << REFS0)|(1 << ADLAR)); |
26 | ADMUX &= ~((1 << REFS1)|(1 << REFS0)|(1 << ADLAR)); |
| 27 | // set muxer to ADC adc_channel 0 (0 to 7 is a valid choice) |
27 | // set muxer to ADC adc_channel 0 (0 to 7 is a valid choice) |
| 28 | ADMUX = (ADMUX & 0xE0) | 0x00; |
28 | ADMUX = (ADMUX & 0xE0) | 0x00; |
| 29 | //Set ADC Control and Status Register A |
29 | //Set ADC Control and Status Register A |
| 30 | //Auto Trigger Enable, Prescaler Select Bits to Division Factor 128, i.e. ADC clock = SYSCKL/128 = 156.25 kHz |
30 | //Auto Trigger Enable, Prescaler Select Bits to Division Factor 128, i.e. ADC clock = SYSCKL/128 = 156.25 kHz |