WebSVN - Projects - Diff - Rev 514 and 728


/****************************************************************************
 *   Copyright (C) 2009-2010 by Claas Anders "CaScAdE" Rathje               *
 *   admiralcascade@gmail.com                                               *
 *   Project-URL: http://www.mylifesucks.de/oss/c-osd/                      *
 *                                                                          *
 *   This program is free software; you can redistribute it and/or modify   *
 *   it under the terms of the GNU General Public License as published by   *
 *   the Free Software Foundation; either version 2 of the License.         *
 *                                                                          *
 *   This program is distributed in the hope that it will be useful,        *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of         *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the          *
 *   GNU General Public License for more details.                           *
 *                                                                          *
 *   You should have received a copy of the GNU General Public License      *
 *   along with this program; if not, write to the                          *
 *   Free Software Foundation, Inc.,                                        *
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.              *
 ****************************************************************************/
 
#include <avr/io.h>
#include <avr/interrupt.h>
#include "spi.h"
#include "main.h"
 
#if !(ALLCHARSDEBUG|(WRITECHARS != -1))
 
volatile uint16_t icnt = 0;
volatile uint8_t request_count = 0;
volatile uint8_t spi_ready = 1;
volatile union SPI_buffer_t SPI_buffer;
int16_t ampere = 0, max_ampere = 0, s_volt;
int32_t ampere_wasted = 0;
 
#define INT0_HIGH                       PORTD |=  (1 << PD2);
#define INT0_LOW                        PORTD &= ~(1 << PD2);
 
/**
 * init the SPI as master
 */
void SpiMasterInit(void) {
    volatile char IOReg;
    // set PB4(/SS), PB5(MOSI), PB7(SCK) as output
    DDRB = (1 << PB4) | (1 << PB5) | (1 << PB7);
    PORTB |= (1 << PB4); // pullup SS
    // enable SPI Interrupt and SPI in Master Mode with SCK = CK/128
    SPCR = (1 << SPIE) | (1 << SPE) | (1 << MSTR) | (1 << SPR0) | (1 << SPR1);
    IOReg = SPSR; // clear SPIF bit in SPSR
    IOReg = SPDR;
    //sei(); // we do it later
}
 
 
/**
 * SPI interrupt handler
 */
ISR(SPI_STC_vect) {
        if (request_count == 0) {
                SPI_buffer.buffer.chk = SPDR; // firs char received is check byte from last transfer
        } else {
                SPI_buffer.buffer.c[request_count - 1] = SPDR; // safe received byte to buffer
        }
        request_count++;
    if (--icnt) {
        //SPDR = *iptr; // send next byte
        spi_ready = 1; // we _should_ send later because the slave needs more time
    } else {
        SPCR &= ~_BV(SPIE); // deactivate interrupt
        INT0_HIGH // transfer is done, slave does not need to listen
    }
}
 
/**
 * check if SPI transfer is still busy
 */
int TransferIsBusy(void) {
    return SPCR & _BV(SPIE);
}
 
/**
 * start a new transfer with length <len>
 */
void StartTransfer(uint16_t len) {
    INT0_LOW // /SS LOW ^= SS HIGH ^= slave should listen
 
        // this is a new request
        request_count = 0;
 
    // set up pointer and length for interrupt handler
    icnt = len;
 
    SPCR |= _BV(SPIE); // enable spi interrupt
        SPDR = 'A'; // start transfer by first command char
}
 
/**
 * send next command through spi
 */
void spi_send_next() {
        SPDR = 'A' + request_count;
}
 
#endif
 

Rev 514	Rev 728
1	/****************************************************************************	1	/****************************************************************************
2	* Copyright (C) 2009 by Claas Anders "CaScAdE" Rathje *	2	* Copyright (C) 2009-2010 by Claas Anders "CaScAdE" Rathje *
3	* admiralcascade@gmail.com *	3	* admiralcascade@gmail.com *
4	* Project-URL: http://www.mylifesucks.de/oss/c-osd/ *	4	* Project-URL: http://www.mylifesucks.de/oss/c-osd/ *
5	* *	5	* *
6	* This program is free software; you can redistribute it and/or modify *	6	* This program is free software; you can redistribute it and/or modify *
7	* it under the terms of the GNU General Public License as published by *	7	* it under the terms of the GNU General Public License as published by *
8	* the Free Software Foundation; either version 2 of the License. *	8	* the Free Software Foundation; either version 2 of the License. *
9	* *	9	* *
10	* This program is distributed in the hope that it will be useful, *	10	* This program is distributed in the hope that it will be useful, *
11	* but WITHOUT ANY WARRANTY; without even the implied warranty of *	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of *
12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13	* GNU General Public License for more details. *	13	* GNU General Public License for more details. *
14	* *	14	* *
15	* You should have received a copy of the GNU General Public License *	15	* You should have received a copy of the GNU General Public License *
16	* along with this program; if not, write to the *	16	* along with this program; if not, write to the *
17	* Free Software Foundation, Inc., *	17	* Free Software Foundation, Inc., *
18	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *	18	* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19	****************************************************************************/	19	****************************************************************************/
20		20
21	#include <avr/io.h>	21	#include <avr/io.h>
22	#include <avr/interrupt.h>	22	#include <avr/interrupt.h>
23	#include "spi.h"	23	#include "spi.h"
24	#include "main.h"	24	#include "main.h"
25		25
26	#if !(ALLCHARSDEBUG\|(WRITECHARS != -1))	26	#if !(ALLCHARSDEBUG\|(WRITECHARS != -1))
27		27
28	volatile uint16_t icnt = 0;	28	volatile uint16_t icnt = 0;
29	volatile uint8_t request_count = 0;	29	volatile uint8_t request_count = 0;
30	volatile uint8_t spi_ready = 1;	30	volatile uint8_t spi_ready = 1;
31	volatile union SPI_buffer_t SPI_buffer;	31	volatile union SPI_buffer_t SPI_buffer;
32	int16_t ampere = 0, max_ampere = 0, s_volt;	32	int16_t ampere = 0, max_ampere = 0, s_volt;
33	int32_t ampere_wasted = 0;	33	int32_t ampere_wasted = 0;
34		34
35	#define INT0_HIGH PORTD \|= (1 << PD2);	35	#define INT0_HIGH PORTD \|= (1 << PD2);
36	#define INT0_LOW PORTD &= ~(1 << PD2);	36	#define INT0_LOW PORTD &= ~(1 << PD2);
37		37
38	/**	38	/**
39	* init the SPI as master	39	* init the SPI as master
40	*/	40	*/
41	void SpiMasterInit(void) {	41	void SpiMasterInit(void) {
42	volatile char IOReg;	42	volatile char IOReg;
43	// set PB4(/SS), PB5(MOSI), PB7(SCK) as output	43	// set PB4(/SS), PB5(MOSI), PB7(SCK) as output
44	DDRB = (1 << PB4) \| (1 << PB5) \| (1 << PB7);	44	DDRB = (1 << PB4) \| (1 << PB5) \| (1 << PB7);
45	PORTB \|= (1 << PB4); // pullup SS	45	PORTB \|= (1 << PB4); // pullup SS
46	// enable SPI Interrupt and SPI in Master Mode with SCK = CK/128	46	// enable SPI Interrupt and SPI in Master Mode with SCK = CK/128
47	SPCR = (1 << SPIE) \| (1 << SPE) \| (1 << MSTR) \| (1 << SPR0) \| (1 << SPR1);	47	SPCR = (1 << SPIE) \| (1 << SPE) \| (1 << MSTR) \| (1 << SPR0) \| (1 << SPR1);
48	IOReg = SPSR; // clear SPIF bit in SPSR	48	IOReg = SPSR; // clear SPIF bit in SPSR
49	IOReg = SPDR;	49	IOReg = SPDR;
50	//sei(); // we do it later	50	//sei(); // we do it later
51	}	51	}
52		52
53		53
54	/**	54	/**
55	* SPI interrupt handler	55	* SPI interrupt handler
56	*/	56	*/
57	ISR(SPI_STC_vect) {	57	ISR(SPI_STC_vect) {
58	if (request_count == 0) {	58	if (request_count == 0) {
59	SPI_buffer.buffer.chk = SPDR; // firs char received is check byte from last transfer	59	SPI_buffer.buffer.chk = SPDR; // firs char received is check byte from last transfer
60	} else {	60	} else {
61	SPI_buffer.buffer.c[request_count - 1] = SPDR; // safe received byte to buffer	61	SPI_buffer.buffer.c[request_count - 1] = SPDR; // safe received byte to buffer
62	}	62	}
63	request_count++;	63	request_count++;
64	if (--icnt) {	64	if (--icnt) {
65	//SPDR = *iptr; // send next byte	65	//SPDR = *iptr; // send next byte
66	spi_ready = 1; // we _should_ send later because the slave needs more time	66	spi_ready = 1; // we _should_ send later because the slave needs more time
67	} else {	67	} else {
68	SPCR &= ~_BV(SPIE); // deactivate interrupt	68	SPCR &= ~_BV(SPIE); // deactivate interrupt
69	INT0_HIGH // transfer is done, slave does not need to listen	69	INT0_HIGH // transfer is done, slave does not need to listen
70	}	70	}
71	}	71	}
72		72
73	/**	73	/**
74	* check if SPI transfer is still busy	74	* check if SPI transfer is still busy
75	*/	75	*/
76	int TransferIsBusy(void) {	76	int TransferIsBusy(void) {
77	return SPCR & _BV(SPIE);	77	return SPCR & _BV(SPIE);
78	}	78	}
79		79
80	/**	80	/**
81	* start a new transfer with length <len>	81	* start a new transfer with length <len>
82	*/	82	*/
83	void StartTransfer(uint16_t len) {	83	void StartTransfer(uint16_t len) {
84	INT0_LOW // /SS LOW ^= SS HIGH ^= slave should listen	84	INT0_LOW // /SS LOW ^= SS HIGH ^= slave should listen
85		85
86	// this is a new request	86	// this is a new request
87	request_count = 0;	87	request_count = 0;
88		88
89	// set up pointer and length for interrupt handler	89	// set up pointer and length for interrupt handler
90	icnt = len;	90	icnt = len;
91		91
92	SPCR \|= _BV(SPIE); // enable spi interrupt	92	SPCR \|= _BV(SPIE); // enable spi interrupt
93	SPDR = 'A'; // start transfer by first command char	93	SPDR = 'A'; // start transfer by first command char
94	}	94	}
95		95
96	/**	96	/**
97	* send next command through spi	97	* send next command through spi
98	*/	98	*/
99	void spi_send_next() {	99	void spi_send_next() {
100	SPDR = 'A' + request_count;	100	SPDR = 'A' + request_count;
101	}	101	}
102		102
103	#endif	103	#endif
104		104

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