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Line 134... | Line 134... | ||
134 | /****************************************************************/ |
134 | /****************************************************************/ |
135 | /* Initialization of the USART0 */ |
135 | /* Initialization of the USART0 */ |
136 | /****************************************************************/ |
136 | /****************************************************************/ |
137 | void USART0_Init (void) |
137 | void USART0_Init (void) |
138 | { |
138 | { |
139 | uint8_t sreg = SREG; |
- | |
140 | - | ||
141 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * BAUD_RATE) - 1); |
139 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * BAUD_RATE) - 1); |
Line 142... | Line 140... | ||
142 | 140 | ||
143 | // disable all interrupts before configuration |
141 | // disable all interrupts before configuration |
Line 148... | Line 146... | ||
148 | // disable TX-Interrupt |
146 | // disable TX-Interrupt |
149 | UCSR0B &= ~(1 << TXCIE0); |
147 | UCSR0B &= ~(1 << TXCIE0); |
Line 150... | Line 148... | ||
150 | 148 | ||
Line 151... | Line 149... | ||
151 | // set direction of RXD0 and TXD0 pins |
149 | // set direction of RXD0 and TXD0 pins |
152 | - | ||
153 | // set RXD0 (PD0) as an input pin |
150 | |
- | 151 | // set RXD0 (PD0) as an input pin tristate |
|
154 | PORTD |= (1 << PORTD0); |
152 | DDRD &= ~(1 << DDD0); |
155 | DDRD &= ~(1 << DDD0); |
- | |
156 | // set TXD0 (PD1) as an output pin |
153 | PORTD &= ~(1 << PORTD0); |
- | 154 | // set TXD0 (PD1) as an output pin |
|
- | 155 | DDRD |= (1 << DDD1); |
|
Line 157... | Line 156... | ||
157 | PORTD |= (1 << PORTD1); |
156 | PORTD &= ~(1 << PORTD1); |
158 | DDRD |= (1 << DDD1); |
157 | |
159 | 158 | ||
160 | // USART0 Baud Rate Register |
159 | // USART0 Baud Rate Register |
Line 161... | Line 160... | ||
161 | // set clock divider |
160 | // set clock divider |
Line 162... | Line 161... | ||
162 | UBRR0H = (uint8_t)(ubrr >> 8); |
161 | UBRR0H = (uint8_t)(ubrr >> 8); |
163 | UBRR0L = (uint8_t)ubrr; |
162 | UBRR0L = (uint8_t)ubrr; |
164 | - | ||
165 | // USART0 Control and Status Register A, B, C |
- | |
- | 163 | ||
166 | 164 | // USART0 Control and Status Register A, B, C |
|
167 | // enable double speed operation |
165 | |
168 | UCSR0A |= (1 << U2X0); |
166 | // enable double speed operation |
169 | // enable receiver and transmitter |
167 | UCSR0A |= (1 << U2X0); |
170 | UCSR0B |= (1 << TXEN0) | (1 << RXEN0); |
168 | |
Line 179... | Line 177... | ||
179 | // 8-bit |
177 | // 8-bit |
180 | UCSR0B &= ~(1 << UCSZ02); |
178 | UCSR0B &= ~(1 << UCSZ02); |
181 | UCSR0C |= (1 << UCSZ01); |
179 | UCSR0C |= (1 << UCSZ01); |
182 | UCSR0C |= (1 << UCSZ00); |
180 | UCSR0C |= (1 << UCSZ00); |
Line -... | Line 181... | ||
- | 181 | ||
- | 182 | // enable receiver and transmitter |
|
- | 183 | UCSR0B |= (1 << RXEN0); |
|
- | 184 | UCSR0B |= (1 << TXEN0); |
|
183 | 185 | ||
184 | // flush receive buffer |
186 | // flush receive buffer |
Line 185... | Line -... | ||
185 | while ( UCSR0A & (1<<RXC0) ) UDR0; |
- | |
186 | 187 | while ( UCSR0A & (1<<RXC0) ) UDR0; |
|
187 | // enable interrupts at the end |
188 | |
188 | // enable RX-Interrupt |
189 | // enable RX-Interrupt |
189 | UCSR0B |= (1 << RXCIE0); |
190 | UCSR0B |= (1 << RXCIE0); |
Line 190... | Line 191... | ||
190 | // enable TX-Interrupt |
191 | // enable TX-Interrupt |
191 | UCSR0B |= (1 << TXCIE0); |
192 | UCSR0B |= (1 << TXCIE0); |
Line 192... | Line -... | ||
192 | - | ||
193 | rxd_buffer_locked = FALSE; |
- | |
194 | txd_complete = TRUE; |
- | |
195 | - | ||
196 | Debug_Timer = SetDelay(200); |
- | |
Line 197... | Line 193... | ||
197 | 193 | ||
198 | 194 | rxd_buffer_locked = FALSE; |
|
199 | // restore global interrupt flags |
195 | txd_complete = TRUE; |
Line -... | Line 196... | ||
- | 196 | ||
200 | SREG = sreg; |
197 | |
- | 198 | VersionInfo.Major = VERSION_MAJOR; |
|
- | 199 | VersionInfo.Minor = VERSION_MINOR; |
|
- | 200 | VersionInfo.PCCompatible = VERSION_COMPATIBLE; |
|
- | 201 | ||
- | 202 | ||
- | 203 | // Version beim Start ausgeben (nicht schön, aber geht... ) |
|
201 | 204 | uart_putchar ('\n'); |
|
202 | VersionInfo.Major = VERSION_MAJOR; |
205 | uart_putchar ('C'); |
203 | VersionInfo.Minor = VERSION_MINOR; |
206 | uart_putchar ('P'); |
204 | VersionInfo.PCCompatible = VERSION_COMPATIBLE; |
207 | uart_putchar (':'); |
Line 205... | Line 208... | ||
205 | 208 | uart_putchar ('V'); |
|
206 | // Version beim Start ausgeben (nicht schön, aber geht... ) |
209 | uart_putchar (0x30 + VERSION_MAJOR); |
207 | uart_putchar ('\n');uart_putchar ('C');uart_putchar ('P');uart_putchar (':'); |
210 | uart_putchar ('.');uart_putchar (0x30 + VERSION_MINOR/10); |
208 | uart_putchar ('V');uart_putchar (0x30 + VERSION_MAJOR);uart_putchar ('.');uart_putchar (0x30 + VERSION_MINOR/10); uart_putchar (0x30 + VERSION_MINOR%10); |
- | |
209 | uart_putchar ('\n'); |
211 | uart_putchar (0x30 + VERSION_MINOR%10); |
- | 212 | uart_putchar ('\n'); |
|
210 | } |
213 | } |
- | 214 | ||
211 | 215 | // --------------------------------------------------------------------------------- |
|
Line 212... | Line 216... | ||
212 | // --------------------------------------------------------------------------------- |
216 | void USART0_EnableTXD(void) |
213 | void USART0_EnableTXD(void) |
217 | { |
214 | { |
218 | DDRD |= (1<<DDD1); // set TXD pin as output |
215 | //if(!(UCSR0B & (1 << TXEN0))) return; |
- | |
216 | DDRD |= (1<<DDD1); // set TXD pin as output |
219 | PORTD &= ~(1 << PORTD1); |
Line -... | Line 220... | ||
- | 220 | UCSR0B |= (1 << TXEN0); // enable TX in USART |
|
217 | UCSR0B |= (1 << TXEN0); // enable TX in USART |
221 | UCSR0B |= (1 << TXCIE0); // disable TX-Interrupt |
218 | } |
222 | } |
- | 223 | ||
219 | 224 | // --------------------------------------------------------------------------------- |
|
Line 220... | Line 225... | ||
220 | // --------------------------------------------------------------------------------- |
225 | void USART0_DisableTXD(void) |
221 | void USART0_DisableTXD(void) |
226 | { |
222 | { |
227 | while(!txd_complete){ }; |