Rev 22 | Rev 24 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 22 | Rev 23 | ||
|---|---|---|---|
| Line 62... | Line 62... | ||
| 62 | #include "main.h" |
62 | #include "main.h" |
| 63 | #include "timer0.h" |
63 | #include "timer0.h" |
| 64 | #include "led.h" |
64 | #include "led.h" |
| Line 65... | Line 65... | ||
| 65 | 65 | ||
| 66 | 66 | ||
| 67 | uint8_t I2C_RxBufferSize = 0, I2C_TxBufferSize = 0; |
67 | volatile uint8_t I2C_RxBufferSize = 0, I2C_TxBufferSize = 0; |
| Line 68... | Line 68... | ||
| 68 | uint8_t *I2C_TxBuffer = 0, *I2C_RxBuffer = 0; |
68 | volatile uint8_t *I2C_TxBuffer = 0, *I2C_RxBuffer = 0; |
| 69 | uint8_t Tx_Idx = 0, Rx_Idx = 0; |
69 | volatile uint8_t Tx_Idx = 0, Rx_Idx = 0; |
| 70 | 70 | ||
| 71 | - | ||
| 72 | 71 | ||
| 73 | I2C_Heading_t I2C_Heading; |
72 | |
| Line 74... | Line 73... | ||
| 74 | I2C_WriteAttitude_t I2C_WriteAttitude; |
73 | struct I2C_Heading_t I2C_Heading; |
| 75 | I2C_Mag_t I2C_Mag; |
74 | struct I2C_WriteAttitude_t I2C_WriteAttitude; |
| Line 88... | Line 87... | ||
| 88 | // disable global interrupts |
87 | // disable global interrupts |
| 89 | cli(); |
88 | cli(); |
| Line 90... | Line 89... | ||
| 90 | 89 | ||
| Line 91... | Line 90... | ||
| 91 | // SCK/SCL and MISO/SDA are at put together on the same connector pin in the schematic |
90 | // SCK/SCL and MISO/SDA are at put together on the same connector pin in the schematic |
| 92 | 91 | ||
| 93 | // set PB4 (SCK) and PB5 (MISO) as input tristate |
92 | // set PB4 (SCK) and PB5 (MISO) as input pull up |
| Line 94... | Line 93... | ||
| 94 | DDRB &= ~((1<<DDB4)|(1<<DDB5)); |
93 | DDRB &= ~((1<<DDB4)|(1<<DDB5)); |
| 95 | PORTB &= ~((1<<PORTB4)|(1<<PORTB5)); |
94 | PORTB |= ((1<<PORTB4)|(1<<PORTB5)); |
| 96 | 95 | ||
| Line 117... | Line 116... | ||
| 117 | // enable TWI Acknowledge Bit (TWEA = 1) |
116 | // enable TWI Acknowledge Bit (TWEA = 1) |
| 118 | // disable TWI START Condition Bit (TWSTA = 0), SLAVE |
117 | // disable TWI START Condition Bit (TWSTA = 0), SLAVE |
| 119 | // disable TWI STOP Condition Bit (TWSTO = 0), SLAVE |
118 | // disable TWI STOP Condition Bit (TWSTO = 0), SLAVE |
| 120 | // enable TWI (TWEN = 1) |
119 | // enable TWI (TWEN = 1) |
| 121 | // enable TWI Interrupt (TWIE = 1) |
120 | // enable TWI Interrupt (TWIE = 1) |
| 122 | TWCR &= ~((1<<TWSTA)|(1<<TWSTO)); |
- | |
| 123 | TWCR |= (1<<TWEA)|(1<<TWEN)|(1<<TWIE); |
121 | TWCR |= (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA)|(0<<TWSTA)|(1<<TWSTO)|(0<<TWWC); |
| 124 | - | ||
| 125 | // update version info |
122 | // update version info |
| 126 | I2C_Version.Major = VERSION_MAJOR; |
123 | I2C_Version.Major = VERSION_MAJOR; |
| 127 | I2C_Version.Minor = VERSION_MINOR; |
124 | I2C_Version.Minor = VERSION_MINOR; |
| 128 | I2C_Version.Compatible = I2C_PROTOCOL_COMP; |
125 | I2C_Version.Compatible = I2C_PROTOCOL_COMP; |
| Line 129... | Line 126... | ||
| 129 | 126 | ||
| 130 | // resore status register |
127 | // resore status register |
| 131 | SREG = sreg; |
128 | SREG = sreg; |
| Line 132... | Line 129... | ||
| 132 | } |
129 | } |
| 133 | 130 | ||
| 134 | // send ACK after recieving a byte / ACK is expected after transmitting a byte |
131 | // send ACK after recieving a byte / ACK is expected after transmitting a byte |
| 135 | #define TWCR_ACK TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(0<<TWWC) |
132 | #define TWCR_ACK TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(0<<TWWC) |
| 136 | // send no ACK after recieving a byte / No ACK is expected after transmitting a byte |
133 | // send no ACK after recieving a byte / No ACK is expected after transmitting a byte |
| 137 | #define TWCR_NACK TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(0<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(0<<TWWC) |
134 | #define TWCR_NACK TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(0<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(0<<TWWC) |
| 138 | // switched to the non adressed slave mode |
135 | // switched to the non adressed slave mode |
| 139 | #define TWCR_RESET TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(0<<TWWC) |
136 | #define TWCR_RESET TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA)|(0<<TWSTA)|(0<<TWSTO)|(0<<TWWC) |
| Line 140... | Line 137... | ||
| 140 | // The bit pattern for TWCR_ACK and TWCR_RESET are equal. This is no errro but used for better understanding. |
137 | // The bit pattern for TWCR_ACK and TWCR_RESET are equal. This is no errro but used for better understanding. |
| 141 | #define TWCR_CLEARBUS TWCR =(1<<TWEA) | (1<<TWSTO) | (1<<TWINT) | (1<<TWEN) | (1<<TWIE) |
138 | #define TWCR_CLEARBUS TWCR = (1<<TWEN)|(1<<TWIE)|(1<<TWINT)|(1<<TWEA)|(0<<TWSTA)|(1<<TWSTO)|(0<<TWWC) |
| 142 | 139 | ||
| - | 140 | ISR (TWI_vect) |
|
| 143 | ISR (TWI_vect) |
141 | { |
| 144 | { |
142 | uint8_t data; |
| 145 | uint8_t data; |
143 | |
| 146 | // check event |
144 | // check event |
| 147 | switch (TW_STATUS) |
145 | switch (TW_STATUS) |
| 148 | { |
146 | { |
| - | 147 | case TW_SR_SLA_ACK: // slave addressed in receiver mode and ack has been returned |
|
| 149 | case TW_SR_SLA_ACK: // slave addressed in receiver mode and ack has been returned |
148 | Rx_Idx = 0xFF; // reset rx buffer pointer |
| Line 150... | Line 149... | ||
| 150 | Rx_Idx = 0xFF; // reset rx buffer pointer |
149 | TWCR_ACK; // trigger receiving of first data byte and send ack afterwards |
| 151 | TWCR_ACK; // trigger receiving of first data byte and send ack afterwards |
150 | LED_GRN_TOGGLE; |
| 152 | return; |
151 | return; |
| Line 158... | Line 157... | ||
| 158 | switch(data) |
157 | switch(data) |
| 159 | { |
158 | { |
| 160 | case I2C_CMD_VERSION: |
159 | case I2C_CMD_VERSION: |
| 161 | I2C_TxBuffer = (uint8_t *)&I2C_Version; |
160 | I2C_TxBuffer = (uint8_t *)&I2C_Version; |
| 162 | I2C_TxBufferSize = sizeof(I2C_Version); |
161 | I2C_TxBufferSize = sizeof(I2C_Version); |
| - | 162 | I2C_RxBuffer = 0; |
|
| 163 | I2C_RxBufferSize = 0; |
163 | I2C_RxBufferSize = 0; |
| 164 | break; |
164 | break; |
| Line 165... | Line -... | ||
| 165 | - | ||
| 166 | case I2C_CMD_WRITE_EEPROM: |
- | |
| 167 | I2C_TxBufferSize = 0; |
- | |
| 168 | I2C_RxBuffer = (uint8_t *)&I2C_WriteEEPROM; |
- | |
| 169 | I2C_RxBufferSize = sizeof(I2C_WriteEEPROM); |
- | |
| 170 | break; |
- | |
| 171 | 165 | ||
| - | 166 | case I2C_CMD_WRITE_CAL: |
|
| 172 | case I2C_CMD_WRITE_CAL: |
167 | I2C_TxBuffer = 0; |
| 173 | I2C_TxBufferSize = 0; |
168 | I2C_TxBufferSize = 0; |
| 174 | I2C_RxBuffer = (uint8_t *)&I2C_WriteCal; |
169 | I2C_RxBuffer = (uint8_t *)&I2C_WriteCal; |
| 175 | I2C_RxBufferSize = sizeof(I2C_WriteCal); |
170 | I2C_RxBufferSize = sizeof(I2C_WriteCal); |
| Line 176... | Line -... | ||
| 176 | break; |
- | |
| 177 | - | ||
| 178 | case I2C_CMD_READ_EEPROM: |
- | |
| 179 | I2C_TxBuffer = (uint8_t *)&I2C_ReadEEPROM.Content; |
- | |
| 180 | I2C_TxBufferSize = 2; |
- | |
| 181 | I2C_RxBuffer = (uint8_t *)&I2C_ReadEEPROM; |
- | |
| 182 | I2C_RxBufferSize = 1; |
- | |
| 183 | break; |
171 | break; |
| 184 | 172 | ||
| 185 | case I2C_CMD_READ_MAG: |
173 | case I2C_CMD_READ_MAG: |
| - | 174 | I2C_TxBuffer = (uint8_t *)&I2C_Mag; |
|
| 186 | I2C_TxBuffer = (uint8_t *)&I2C_Mag; |
175 | I2C_TxBufferSize = sizeof(I2C_Mag); |
| Line 187... | Line 176... | ||
| 187 | I2C_TxBufferSize = sizeof(I2C_Mag); |
176 | I2C_RxBuffer = 0; |
| 188 | I2C_RxBufferSize = 0; |
177 | I2C_RxBufferSize = 0; |
| 189 | 178 | ||
| Line 201... | Line 190... | ||
| 201 | I2C_Heading.Heading = Heading; |
190 | I2C_Heading.Heading = Heading; |
| 202 | // copy current attitude from I2C rx buffer to uart rx buffer (this is used for the calulation of the heading) |
191 | // copy current attitude from I2C rx buffer to uart rx buffer (this is used for the calulation of the heading) |
| 203 | ExternData.Attitude[NICK] = I2C_WriteAttitude.Nick; |
192 | ExternData.Attitude[NICK] = I2C_WriteAttitude.Nick; |
| 204 | ExternData.Attitude[ROLL] = I2C_WriteAttitude.Roll; |
193 | ExternData.Attitude[ROLL] = I2C_WriteAttitude.Roll; |
| 205 | break; |
194 | break; |
| 206 | default: |
195 | default: // unknown command id |
| 207 | I2C_RxBuffer = 0; |
196 | I2C_RxBuffer = 0; |
| 208 | I2C_RxBufferSize = 0; |
197 | I2C_RxBufferSize = 0; |
| 209 | I2C_TxBuffer = 0; |
198 | I2C_TxBuffer = 0; |
| 210 | I2C_TxBufferSize = 0; |
199 | I2C_TxBufferSize = 0; |
| 211 | break; |
200 | break; |
| 212 | } |
201 | } |
| 213 | Rx_Idx = 0; // set rx buffer index to start of the buffer |
202 | Rx_Idx = 0; // set rx buffer index to start of the buffer |
| 214 | if(I2C_RxBufferSize > 1) TWCR_ACK; // prepare receiving of next byte and send ACK afterwards |
- | |
| 215 | else TWCR_NACK; // prepare receiving of next byte and send NACK afterwards |
- | |
| 216 | } |
203 | } |
| 217 | else // Rx_Idx != 0xFF |
204 | else // Rx_Idx != 0xFF |
| 218 | { |
205 | { |
| 219 | // fill receiver buffer with byte that has been received |
206 | // fill receiver buffer with the byte that has been received |
| 220 | // if buffer exist |
- | |
| 221 | if(I2C_RxBuffer != 0) |
- | |
| 222 | { // and there is still some free space |
207 | // if buffer exist and there is still some free space |
| 223 | if (Rx_Idx < I2C_RxBufferSize) I2C_RxBuffer[Rx_Idx++] = data; |
208 | if((I2C_RxBuffer != 0) && (Rx_Idx < I2C_RxBufferSize)) |
| 224 | // if there is space for more than one byte |
209 | { |
| 225 | if(Rx_Idx < (I2C_RxBufferSize - 1)) TWCR_ACK; |
210 | I2C_RxBuffer[Rx_Idx++] = data; |
| 226 | // with the next incomming byte the rx buffer is full |
- | |
| 227 | else TWCR_NACK; |
- | |
| 228 | } |
211 | } |
| 229 | // rx buffer does not exist |
212 | // else ignore the data |
| 230 | else TWCR_NACK; // prepare receiving of next byte and send NACK afterwards |
- | |
| 231 | } |
213 | } |
| - | 214 | TWCR_ACK; |
|
| 232 | return; |
215 | return; |
| Line 233... | Line -... | ||
| 233 | - | ||
| 234 | case TW_SR_DATA_NACK: // data has been received and NACK has been returned |
- | |
| 235 | // read the last byte that is expected |
- | |
| 236 | data = TWDR; |
- | |
| 237 | if((I2C_RxBuffer != 0) && (Rx_Idx != 0xFF)) |
- | |
| 238 | { // and there is still some free space |
- | |
| 239 | if (Rx_Idx < I2C_RxBufferSize) I2C_RxBuffer[Rx_Idx++] = data; |
- | |
| 240 | } |
- | |
| 241 | TWCR_RESET; // switched to the non adressed slave mode |
- | |
| 242 | return; |
- | |
| 243 | 216 | ||
| 244 | case TW_ST_SLA_ACK: // slave transmitter selected |
217 | case TW_ST_SLA_ACK: // slave transmitter selected |
| 245 | // reset position in tx buffer |
218 | // reset index to start of tx buffer |
| 246 | Tx_Idx = 0; |
219 | Tx_Idx = 0; |
| 247 | case TW_ST_DATA_ACK: // data byte has been transmitted ack has been received |
- | |
| 248 | // put next byte from tx buffer to twi data register |
220 | // if tx bufer exist and there is at least ine byte to transfer |
| 249 | if(I2C_TxBuffer != 0) |
221 | if((I2C_TxBuffer != 0) && (I2C_TxBufferSize > 1)) |
| 250 | { |
- | |
| 251 | if (Tx_Idx < I2C_TxBufferSize) |
- | |
| 252 | { |
222 | { |
| 253 | TWDR = I2C_TxBuffer[Tx_Idx++]; |
- | |
| 254 | if(Tx_Idx + 1 < I2C_TxBufferSize) TWCR_ACK; // more than one byte to send |
- | |
| 255 | else TWCR_NACK; // last byte was send NACK should be received |
- | |
| 256 | } |
- | |
| 257 | else |
- | |
| 258 | { // |
- | |
| 259 | TWDR = 0x00; |
- | |
| 260 | TWCR_NACK;// NACK should be received |
- | |
| 261 | } |
223 | TWDR = I2C_TxBuffer[Tx_Idx++]; |
| - | 224 | } |
|
| - | 225 | else |
|
| - | 226 | { // send 0x00 if no tx buffer exist or all bytes of the tx buffer have been transmitted |
|
| - | 227 | TWDR = 0x00; |
|
| - | 228 | } |
|
| - | 229 | TWCR_ACK; |
|
| - | 230 | return; |
|
| - | 231 | ||
| 262 | } |
232 | case TW_ST_DATA_ACK: // data byte has been transmitted ack has been received |
| - | 233 | // put next byte from tx buffer to the data register |
|
| 263 | else // buffer not existent |
234 | if((I2C_TxBuffer != 0) && (Tx_Idx < I2C_TxBufferSize)) |
| - | 235 | { |
|
| - | 236 | TWDR = I2C_TxBuffer[Tx_Idx++]; |
|
| - | 237 | } |
|
| - | 238 | else |
|
| 264 | { |
239 | { // send dummy byte instead |
| 265 | TWDR = 0x00; |
- | |
| 266 | TWCR_NACK;// NACK should be received |
240 | TWDR = 0x00; |
| - | 241 | } |
|
| 267 | } |
242 | TWCR_ACK; |
| Line 268... | Line 243... | ||
| 268 | return; |
243 | return; |
| 269 | 244 | ||
| 270 | case TW_BUS_ERROR: // Bus-Error |
245 | case TW_BUS_ERROR: // Bus-Error |
| Line 271... | Line 246... | ||
| 271 | TWCR_CLEARBUS; // free bus reset to nonselected slave |
246 | TWCR_CLEARBUS; // free bus, reset to nonselected slave |
| 272 | return; |
247 | return; |
| 273 | 248 | ||