Rev 483 | Rev 489 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 483 | Rev 484 | ||
---|---|---|---|
Line 75... | Line 75... | ||
75 | if(SD_WatchDog) SD_WatchDog--; |
75 | if(SD_WatchDog) SD_WatchDog--; |
76 | if(SPIWatchDog) SPIWatchDog--; |
76 | if(SPIWatchDog) SPIWatchDog--; |
77 | if(PollingTimeout) PollingTimeout--; |
77 | if(PollingTimeout) PollingTimeout--; |
78 | // generate SW Interrupt to make a regular timing |
78 | // generate SW Interrupt to make a regular timing |
79 | // independent from the mainloop at the lowest IRQ priority |
79 | // independent from the mainloop at the lowest IRQ priority |
80 | VIC_SWITCmd(EXTIT3_ITLine, ENABLE); |
80 | VIC_SWITCmd(EXTIT3_ITLine, ENABLE); // Start this Interrupt |
81 | } |
81 | } |
82 | // IDISABLE; |
82 | // IDISABLE; |
Line 83... | Line 83... | ||
83 | 83 | ||
84 | VIC0->VAR = 0xFF; // write any value to VIC0 Vector address register |
84 | VIC0->VAR = 0xFF; // write any value to VIC0 Vector address register |