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1 | /******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** |
1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** |
2 | * File Name : usb_regs.h |
2 | * File Name : usb_regs.h |
3 | * Author : MCD Application Team |
3 | * Author : MCD Application Team |
- | 4 | * Version : V4.0.0 |
|
4 | * Date First Issued : 10/27/2003 : V1.0 |
5 | * Date : 09/29/2008 |
5 | * Description : Interface prototype functions to USB cell registers |
6 | * Description : Interface prototype functions to USB cell registers. |
6 | ******************************************************************************** |
7 | ******************************************************************************** |
7 | * History: |
- | |
8 | * 09/18/2006 : V3.0 |
- | |
9 | * 09/01/2006 : V2.0 |
- | |
10 | * 10/27/2003 : V1.0 |
- | |
11 | ******************************************************************************** |
- | |
12 | * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
8 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
9 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
14 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
10 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
15 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
11 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
16 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
12 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
17 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
13 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
18 | *******************************************************************************/ |
14 | *******************************************************************************/ |
- | 15 | ||
19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
16 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef __USB_REGS_H |
17 | #ifndef __USB_REGS_H |
21 | #define __USB_REGS_H |
18 | #define __USB_REGS_H |
- | 19 | ||
22 | /* Includes ------------------------------------------------------------------*/ |
20 | /* Includes ------------------------------------------------------------------*/ |
23 | /* Exported types ------------------------------------------------------------*/ |
21 | /* Exported types ------------------------------------------------------------*/ |
Line 24... | Line 22... | ||
24 | 22 | ||
25 | typedef enum _EP_DBUF_DIR{ /* double buffered endpoint direction */ |
23 | typedef enum _EP_DBUF_DIR{ /* double buffered endpoint direction */ |
26 | EP_DBUF_ERR, |
24 | EP_DBUF_ERR, |
27 | EP_DBUF_OUT, |
25 | EP_DBUF_OUT, |
28 | EP_DBUF_IN |
26 | EP_DBUF_IN |
Line 29... | Line 27... | ||
29 | }EP_DBUF_DIR; |
27 | }EP_DBUF_DIR; |
30 | 28 | ||
31 | /* endpoint buffer number */ |
29 | /* endpoint buffer number */ |
32 | enum EP_BUF_NUM{ |
30 | enum EP_BUF_NUM{ |
33 | EP_NOBUF, |
31 | EP_NOBUF, |
34 | EP_BUF0, |
32 | EP_BUF0, |
Line 35... | Line 33... | ||
35 | EP_BUF1 |
33 | EP_BUF1 |
36 | }; |
34 | }; |
Line 37... | Line 35... | ||
37 | 35 | ||
38 | /* Exported constants --------------------------------------------------------*/ |
36 | /* Exported constants --------------------------------------------------------*/ |
39 | #ifdef STR7xx |
37 | #ifdef STR7xx |
40 | 38 | ||
41 | #ifdef STR71x /*STR71x family*/ |
39 | #ifdef STR71x /*STR71x family*/ |
42 | #define RegBase (0xC0008800L) /* USB_IP Peripheral Registers base address */ |
40 | #define RegBase (0xC0008800L) /* USB_IP Peripheral Registers base address */ |
43 | #define PMAAddr (0xC0008000L) /* USB_IP Packet Memory Area base address */ |
41 | #define PMAAddr (0xC0008000L) /* USB_IP Packet Memory Area base address */ |
44 | #endif /*end of STR71x family*/ |
42 | #endif /*end of STR71x family*/ |
45 | 43 | ||
46 | #ifdef STR75x /*STR75x family*/ |
44 | #ifdef STR75x /*STR75x family*/ |
47 | #define RegBase (0xFFFFA800L) /* USB_IP Peripheral Registers base address */ |
45 | #define RegBase (0xFFFFA800L) /* USB_IP Peripheral Registers base address */ |
Line 48... | Line 46... | ||
48 | #define PMAAddr (0xFFFFA000L) /* USB_IP Packet Memory Area base address */ |
46 | #define PMAAddr (0xFFFFA000L) /* USB_IP Packet Memory Area base address */ |
Line 49... | Line 47... | ||
49 | #endif /*end of STR75x family*/ |
47 | #endif /*end of STR75x family*/ |
50 | 48 | ||
51 | #endif /*end of STR7xx family*/ |
49 | #endif /*end of STR7xx family*/ |
52 | 50 | ||
53 | #ifdef STR91x /*STR91x family*/ |
51 | #ifdef STR91x /*STR91x family*/ |
54 | 52 | ||
55 | #ifdef STR91x_USB_BUFFERED |
53 | #ifdef STR91x_USB_BUFFERED |
56 | #define RegBase (0x60000800L) /* USB_IP Peripheral Registers base address */ |
54 | #define RegBase (0x60000800L) /* USB_IP Peripheral Registers base address */ |
57 | #define PMAAddr (0x60000000L) /* USB_IP Packet Memory Area base address */ |
55 | #define PMAAddr (0x60000000L) /* USB_IP Packet Memory Area base address */ |
58 | #endif |
56 | #endif |
Line 59... | Line 57... | ||
59 | 57 | ||
- | 58 | #ifdef STR91x_USB_NON_BUFFERED |
|
60 | #ifdef STR91x_USB_NON_BUFFERED |
59 | #define RegBase (0x70000800L) /* USB_IP Peripheral Registers base address */ |
- | 60 | #define PMAAddr (0x70000000L) /* USB_IP Packet Memory Area base address */ |
|
61 | #define RegBase (0x70000800L) /* USB_IP Peripheral Registers base address */ |
61 | #endif |
- | 62 | #endif |
|
62 | #define PMAAddr (0x70000000L) /* USB_IP Packet Memory Area base address */ |
63 | |
- | 64 | /* General registers */ |
|
63 | #endif |
65 | /* Control register */ |
- | 66 | #define CNTR ((volatile unsigned *)(RegBase + 0x40)) |
|
64 | #endif |
67 | /* Interrupt status register */ |
Line 65... | Line 68... | ||
65 | 68 | #define ISTR ((volatile unsigned *)(RegBase + 0x44)) |
|
66 | /* General registers */ |
- | |
- | 69 | /* Frame number register */ |
|
67 | #define CNTR ((volatile unsigned *)(RegBase + 0x40)) /* Control register */ |
70 | #define FNR ((volatile unsigned *)(RegBase + 0x48)) |
- | 71 | /* Device address register */ |
|
68 | #define ISTR ((volatile unsigned *)(RegBase + 0x44)) /* Interrupt status register */ |
72 | #define DADDR ((volatile unsigned *)(RegBase + 0x4C)) |
- | 73 | /* Buffer Table address register */ |
|
69 | #define FNR ((volatile unsigned *)(RegBase + 0x48)) /* Frame number register */ |
74 | #define BTABLE ((volatile unsigned *)(RegBase + 0x50)) |
- | 75 | ||
70 | #define DADDR ((volatile unsigned *)(RegBase + 0x4C)) /* Device address register */ |
76 | #ifdef STR91x /*STR91x family DMA registers*/ |
- | 77 | /* DMA control register 1 */ |
|
71 | #define BTABLE ((volatile unsigned *)(RegBase + 0x50)) /* Buffer Table address register */ |
78 | #define DMACR1 ((volatile unsigned *)(RegBase + 0x54)) |
Line 72... | Line 79... | ||
72 | 79 | /* DMA control register 2 */ |
|
Line 73... | Line 80... | ||
73 | #ifdef STR91x /*STR91x family DMA registers*/ |
80 | #define DMACR2 ((volatile unsigned *)(RegBase + 0x58)) |
- | 81 | /* DMA control register 3 */ |
|
74 | 82 | #define DMACR3 ((volatile unsigned *)(RegBase + 0x5C)) |
|
75 | #define DMACR1 ((volatile unsigned *)(RegBase + 0x54)) /* DMA control register 1 */ |
83 | /* DMA burst size register */ |
76 | #define DMACR2 ((volatile unsigned *)(RegBase + 0x58)) /* DMA control register 2 */ |
84 | #define DMABSIZE ((volatile unsigned *)(RegBase + 0x60)) |
77 | #define DMACR3 ((volatile unsigned *)(RegBase + 0x5C)) /* DMA control register 3 */ |
85 | /* DMA LLI register */ |
78 | #define DMABSIZE ((volatile unsigned *)(RegBase + 0x60))/* DMA burst size register */ |
86 | #define DMALLI ((volatile unsigned *)(RegBase + 0x64)) |
79 | #define DMALLI ((volatile unsigned *)(RegBase + 0x64)) /* DMA LLI register */ |
87 | |
80 | 88 | #endif |
|
81 | #endif |
89 | |
82 | 90 | /* Endpoint registers */ |
|
83 | /* Endpoint registers */ |
91 | /* endpoint 0 register address */ |
84 | #define EP0REG ((volatile unsigned *)(RegBase)) /* endpoint 0 register address */ |
92 | #define EP0REG ((volatile unsigned *)(RegBase)) |
85 | /* endpoints enumeration */ |
93 | /* endpoints enumeration */ |
86 | #define ENDP0 ((u8)0) |
94 | #define ENDP0 ((u8)0) |
87 | #define ENDP1 ((u8)1) |
95 | #define ENDP1 ((u8)1) |
88 | #define ENDP2 ((u8)2) |
96 | #define ENDP2 ((u8)2) |
89 | #define ENDP3 ((u8)3) |
97 | #define ENDP3 ((u8)3) |
90 | #define ENDP4 ((u8)4) |
98 | #define ENDP4 ((u8)4) |
91 | #define ENDP5 ((u8)5) |
99 | #define ENDP5 ((u8)5) |
92 | #define ENDP6 ((u8)6) |
100 | #define ENDP6 ((u8)6) |
93 | #define ENDP7 ((u8)7) /* Only 8 endpoints for STR75x Family */ |
101 | #define ENDP7 ((u8)7) /* Only 8 endpoints for STR75x Family */ |
94 | #define ENDP8 ((u8)8) |
102 | #define ENDP8 ((u8)8) |
95 | #define ENDP9 ((u8)9) /* Only 10 endpoints for STR91x Family */ |
103 | #define ENDP9 ((u8)9) /* Only 10 endpoints for STR91x Family */ |
96 | #define ENDP10 ((u8)10) |
104 | #define ENDP10 ((u8)10) |
97 | #define ENDP11 ((u8)11) |
105 | #define ENDP11 ((u8)11) |
98 | #define ENDP12 ((u8)12) |
106 | #define ENDP12 ((u8)12) |
99 | #define ENDP13 ((u8)13) |
107 | #define ENDP13 ((u8)13) |
100 | #define ENDP14 ((u8)14) |
108 | #define ENDP14 ((u8)14) |
101 | #define ENDP15 ((u8)15) |
109 | #define ENDP15 ((u8)15) |
102 | 110 | ||
103 | /*******************************************************************************/ |
111 | /******************************************************************************/ |
Line 104... | Line 112... | ||
104 | /* ISTR interrupt events */ |
112 | /* ISTR interrupt events */ |
105 | /*******************************************************************************/ |
113 | /******************************************************************************/ |
106 | #define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */ |
114 | #define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */ |
Line 107... | Line 115... | ||
107 | #define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */ |
115 | #define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */ |
108 | #define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */ |
116 | #define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */ |
Line 109... | Line 117... | ||
109 | #define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */ |
117 | #define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */ |
110 | #define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */ |
118 | #define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */ |
111 | #define ISTR_RESET (0x0400) /* RESET (clear-only bit) */ |
119 | #define ISTR_RESET (0x0400) /* RESET (clear-only bit) */ |
112 | #define ISTR_SOF (0x0200) /* Start Of Frame (clear-only bit) */ |
120 | #define ISTR_SOF (0x0200) /* Start Of Frame (clear-only bit) */ |
113 | #define ISTR_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */ |
121 | #define ISTR_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */ |
114 | 122 | ||
115 | #ifdef STR91x /*STR91x family*/ |
123 | #ifdef STR91x /*STR91x family*/ |
116 | #define ISTR_SZDPR (0x0080) /* Short or Zero-Length Received Data Packet */ |
124 | #define ISTR_SZDPR (0x0080) /* Short or Zero-Length Received Data Packet */ |
Line 117... | Line 125... | ||
117 | #endif |
125 | #endif |
118 | 126 | ||
119 | #define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */ |
127 | #define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */ |
Line 120... | Line 128... | ||
120 | #define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */ |
128 | #define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */ |
121 | 129 | ||
122 | #define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */ |
130 | #define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */ |
123 | #define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/ |
131 | #define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/ |
124 | #define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */ |
132 | #define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */ |
125 | #define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */ |
133 | #define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */ |
126 | #define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */ |
134 | #define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */ |
127 | #define CLR_RESET (~ISTR_RESET) /* clear RESET bit */ |
135 | #define CLR_RESET (~ISTR_RESET) /* clear RESET bit */ |
128 | #define CLR_SOF (~ISTR_SOF) /* clear Start Of Frame bit */ |
136 | #define CLR_SOF (~ISTR_SOF) /* clear Start Of Frame bit */ |
129 | #define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */ |
137 | #define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */ |
130 | 138 | ||
Line 131... | Line 139... | ||
131 | #ifdef STR91x /*STR91x family*/ |
139 | #ifdef STR91x /*STR91x family*/ |
132 | #define CLR_SZDPR (~ISTR_SZDPR)/* clear SZDPR bit */ |
140 | #define CLR_SZDPR (~ISTR_SZDPR) /* clear SZDPR bit */ |
133 | #endif |
141 | #endif |
Line 134... | Line 142... | ||
134 | 142 | ||
135 | /*******************************************************************************/ |
143 | /******************************************************************************/ |
136 | /* CNTR control register bits definitions */ |
144 | /* CNTR control register bits definitions */ |
137 | /*******************************************************************************/ |
145 | /******************************************************************************/ |
138 | #define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */ |
146 | #define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */ |
139 | #define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */ |
147 | #define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */ |
140 | #define CNTR_ERRM (0x2000) /* ERRor Mask */ |
148 | #define CNTR_ERRM (0x2000) /* ERRor Mask */ |
141 | #define CNTR_WKUPM (0x1000) /* WaKe UP Mask */ |
149 | #define CNTR_WKUPM (0x1000) /* WaKe UP Mask */ |
142 | #define CNTR_SUSPM (0x0800) /* SUSPend Mask */ |
150 | #define CNTR_SUSPM (0x0800) /* SUSPend Mask */ |
143 | #define CNTR_RESETM (0x0400) /* RESET Mask */ |
151 | #define CNTR_RESETM (0x0400) /* RESET Mask */ |
144 | #define CNTR_SOFM (0x0200) /* Start Of Frame Mask */ |
152 | #define CNTR_SOFM (0x0200) /* Start Of Frame Mask */ |
145 | #define CNTR_ESOFM (0x0100) /* Expected Start Of Frame Mask */ |
153 | #define CNTR_ESOFM (0x0100) /* Expected Start Of Frame Mask */ |
146 | 154 | ||
147 | #ifdef STR91x /*STR91x family*/ |
155 | #ifdef STR91x /*STR91x family*/ |
148 | #define CNTR_SZDPRM (0x0080) /* Short or Zero-Length Received Data Packet Mask*/ |
156 | #define CNTR_SZDPRM (0x0080) /* Short or Zero-Length Received Data Packet Mask*/ |
149 | #endif |
157 | #endif |
150 | 158 | ||
151 | #define CNTR_RESUME (0x0010) /* RESUME request */ |
159 | #define CNTR_RESUME (0x0010) /* RESUME request */ |
152 | #define CNTR_FSUSP (0x0008) /* Force SUSPend */ |
160 | #define CNTR_FSUSP (0x0008) /* Force SUSPend */ |
- | 161 | #define CNTR_LPMODE (0x0004) /* Low-power MODE */ |
|
153 | #define CNTR_LPMODE (0x0004) /* Low-power MODE */ |
162 | #define CNTR_PDWN (0x0002) /* Power DoWN */ |
154 | #define CNTR_PDWN (0x0002) /* Power DoWN */ |
163 | #define CNTR_FRES (0x0001) /* Force USB RESet */ |
155 | #define CNTR_FRES (0x0001) /* Force USB RESet */ |
- | |
156 | - | ||
157 | /*******************************************************************************/ |
164 | |
158 | /* FNR Frame Number Register bit definitions */ |
165 | /******************************************************************************/ |
159 | /*******************************************************************************/ |
166 | /* FNR Frame Number Register bit definitions */ |
160 | #define FNR_RXDP (0x8000) /* status of D+ data line */ |
167 | /******************************************************************************/ |
161 | #define FNR_RXDM (0x4000) /* status of D- data line */ |
168 | #define FNR_RXDP (0x8000) /* status of D+ data line */ |
162 | #define FNR_LCK (0x2000) /* LoCKed */ |
169 | #define FNR_RXDM (0x4000) /* status of D- data line */ |
163 | #define FNR_LSOF (0x1800) /* Lost SOF */ |
170 | #define FNR_LCK (0x2000) /* LoCKed */ |
164 | #define FNR_FN (0x07FF) /* Frame Number */ |
171 | #define FNR_LSOF (0x1800) /* Lost SOF */ |
165 | /*******************************************************************************/ |
172 | #define FNR_FN (0x07FF) /* Frame Number */ |
166 | /* DADDR Device ADDRess bit definitions */ |
173 | /******************************************************************************/ |
Line 167... | Line 174... | ||
167 | /*******************************************************************************/ |
174 | /* DADDR Device ADDRess bit definitions */ |
168 | #define DADDR_EF (0x80) |
175 | /******************************************************************************/ |
- | 176 | #define DADDR_EF (0x80) |
|
Line 169... | Line 177... | ||
169 | #define DADDR_ADD (0x7F) |
177 | #define DADDR_ADD (0x7F) |
170 | /*===============================================================================*/ |
178 | |
171 | /* Endpoint register */ |
179 | /******************************************************************************/ |
172 | /*===============================================================================*/ |
180 | /* Endpoint register */ |
173 | /* bit positions */ |
181 | #define EP_CTR_RX (0x8000) /* EndPoint Correct TRansfer RX */ |
174 | #define EP_CTR_RX (0x8000) /* EndPoint Correct TRansfer RX */ |
182 | #define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */ |
175 | #define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */ |
183 | #define EPRX_STAT (0x3000) /* EndPoint RX STATus bit field */ |
Line 176... | Line 184... | ||
176 | #define EPRX_STAT (0x3000) /* EndPoint RX STATus bit field */ |
184 | #define EP_SETUP (0x0800) /* EndPoint SETUP */ |
177 | #define EP_SETUP (0x0800) /* EndPoint SETUP */ |
185 | #define EP_T_FIELD (0x0600) /* EndPoint TYPE */ |
Line 178... | Line 186... | ||
178 | #define EP_T_FIELD (0x0600) /* EndPoint TYPE */ |
186 | #define EP_KIND (0x0100) /* EndPoint KIND */ |
179 | #define EP_KIND (0x0100) /* EndPoint KIND */ |
187 | #define EP_CTR_TX (0x0080) /* EndPoint Correct TRansfer TX */ |
180 | #define EP_CTR_TX (0x0080) /* EndPoint Correct TRansfer TX */ |
188 | #define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */ |
181 | #define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */ |
189 | #define EPTX_STAT (0x0030) /* EndPoint TX STATus bit field */ |
182 | #define EPTX_STAT (0x0030) /* EndPoint TX STATus bit field */ |
190 | #define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */ |
183 | #define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */ |
191 | |
184 | 192 | /* EndPoint REGister MASK (no toggle fields) */ |
|
185 | /* EndPoint REGister MASK (no toggle fields) */ |
193 | #define EPREG_MASK (EP_CTR_RX | EP_SETUP | EP_T_FIELD | EP_KIND |\ |
Line 186... | Line 194... | ||
186 | #define EPREG_MASK (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD) |
194 | EP_CTR_TX |EPADDR_FIELD) |
187 | 195 | ||
188 | /* EP_TYPE[1:0] EndPoint TYPE */ |
196 | /* EP_TYPE[1:0] EndPoint TYPE */ |
189 | #define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */ |
197 | #define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */ |
190 | #define EP_BULK (0x0000) /* EndPoint BULK */ |
198 | #define EP_BULK (0x0000) /* EndPoint BULK */ |
191 | #define EP_CONTROL (0x0200) /* EndPoint CONTROL */ |
199 | #define EP_CONTROL (0x0200) /* EndPoint CONTROL */ |
192 | #define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */ |
200 | #define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */ |
193 | #define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */ |
201 | #define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */ |
Line 194... | Line 202... | ||
194 | #define EP_T_MASK (~EP_T_FIELD & EPREG_MASK) |
202 | #define EP_T_MASK (~EP_T_FIELD & EPREG_MASK) |
195 | - | ||
- | 203 | ||
196 | 204 | ||
197 | /* EP_KIND EndPoint KIND */ |
- | |
198 | #define EPKIND_MASK (~EP_KIND & EPREG_MASK) |
205 | /* EP_KIND EndPoint KIND */ |
199 | - | ||
- | 206 | #define EPKIND_MASK (~EP_KIND & EPREG_MASK) |
|
200 | /* STAT_TX[1:0] STATus for TX transfer */ |
207 | |
201 | #define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */ |
- | |
202 | #define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */ |
208 | /* STAT_TX[1:0] STATus for TX transfer */ |
203 | #define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */ |
- | |
- | 209 | #define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */ |
|
204 | #define EP_TX_VALID (0x0030) /* EndPoint TX VALID */ |
210 | #define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */ |
205 | #define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */ |
- | |
206 | #define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */ |
211 | #define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */ |
207 | #define EPTX_DTOGMASK (EPTX_STAT|EPREG_MASK) |
- | |
- | 212 | #define EP_TX_VALID (0x0030) /* EndPoint TX VALID */ |
|
208 | 213 | #define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */ |
|
209 | /* STAT_RX[1:0] STATus for RX transfer */ |
- | |
210 | #define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */ |
214 | #define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */ |
211 | #define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */ |
- | |
- | 215 | #define EPTX_DTOGMASK (EPTX_STAT|EPREG_MASK) |
|
212 | #define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */ |
216 | |
213 | #define EP_RX_VALID (0x3000) /* EndPoint RX VALID */ |
- | |
214 | #define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */ |
217 | /* STAT_RX[1:0] STATus for RX transfer */ |
215 | #define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */ |
- | |
- | 218 | #define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */ |
|
216 | #define EPRX_DTOGMASK (EPRX_STAT|EPREG_MASK) |
219 | #define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */ |
217 | - | ||
218 | /* Exported macro ------------------------------------------------------------*/ |
220 | #define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */ |
219 | /*----------------------------------------------------------------*/ |
- | |
- | 221 | #define EP_RX_VALID (0x3000) /* EndPoint RX VALID */ |
|
220 | /* SetCNTR */ |
222 | #define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */ |
221 | /*----------------------------------------------------------------*/ |
- | |
222 | #define _SetCNTR(wRegValue) (*CNTR = (u16)wRegValue) |
223 | #define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */ |
223 | /*----------------------------------------------------------------*/ |
- | |
- | 224 | #define EPRX_DTOGMASK (EPRX_STAT|EPREG_MASK) |
|
224 | /* SetISTR */ |
225 | |
225 | /*----------------------------------------------------------------*/ |
- | |
226 | #define _SetISTR(wRegValue) (*ISTR = (u16)wRegValue) |
226 | /* Exported macro */ |
227 | /*----------------------------------------------------------------*/ |
- | |
- | 227 | ||
228 | /* SetDADDR */ |
228 | /* SetCNTR */ |
229 | /*----------------------------------------------------------------*/ |
- | |
230 | #define _SetDADDR(wRegValue) (*DADDR = (u16)wRegValue) |
229 | #define _SetCNTR(wRegValue) (*CNTR = (u16)wRegValue) |
231 | /*----------------------------------------------------------------*/ |
- | |
- | 230 | ||
232 | /* SetBTABLE */ |
231 | /* SetISTR */ |
233 | /*----------------------------------------------------------------*/ |
- | |
234 | #define _SetBTABLE(wRegValue)(*BTABLE = (u16)(wRegValue & 0xFFF8)) |
232 | #define _SetISTR(wRegValue) (*ISTR = (u16)wRegValue) |
235 | /*----------------------------------------------------------------*/ |
233 | |
236 | /* GetCNTR */ |
- | |
- | 234 | /* SetDADDR */ |
|
237 | /*----------------------------------------------------------------*/ |
235 | #define _SetDADDR(wRegValue) (*DADDR = (u16)wRegValue) |
238 | #define _GetCNTR() ((u16) *CNTR) |
- | |
239 | /*----------------------------------------------------------------*/ |
236 | |
240 | /* GetISTR */ |
237 | /* SetBTABLE */ |
241 | /*----------------------------------------------------------------*/ |
238 | #define _SetBTABLE(wRegValue)(*BTABLE = (u16)(wRegValue & 0xFFF8)) |
242 | #define _GetISTR() ((u16) *ISTR) |
239 | |
243 | /*----------------------------------------------------------------*/ |
240 | /* GetCNTR */ |
- | 241 | #define _GetCNTR() ((u16) *CNTR) |
|
244 | /* GetFNR */ |
242 | |
245 | /*----------------------------------------------------------------*/ |
243 | /* GetISTR */ |
246 | #define _GetFNR() ((u16) *FNR) |
244 | #define _GetISTR() ((u16) *ISTR) |
247 | /*----------------------------------------------------------------*/ |
245 | |
248 | /* GetDADDR */ |
246 | /* GetFNR */ |
- | 247 | #define _GetFNR() ((u16) *FNR) |
|
249 | /*----------------------------------------------------------------*/ |
248 | |
250 | #define _GetDADDR() ((u16) *DADDR) |
249 | /* GetDADDR */ |
251 | /*----------------------------------------------------------------*/ |
250 | #define _GetDADDR() ((u16) *DADDR) |
252 | /* GetBTABLE */ |
251 | |
253 | /*----------------------------------------------------------------*/ |
252 | /* GetBTABLE */ |
- | 253 | #define _GetBTABLE() ((u16) *BTABLE) |
|
254 | #define _GetBTABLE() ((u16) *BTABLE) |
254 | |
255 | /*----------------------------------------------------------------*/ |
255 | /* SetENDPOINT */ |
- | 256 | #define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \ |
|
256 | /* SetENDPOINT */ |
257 | (u16)wRegValue) |
257 | /*----------------------------------------------------------------*/ |
258 | |
258 | #define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \ |
259 | /* GetENDPOINT */ |
259 | (u16)wRegValue) |
260 | #define _GetENDPOINT(bEpNum) ((u16)(*(EP0REG + bEpNum))) |
260 | /*----------------------------------------------------------------*/ |
261 | /******************************************************************************* |
261 | /* GetENDPOINT */ |
262 | * Macro Name : SetEPType |
- | 263 | * Description : sets the type in the endpoint register(bits EP_TYPE[1:0]) |
|
262 | /*----------------------------------------------------------------*/ |
264 | * Input : bEpNum: Endpoint Number. |
263 | #define _GetENDPOINT(bEpNum) ((u16)(*(EP0REG + bEpNum))) |
265 | * wType |
264 | /*----------------------------------------------------------------*/ |
266 | * Output : None. |
265 | /* SetEPType */ |
267 | * Return : None. |
266 | /* sets the type in the endpoint register(bits EP_TYPE[1:0]) */ |
268 | *******************************************************************************/ |
267 | /* IN : bEpNum = endpoint number */ |
269 | #define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\ |
268 | /* wType = type definition */ |
270 | ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType))) |
269 | /* OUT: none */ |
271 | |
270 | /*----------------------------------------------------------------*/ |
272 | /******************************************************************************* |
271 | #define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\ |
273 | * Macro Name : GetEPType |
272 | ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType))) |
274 | * Description : gets the type in the endpoint register(bits EP_TYPE[1:0]) |
273 | /*----------------------------------------------------------------*/ |
275 | * Input : bEpNum: Endpoint Number. |
274 | /* GetEPType */ |
276 | * Output : None. |
275 | /* gets the type in the endpoint register(bits EP_TYPE[1:0]) */ |
277 | * Return : Endpoint Type |
276 | /* IN : bEpNum = endpoint number */ |
278 | *******************************************************************************/ |
277 | /* OUT: type definition */ |
279 | #define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD) |
278 | /*----------------------------------------------------------------*/ |
280 | |
279 | #define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD) |
281 | /******************************************************************************* |
280 | /*----------------------------------------------------------------*/ |
282 | * Macro Name : SetEPTxStatus |
- | 283 | * Description : sets the status for tx transfer (bits STAT_TX[1:0]). |
|
281 | /* SetEPTxStatus */ |
284 | * Input : bEpNum: Endpoint Number. |
282 | /* sets the status for tx transfer (bits STAT_TX[1:0]) */ |
285 | * wState: new state |
283 | /* IN : bEpNum = endpoint number */ |
286 | * Output : None. |
284 | /* wState = new state */ |
287 | * Return : None. |
285 | /* OUT: none */ |
288 | *******************************************************************************/ |
286 | /*----------------------------------------------------------------*/ |
289 | #define _SetEPTxStatus(bEpNum,wState) {\ |
287 | #define _SetEPTxStatus(bEpNum,wState) {\ |
290 | register u16 _wRegVal; \ |
288 | register u16 _wRegVal; \ |
291 | _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\ |
289 | _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\ |
292 | /* toggle first bit ? */ \ |
290 | /* toggle first bit ? */ \ |
293 | if((EPTX_DTOG1 & wState)!= 0) \ |
291 | if((EPTX_DTOG1 & wState)!= 0) \ |
294 | _wRegVal ^= EPTX_DTOG1; \ |
292 | _wRegVal ^= EPTX_DTOG1; \ |
295 | /* toggle second bit ? */ \ |
293 | /* toggle second bit ? */ \ |
296 | if((EPTX_DTOG2 & wState)!= 0) \ |
- | 297 | _wRegVal ^= EPTX_DTOG2; \ |
|
294 | if((EPTX_DTOG2 & wState)!= 0) \ |
298 | _SetENDPOINT(bEpNum, _wRegVal); \ |
295 | _wRegVal ^= EPTX_DTOG2; \ |
299 | } /* _SetEPTxStatus */ |
296 | _SetENDPOINT(bEpNum, _wRegVal); \ |
300 | |
- | 301 | /******************************************************************************* |
|
297 | } /* _SetEPTxStatus */ |
302 | * Macro Name : SetEPRxStatus |
- | 303 | * Description : sets the status for rx transfer (bits STAT_TX[1:0]) |
|
298 | 304 | * Input : bEpNum: Endpoint Number. |
|
299 | /*----------------------------------------------------------------*/ |
305 | * wState: new state. |
300 | /* SetEPRxStatus */ |
306 | * Output : None. |
301 | /* sets the status for rx transfer (bits STAT_TX[1:0]) */ |
307 | * Return : None. |
- | 308 | *******************************************************************************/ |
|
302 | /* IN : bEpNum = endpoint number */ |
309 | #define _SetEPRxStatus(bEpNum,wState) {\ |
303 | /* wState = new state */ |
310 | register u16 _wRegVal; \ |
304 | /* OUT: none */ |
311 | \ |
305 | /*----------------------------------------------------------------*/ |
312 | _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\ |
306 | #define _SetEPRxStatus(bEpNum,wState) {\ |
313 | /* toggle first bit ? */ \ |
- | 314 | if((EPRX_DTOG1 & wState)!= 0) \ |
|
307 | register u16 _wRegVal; \ |
315 | _wRegVal ^= EPRX_DTOG1; \ |
308 | \ |
316 | /* toggle second bit ? */ \ |
309 | _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\ |
317 | if((EPRX_DTOG2 & wState)!= 0) \ |
- | 318 | _wRegVal ^= EPRX_DTOG2; \ |
|
310 | /* toggle first bit ? */ \ |
319 | _SetENDPOINT(bEpNum, _wRegVal); \ |
311 | if((EPRX_DTOG1 & wState)!= 0) \ |
320 | } /* _SetEPRxStatus */ |
312 | _wRegVal ^= EPRX_DTOG1; \ |
321 | |
313 | /* toggle second bit ? */ \ |
322 | /******************************************************************************* |
- | 323 | * Macro Name : GetEPTxStatus / GetEPRxStatus |
|
314 | if((EPRX_DTOG2 & wState)!= 0) \ |
324 | * Description : gets the status for tx/rx transfer (bits STAT_TX[1:0] |
315 | _wRegVal ^= EPRX_DTOG2; \ |
325 | * /STAT_RX[1:0]) |
316 | _SetENDPOINT(bEpNum, _wRegVal); \ |
326 | * Input : bEpNum: Endpoint Number. |
317 | } /* _SetEPRxStatus */ |
327 | * Output : None. |
318 | /*----------------------------------------------------------------*/ |
328 | * Return : status . |
319 | /* GetEPTxStatus / GetEPRxStatus */ |
329 | *******************************************************************************/ |
320 | /* gets the status for tx/rx transfer (bits STAT_TX[1:0]/STAT_RX[1:0]) */ |
330 | #define _GetEPTxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPTX_STAT) |
321 | /* IN : bEpNum = endpoint number */ |
331 | #define _GetEPRxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPRX_STAT) |
- | 332 | ||
322 | /* OUT: u16 status */ |
333 | /******************************************************************************* |
323 | /*----------------------------------------------------------------*/ |
334 | * Macro Name : SetEPTxValid / SetEPRxValid |
- | 335 | * Description : sets directly the VALID tx/rx-status into the enpoint register |
|
324 | #define _GetEPTxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPTX_STAT) |
336 | * Input : bEpNum: Endpoint Number. |
325 | #define _GetEPRxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPRX_STAT) |
337 | * Output : None. |
326 | /*----------------------------------------------------------------*/ |
338 | * Return : None. |
327 | /* SetEPTxValid / SetEPRxValid */ |
339 | *******************************************************************************/ |
328 | /* sets directly the VALID tx/rx-status into the enpoint register */ |
340 | #define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID)) |
- | 341 | #define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID)) |
|
329 | /* IN : bEpNum = endpoint number */ |
342 | |
330 | /* OUT: none */ |
343 | /******************************************************************************* |
331 | /*----------------------------------------------------------------*/ |
344 | * Macro Name : GetTxStallStatus / GetRxStallStatus. |
332 | #define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID)) |
345 | * Description : checks stall condition in an endpoint. |
333 | #define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID)) |
346 | * Input : bEpNum: Endpoint Number. |
334 | /*----------------------------------------------------------------*/ |
347 | * Output : None. |
335 | /* GetTxStallStatus / GetRxStallStatus */ |
348 | * Return : TRUE = endpoint in stall condition. |
336 | /* checks stall condition in an endpoint */ |
349 | *******************************************************************************/ |
337 | /* IN : bEpNum = endpoint number */ |
350 | #define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \ |
- | 351 | == EP_TX_STALL) |
|
338 | /* OUT: TRUE = endpoint in stall condition */ |
352 | #define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \ |
339 | /*----------------------------------------------------------------*/ |
353 | == EP_RX_STALL) |
340 | #define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \ |
354 | /******************************************************************************* |
341 | == EP_TX_STALL) |
355 | * Macro Name : SetEP_KIND / ClearEP_KIND. |
342 | #define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \ |
356 | * Description : set & clear EP_KIND bit. |
- | 357 | * Input : bEpNum: Endpoint Number. |
|
343 | == EP_RX_STALL) |
358 | * Output : None. |
344 | /*----------------------------------------------------------------*/ |
359 | * Return : None. |
345 | /* SetEP_KIND / ClearEP_KIND */ |
360 | *******************************************************************************/ |
- | 361 | #define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ |
|
346 | /* IN : bEpNum = endpoint number */ |
362 | (_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK)) |
347 | /* OUT: none */ |
363 | #define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ |
348 | /*----------------------------------------------------------------*/ |
364 | (_GetENDPOINT(bEpNum) & EPKIND_MASK))) |
349 | #define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ |
365 | |
350 | (_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK)) |
366 | /******************************************************************************* |
- | 367 | * Macro Name : Set_Status_Out / Clear_Status_Out. |
|
351 | #define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ |
368 | * Description : Sets/clears directly STATUS_OUT bit in the endpoint register. |
352 | (_GetENDPOINT(bEpNum) & EPKIND_MASK))) |
369 | * Input : bEpNum: Endpoint Number. |
353 | /*----------------------------------------------------------------*/ |
370 | * Output : None. |
354 | /* Set_Status_Out / Clear_Status_Out */ |
371 | * Return : None. |
355 | /* sets/clears directly STATUS_OUT bit in the endpoint register */ |
372 | *******************************************************************************/ |
- | 373 | #define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum) |
|
356 | /* to be used only during control transfers */ |
374 | #define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum) |
357 | /* IN : bEpNum = endpoint number */ |
375 | |
358 | /* OUT: none */ |
376 | /******************************************************************************* |
359 | /*----------------------------------------------------------------*/ |
377 | * Macro Name : SetEPDoubleBuff / ClearEPDoubleBuff. |
360 | #define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum) |
378 | * Description : Sets/clears directly EP_KIND bit in the endpoint register. |
- | 379 | * Input : bEpNum: Endpoint Number. |
|
361 | #define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum) |
380 | * Output : None. |
362 | /*----------------------------------------------------------------*/ |
381 | * Return : None. |
363 | /* SetEPDoubleBuff / ClearEPDoubleBuff */ |
382 | *******************************************************************************/ |
364 | /* sets/clears directly EP_KIND bit in the endpoint register */ |
383 | #define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum) |
365 | /* IN : bEpNum = endpoint number */ |
384 | #define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum) |
- | 385 | ||
366 | /* OUT: none */ |
386 | /******************************************************************************* |
367 | /*----------------------------------------------------------------*/ |
387 | * Macro Name : ClearEP_CTR_RX / ClearEP_CTR_TX. |
- | 388 | * Description : Clears bit CTR_RX / CTR_TX in the endpoint register. |
|
368 | #define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum) |
389 | * Input : bEpNum: Endpoint Number. |
369 | #define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum) |
390 | * Output : None. |
- | 391 | * Return : None. |
|
370 | /*----------------------------------------------------------------*/ |
392 | *******************************************************************************/ |
371 | /* ClearEP_CTR_RX / ClearEP_CTR_TX */ |
393 | #define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum,\ |
372 | /* clears bit CTR_RX / CTR_TX in the endpoint register */ |
394 | _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK)) |
373 | /* IN : bEpNum = endpoint number */ |
395 | #define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum,\ |
374 | /* OUT: none */ |
396 | _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK)) |
375 | /*----------------------------------------------------------------*/ |
397 | |
376 | #define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum,\ |
398 | /******************************************************************************* |
377 | _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK)) |
399 | * Macro Name : ToggleDTOG_RX / ToggleDTOG_TX . |
378 | #define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum,\ |
400 | * Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register. |
- | 401 | * Input : bEpNum: Endpoint Number. |
|
379 | _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK)) |
402 | * Output : None. |
380 | /*----------------------------------------------------------------*/ |
403 | * Return : None. |
381 | /* ToggleDTOG_RX / ToggleDTOG_TX */ |
404 | *******************************************************************************/ |
Line 382... | Line 405... | ||
382 | /* toggles DTOG_RX / DTOG_TX bit in the endpoint register */ |
405 | #define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \ |
383 | /* IN : bEpNum = endpoint number */ |
406 | EP_DTOG_RX | _GetENDPOINT(bEpNum) & EPREG_MASK)) |
384 | /* OUT: none */ |
407 | #define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \ |
385 | /*----------------------------------------------------------------*/ |
408 | EP_DTOG_TX | _GetENDPOINT(bEpNum) & EPREG_MASK)) |
- | 409 | ||
386 | #define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \ |
410 | /******************************************************************************* |
387 | EP_DTOG_RX | _GetENDPOINT(bEpNum) & EPREG_MASK)) |
411 | * Macro Name : ClearDTOG_RX / ClearDTOG_TX. |
- | 412 | * Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register. |
|
388 | #define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \ |
413 | * Input : bEpNum: Endpoint Number. |
389 | EP_DTOG_TX | _GetENDPOINT(bEpNum) & EPREG_MASK)) |
414 | * Output : None. |
390 | /*----------------------------------------------------------------*/ |
- | |
- | 415 | * Return : None. |
|
391 | /* ClearDTOG_RX / ClearDTOG_TX */ |
416 | *******************************************************************************/ |
392 | /* IN : bEpNum = endpoint number */ |
417 | #define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\ |
393 | /* OUT: none */ |
418 | _ToggleDTOG_RX(bEpNum) |
394 | /*----------------------------------------------------------------*/ |
419 | #define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\ |
395 | #define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\ |
420 | _ToggleDTOG_TX(bEpNum) |
396 | _ToggleDTOG_RX(bEpNum) |
421 | /******************************************************************************* |
Line 397... | Line 422... | ||
397 | #define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\ |
422 | * Macro Name : SetEPAddress. |
398 | _ToggleDTOG_TX(bEpNum) |
423 | * Description : Sets address in an endpoint register. |
399 | /*----------------------------------------------------------------*/ |
424 | * Input : bEpNum: Endpoint Number. |
400 | /* SetEPAddress */ |
425 | * bAddr: Address. |
401 | /* sets address in an endpoint register */ |
426 | * Output : None. |
402 | /* IN : bEpNum = endpoint number */ |
427 | * Return : None. |
403 | /* bAddr = address */ |
428 | *******************************************************************************/ |
404 | /* OUT: none */ |
429 | |
405 | /*----------------------------------------------------------------*/ |
430 | #define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\ |
406 | 431 | _GetENDPOINT(bEpNum) & EPREG_MASK | bAddr) |
|
407 | #define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\ |
432 | /******************************************************************************* |
- | 433 | * Macro Name : GetEPAddress. |
|
408 | _GetENDPOINT(bEpNum) & EPREG_MASK | bAddr) |
434 | * Description : Gets address in an endpoint register. |
409 | /*----------------------------------------------------------------*/ |
- | |
410 | /* GetEPAddress */ |
435 | * Input : bEpNum: Endpoint Number. |
411 | /* IN : bEpNum = endpoint number */ |
436 | * Output : None. |
412 | /* OUT: none */ |
437 | * Return : None. |
413 | /*----------------------------------------------------------------*/ |
438 | *******************************************************************************/ |
Line 414... | Line 439... | ||
414 | #define _GetEPAddress(bEpNum) ((u8)(_GetENDPOINT(bEpNum) & EPADDR_FIELD)) |
439 | #define _GetEPAddress(bEpNum) ((u8)(_GetENDPOINT(bEpNum) & EPADDR_FIELD)) |
415 | /*----------------------------------------------------------------*/ |
440 | |
416 | #ifdef STR7xx /*STR7xx family*/ |
441 | #ifdef STR7xx /*STR7xx family*/ |
417 | #define _pEPTxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8 )*2 + PMAAddr)) |
442 | #define _pEPTxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8 )*2 + PMAAddr)) |
418 | #define _pEPTxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr)) |
443 | #define _pEPTxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr)) |
419 | #define _pEPRxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr)) |
444 | #define _pEPRxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr)) |
420 | #define _pEPRxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr)) |
445 | #define _pEPRxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr)) |
421 | #endif |
446 | #endif |
422 | 447 | ||
423 | #ifdef STR91x /*STR91x family*/ |
448 | #ifdef STR91x /*STR91x family*/ |
Line 424... | Line 449... | ||
424 | /* Pointers on endpoint(bEpNum) Count & Addr registers on PMA */ |
449 | /* Pointers on endpoint(bEpNum) Count & Addr registers on PMA */ |
425 | #define _pEPBufCount(bEpNum) ((u32 *)(_GetBTABLE()+bEpNum*8 + 4 + PMAAddr)) |
450 | #define _pEPBufCount(bEpNum) ((u32 *)(_GetBTABLE()+bEpNum*8 + 4 + PMAAddr)) |
426 | #define _pEPBufAddr(bEpNum) ((u32 *)(_GetBTABLE()+bEpNum*8 + PMAAddr)) |
451 | #define _pEPBufAddr(bEpNum) ((u32 *)(_GetBTABLE()+bEpNum*8 + PMAAddr)) |
427 | #endif |
452 | #endif |
428 | /*----------------------------------------------------------------*/ |
453 | /******************************************************************************* |
429 | /* SetEPTxAddr / SetEPRxAddr */ |
454 | * Macro Name : SetEPTxAddr / SetEPRxAddr. |
430 | /* sets address of the tx/rx buffer */ |
455 | * Description : sets address of the tx/rx buffer. |
431 | /* IN : bEpNum = endpoint number */ |
- | |
432 | /* wAddr = address to be set ( must be word aligned ) */ |
456 | * Input : bEpNum: Endpoint Number. |
433 | /* OUT: none */ |
457 | * wAddr: address to be set (must be word aligned). |
434 | /*----------------------------------------------------------------*/ |
458 | * Output : None. |
435 | 459 | * Return : None. |
|
Line 436... | Line 460... | ||
436 | #ifdef STR7xx /*STR7xx family*/ |
460 | *******************************************************************************/ |
437 | #define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1)) |
461 | #ifdef STR7xx /*STR7xx family*/ |
438 | #define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1)) |
462 | #define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1)) |
439 | #endif |
463 | #define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1)) |
440 | 464 | #endif |
|
441 | #ifdef STR91x /*STR91x family*/ |
465 | |
442 | #define _SetEPTxAddr(bEpNum , wAddr) {\ |
466 | #ifdef STR91x /*STR91x family*/ |
443 | *_pEPBufAddr(bEpNum) &=0xFFFF0000; \ |
467 | #define _SetEPTxAddr(bEpNum , wAddr) {\ |
444 | *_pEPBufAddr(bEpNum) |=((wAddr)&0x0FFFC);\ |
468 | *_pEPBufAddr(bEpNum) &=0xFFFF0000; \ |
445 | } |
469 | *_pEPBufAddr(bEpNum) |=((wAddr)&0x0FFFC);\ |
- | 470 | } |
|
446 | #define _SetEPRxAddr(bEpNum, wAddr) {\ |
471 | #define _SetEPRxAddr(bEpNum, wAddr) {\ |
447 | *_pEPBufAddr(bEpNum) &=0x0000FFFF;\ |
- | |
448 | *_pEPBufAddr(bEpNum) |=((wAddr<<16)&0xFFFC0000);\ |
472 | *_pEPBufAddr(bEpNum) &=0x0000FFFF;\ |
449 | } |
473 | *_pEPBufAddr(bEpNum) |=((wAddr<<16)&0xFFFC0000);\ |
450 | #endif |
474 | } |
451 | 475 | #endif |
|
452 | /*----------------------------------------------------------------*/ |
476 | |
453 | /* GetEPTxAddr / GetEPRxAddr */ |
477 | /******************************************************************************* |
454 | /* gets address of the tx/rx buffer */ |
478 | * Macro Name : GetEPTxAddr / GetEPRxAddr. |
Line 455... | Line 479... | ||
455 | /* IN : bEpNum = endpoint number */ |
479 | * Description : Gets address of the tx/rx buffer. |
456 | /* IN : */ |
480 | * Input : bEpNum: Endpoint Number. |
457 | /* OUT: address of the buffer */ |
481 | * Output : None. |
458 | /*----------------------------------------------------------------*/ |
482 | * Return : address of the buffer. |
459 | 483 | *******************************************************************************/ |
|
460 | #ifdef STR7xx /*STR7xx family*/ |
484 | #ifdef STR7xx /*STR7xx family*/ |
Line 461... | Line 485... | ||
461 | #define _GetEPTxAddr(bEpNum) ((u16)*_pEPTxAddr(bEpNum)) |
485 | #define _GetEPTxAddr(bEpNum) ((u16)*_pEPTxAddr(bEpNum)) |
462 | #define _GetEPRxAddr(bEpNum) ((u16)*_pEPRxAddr(bEpNum)) |
486 | #define _GetEPRxAddr(bEpNum) ((u16)*_pEPRxAddr(bEpNum)) |
463 | #endif |
487 | #endif |
464 | 488 | ||
465 | #ifdef STR91x /*STR91x family*/ |
489 | #ifdef STR91x /*STR91x family*/ |
466 | #define _GetEPTxAddr(bEpNum) ((u16)(*_pEPBufAddr(bEpNum) &0x0000FFFF)) |
- | |
467 | #define _GetEPRxAddr(bEpNum) ((u16)((*_pEPBufAddr(bEpNum)&0xFFFF0000)>>16)) |
- | |
Line 468... | Line 490... | ||
468 | #endif |
490 | #define _GetEPTxAddr(bEpNum) ((u16)(*_pEPBufAddr(bEpNum) &0x0000FFFF)) |
469 | /*----------------------------------------------------------------*/ |
491 | #define _GetEPRxAddr(bEpNum) ((u16)((*_pEPBufAddr(bEpNum)&0xFFFF0000)>>16)) |
470 | /* SetEPCountRxReg */ |
492 | #endif |
471 | /* sets counter of rx buffer with no. of blocks */ |
493 | /******************************************************************************* |
472 | /* IN : pdwReg = pointer to counter */ |
494 | * Macro Name : SetEPCountRxReg. |
473 | /* wCount = counter */ |
495 | * Description : Sets counter of rx buffer with no. of blocks. |
474 | /* OUT: none */ |
496 | * Input : pdwReg: pointer to counter. |
475 | /*----------------------------------------------------------------*/ |
497 | * wCount: Counter. |
476 | 498 | * Output : None. |
|
477 | #ifdef STR7xx /*STR7xx family*/ |
499 | * Return : None. |
478 | #define _BlocksOf32(dwReg,wCount,wNBlocks) {\ |
500 | *******************************************************************************/ |
- | 501 | #ifdef STR7xx /*STR7xx family*/ |
|
479 | wNBlocks = wCount >> 5;\ |
502 | #define _BlocksOf32(dwReg,wCount,wNBlocks) {\ |
Line 480... | Line 503... | ||
480 | if((wCount & 0x1f) == 0)\ |
503 | wNBlocks = wCount >> 5;\ |
481 | wNBlocks--;\ |
504 | if((wCount & 0x1f) == 0)\ |
482 | *pdwReg = (u32)((wNBlocks << 10) | 0x8000);\ |
505 | wNBlocks--;\ |
483 | }/* _BlocksOf32 */ |
506 | *pdwReg = (u32)((wNBlocks << 10) | 0x8000);\ |
484 | 507 | }/* _BlocksOf32 */ |
|
485 | #define _BlocksOf2(dwReg,wCount,wNBlocks) {\ |
508 | |
486 | wNBlocks = wCount >> 1;\ |
509 | #define _BlocksOf2(dwReg,wCount,wNBlocks) {\ |
Line 487... | Line 510... | ||
487 | if((wCount & 0x1) != 0)\ |
510 | wNBlocks = wCount >> 1;\ |
488 | wNBlocks++;\ |
511 | if((wCount & 0x1) != 0)\ |
489 | *pdwReg = (u32)(wNBlocks << 10);\ |
512 | wNBlocks++;\ |
490 | }/* _BlocksOf2 */ |
513 | *pdwReg = (u32)(wNBlocks << 10);\ |
491 | 514 | }/* _BlocksOf2 */ |
|
Line 492... | Line 515... | ||
492 | #define _SetEPCountRxReg(dwReg,wCount) {\ |
515 | |
493 | u16 wNBlocks;\ |
516 | #define _SetEPCountRxReg(dwReg,wCount) {\ |
494 | if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\ |
517 | u16 wNBlocks;\ |
495 | else {_BlocksOf2(dwReg,wCount,wNBlocks);}\ |
518 | if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\ |
496 | }/* _SetEPCountRxReg */ |
519 | else {_BlocksOf2(dwReg,wCount,wNBlocks);}\ |
497 | 520 | }/* _SetEPCountRxReg */ |
|
498 | 521 | ||
499 | 522 | #define _SetEPRxDblBuf0Count(bEpNum,wCount) {\ |
|
500 | #define _SetEPRxDblBuf0Count(bEpNum,wCount) {\ |
523 | u32 *pdwReg = _pEPTxCount(bEpNum); \ |
501 | u32 *pdwReg = _pEPTxCount(bEpNum); \ |
524 | _SetEPCountRxReg(pdwReg, wCount);\ |
502 | _SetEPCountRxReg(pdwReg, wCount);\ |
525 | } |
503 | } |
526 | #endif |
504 | #endif |
527 | /******************************************************************************* |
505 | /*----------------------------------------------------------------*/ |
528 | * Macro Name : SetEPTxCount / SetEPRxCount. |
506 | /* SetEPTxCount / SetEPRxCount */ |
529 | * Description : sets counter for the tx/rx buffer. |
507 | /* sets counter for the tx/rx buffer */ |
530 | * Input : bEpNum: endpoint number. |
508 | /* IN : bEpNum = endpoint number */ |
531 | * wCount: Counter value. |
509 | /* wCount = counter value */ |
532 | * Output : None. |
510 | /* OUT: none */ |
533 | * Return : None. |
511 | /*----------------------------------------------------------------*/ |
534 | *******************************************************************************/ |
- | 535 | ||
512 | 536 | #ifdef STR7xx /*STR7xx family*/ |
|
513 | #ifdef STR7xx /*STR7xx family*/ |
537 | #define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount) |
514 | #define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount) |
538 | #define _SetEPRxCount(bEpNum,wCount) {\ |
515 | #define _SetEPRxCount(bEpNum,wCount) {\ |
539 | u32 *pdwReg = _pEPRxCount(bEpNum); \ |
516 | u32 *pdwReg = _pEPRxCount(bEpNum); \ |
540 | _SetEPCountRxReg(pdwReg, wCount);\ |
517 | _SetEPCountRxReg(pdwReg, wCount);\ |
541 | } |
Line 518... | Line 542... | ||
518 | } |
542 | #endif |
519 | #endif |
543 | |
520 | 544 | #ifdef STR91x /*STR91x family*/ |
|
521 | #ifdef STR91x /*STR91x family*/ |
545 | #define _SetEPTxCount(bEpNum,wCount) {\ |
- | 546 | *_pEPBufCount(bEpNum) &=0xFFFFFC00;\ |
|
522 | #define _SetEPTxCount(bEpNum,wCount) {\ |
547 | *_pEPBufCount(bEpNum) |=wCount;\ |
523 | *_pEPBufCount(bEpNum) &=0xFFFFFC00;\ |
548 | } |
524 | *_pEPBufCount(bEpNum) |=wCount;\ |
549 | |
525 | } |
550 | #define _SetEPRxCount(bEpNum,wCount) {\ |
526 | 551 | u32 BLsize=0;\ |
|
527 | #define _SetEPRxCount(bEpNum,wCount) {\ |
552 | u32 Blocks;\ |
- | 553 | if (wCount < 64) Blocks = wCount>>1;\ |
|
528 | u32 BLsize=0;\ |
554 | else\ |
529 | u32 Blocks;\ |
555 | {\ |
530 | if (wCount < 64) Blocks = wCount>>1;\ |
556 | BLsize = 0x80000000;\ |
Line 531... | Line 557... | ||
531 | else\ |
557 | Blocks = wCount>>6;\ |
532 | {\ |
558 | }\ |
533 | BLsize = 0x80000000;\ |
559 | *_pEPBufCount(bEpNum) &=~0x80000000;\ |
534 | Blocks = wCount>>6;\ |
560 | *_pEPBufCount(bEpNum) |=BLsize;\ |
535 | }\ |
561 | *_pEPBufCount(bEpNum) &=0x83FFFFFF;\ |
536 | *_pEPBufCount(bEpNum) &=~0x80000000;\ |
562 | *_pEPBufCount(bEpNum) |=Blocks<<26;\ |
537 | *_pEPBufCount(bEpNum) |=BLsize;\ |
563 | *_pEPBufCount(bEpNum) &=0xFC00FFFF;\ |
- | 564 | } |
|
538 | *_pEPBufCount(bEpNum) &=0x83FFFFFF;\ |
565 | #endif |
539 | *_pEPBufCount(bEpNum) |=Blocks<<26;\ |
566 | /******************************************************************************* |
540 | *_pEPBufCount(bEpNum) &=0xFC00FFFF;\ |
567 | * Macro Name : GetEPTxCount / GetEPRxCount. |
541 | } |
568 | * Description : gets counter of the tx buffer. |
542 | #endif |
569 | * Input : bEpNum: endpoint number. |
- | 570 | * Output : None. |
|
543 | /*----------------------------------------------------------------*/ |
571 | * Return : Counter value. |
544 | /* GetEPTxCount / GetEPRxCount */ |
572 | *******************************************************************************/ |
545 | /* gets counter of the tx buffer */ |
573 | #ifdef STR7xx /*STR7xx family*/ |
546 | /* IN : bEpNum = endpoint number */ |
574 | #define _GetEPTxCount(bEpNum)((u16)(*_pEPTxCount(bEpNum)) & 0x3ff) |
547 | /* OUT: counter value */ |
575 | #define _GetEPRxCount(bEpNum)((u16)(*_pEPRxCount(bEpNum)) & 0x3ff) |
- | 576 | #endif |
|
548 | /*----------------------------------------------------------------*/ |
577 | |
549 | #ifdef STR7xx /*STR7xx family*/ |
578 | #ifdef STR91x /*STR91x family*/ |
550 | #define _GetEPTxCount(bEpNum)((u16)(*_pEPTxCount(bEpNum)) & 0x3ff) |
579 | #define _GetEPTxCount(bEpNum) (u16)(*_pEPBufCount(bEpNum)&0x3FF) |
551 | #define _GetEPRxCount(bEpNum)((u16)(*_pEPRxCount(bEpNum)) & 0x3ff) |
- | |
552 | #endif |
- | |
553 | - | ||
554 | #ifdef STR91x /*STR91x family*/ |
- | |
555 | #define _GetEPTxCount(bEpNum) (u16)(*_pEPBufCount(bEpNum)&0x3FF) |
- | |
556 | #define _GetEPRxCount(bEpNum) (u16)((*_pEPBufCount(bEpNum)&0x3FF0000)>>16) |
- | |
557 | #endif |
- | |
558 | /*----------------------------------------------------------------*/ |
- | |
559 | /* SetEPDblBuf0Addr / SetEPDblBuf1Addr */ |
- | |
Line -... | Line 580... | ||
- | 580 | #define _GetEPRxCount(bEpNum) (u16)((*_pEPBufCount(bEpNum)&0x3FF0000)>>16) |
|
- | 581 | #endif |
|
- | 582 | ||
- | 583 | /******************************************************************************* |
|
- | 584 | * Macro Name : SetEPDblBuf0Addr / SetEPDblBuf1Addr. |
|
- | 585 | * Description : Sets buffer 0/1 address in a double buffer endpoint. |
|
- | 586 | * Input : bEpNum: endpoint number. |
|
- | 587 | * : wBuf0Addr: buffer 0 address. |
|
- | 588 | * Output : None. |
|
- | 589 | * Return : None. |
|
560 | /* sets buffer 0/1 address in a double buffer endpoint */ |
590 | *******************************************************************************/ |
Line 561... | Line 591... | ||
561 | /* IN : bEpNum = endpoint number */ |
591 | #define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);} |
562 | /* wBuf0Addr = buffer 0 address */ |
592 | #define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);} |
563 | /* OUT: none */ |
593 | |
564 | /*----------------------------------------------------------------*/ |
594 | /******************************************************************************* |
565 | #define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);} |
595 | * Macro Name : SetEPDblBuffAddr. |
566 | #define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);} |
596 | * Description : Sets addresses in a double buffer endpoint. |
567 | 597 | * Input : bEpNum: endpoint number. |
|
568 | /*----------------------------------------------------------------*/ |
598 | * : wBuf0Addr: buffer 0 address. |
Line 569... | Line 599... | ||
569 | /* SetEPDblBuffAddr */ |
599 | * : wBuf1Addr = buffer 1 address. |
570 | /* sets addresses in a double buffer endpoint */ |
600 | * Output : None. |
571 | /* IN : bEpNum = endpoint number */ |
601 | * Return : None. |
572 | /* wBuf0Addr = buffer 0 address */ |
602 | *******************************************************************************/ |
573 | /* wBuf1Addr = buffer 1 address */ |
603 | #define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \ |
574 | /* OUT: none */ |
604 | _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\ |
575 | /*----------------------------------------------------------------*/ |
605 | _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\ |
576 | #define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \ |
606 | } /* _SetEPDblBuffAddr */ |
Line 577... | Line 607... | ||
577 | _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\ |
607 | |
578 | _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\ |
608 | /******************************************************************************* |
579 | } /* _SetEPDblBuffAddr */ |
609 | * Macro Name : GetEPDblBuf0Addr / GetEPDblBuf1Addr. |
580 | /*----------------------------------------------------------------*/ |
610 | * Description : Gets buffer 0/1 address of a double buffer endpoint. |
581 | /* GetEPDblBuf0Addr / GetEPDblBuf1Addr */ |
611 | * Input : bEpNum: endpoint number. |
- | 612 | * Output : None. |
|
582 | /* gets buffer 0/1 address of a double buffer endpoint */ |
613 | * Return : None. |
583 | /* IN : bEpNum = endpoint number */ |
614 | *******************************************************************************/ |
584 | /* OUT: none */ |
615 | #define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum)) |
585 | /*----------------------------------------------------------------*/ |
616 | #define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum)) |
586 | #define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum)) |
617 | |
- | 618 | /******************************************************************************* |
|
587 | #define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum)) |
619 | * Macro Name : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count. |
588 | /*----------------------------------------------------------------*/ |
620 | * Description : Gets buffer 0/1 address of a double buffer endpoint. |
589 | /* SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count */ |
621 | * Input : bEpNum: endpoint number. |
Line 590... | Line -... | ||
590 | /* sets both buffers or buff0 or buff1 counter for double buffering */ |
- | |
591 | /* IN : bEpNum = endpoint number */ |
622 | * : bDir: endpoint dir EP_DBUF_OUT = OUT |
592 | /* bDir = endpoint dir EP_DBUF_OUT = OUT */ |
623 | * EP_DBUF_IN = IN |
Line 593... | Line 624... | ||
593 | /* EP_DBUF_IN = IN */ |
624 | * : wCount: Counter value |
594 | /* wCount = counter value */ |
625 | * Output : None. |
Line 642... | Line 673... | ||
642 | u16 GetCNTR(void); |
673 | u16 GetCNTR(void); |
643 | u16 GetISTR(void); |
674 | u16 GetISTR(void); |
644 | u16 GetFNR(void); |
675 | u16 GetFNR(void); |
645 | u16 GetDADDR(void); |
676 | u16 GetDADDR(void); |
646 | u16 GetBTABLE(void); |
677 | u16 GetBTABLE(void); |
647 | void SetENDPOINT(u8 /*bEpNum*/,u16 /*wRegValue*/); |
678 | void SetENDPOINT(u8 /*bEpNum*/, u16 /*wRegValue*/); |
648 | u16 GetENDPOINT(u8 /*bEpNum*/); |
679 | u16 GetENDPOINT(u8 /*bEpNum*/); |
649 | void SetEPType(u8 /*bEpNum*/,u16 /*wType*/); |
680 | void SetEPType(u8 /*bEpNum*/, u16 /*wType*/); |
650 | u16 GetEPType(u8 /*bEpNum*/); |
681 | u16 GetEPType(u8 /*bEpNum*/); |
651 | void SetEPTxStatus(u8 /*bEpNum*/,u16 /*wState*/); |
682 | void SetEPTxStatus(u8 /*bEpNum*/, u16 /*wState*/); |
652 | void SetEPRxStatus(u8 /*bEpNum*/,u16 /*wState*/); |
683 | void SetEPRxStatus(u8 /*bEpNum*/, u16 /*wState*/); |
653 | void SetDouBleBuffEPStall(u8 /*bEpNum*/,u8 bDir); |
684 | void SetDouBleBuffEPStall(u8 /*bEpNum*/, u8 bDir); |
654 | u16 GetEPTxStatus(u8 /*bEpNum*/); |
685 | u16 GetEPTxStatus(u8 /*bEpNum*/); |
655 | u16 GetEPRxStatus(u8 /*bEpNum*/); |
686 | u16 GetEPRxStatus(u8 /*bEpNum*/); |
656 | void SetEPTxValid(u8 /*bEpNum*/); |
687 | void SetEPTxValid(u8 /*bEpNum*/); |
657 | void SetEPRxValid(u8 /*bEpNum*/); |
688 | void SetEPRxValid(u8 /*bEpNum*/); |
658 | u16 GetTxStallStatus(u8 /*bEpNum*/); |
689 | u16 GetTxStallStatus(u8 /*bEpNum*/); |
Line 667... | Line 698... | ||
667 | void ClearEP_CTR_TX(u8 /*bEpNum*/); |
698 | void ClearEP_CTR_TX(u8 /*bEpNum*/); |
668 | void ToggleDTOG_RX(u8 /*bEpNum*/); |
699 | void ToggleDTOG_RX(u8 /*bEpNum*/); |
669 | void ToggleDTOG_TX(u8 /*bEpNum*/); |
700 | void ToggleDTOG_TX(u8 /*bEpNum*/); |
670 | void ClearDTOG_RX(u8 /*bEpNum*/); |
701 | void ClearDTOG_RX(u8 /*bEpNum*/); |
671 | void ClearDTOG_TX(u8 /*bEpNum*/); |
702 | void ClearDTOG_TX(u8 /*bEpNum*/); |
672 | void SetEPAddress(u8 /*bEpNum*/,u8 /*bAddr*/); |
703 | void SetEPAddress(u8 /*bEpNum*/, u8 /*bAddr*/); |
673 | u8 GetEPAddress(u8 /*bEpNum*/); |
704 | u8 GetEPAddress(u8 /*bEpNum*/); |
674 | void SetEPTxAddr(u8 /*bEpNum*/,u16 /*wAddr*/); |
705 | void SetEPTxAddr(u8 /*bEpNum*/, u16 /*wAddr*/); |
675 | void SetEPRxAddr(u8 /*bEpNum*/,u16 /*wAddr*/); |
706 | void SetEPRxAddr(u8 /*bEpNum*/, u16 /*wAddr*/); |
676 | u16 GetEPTxAddr(u8 /*bEpNum*/); |
707 | u16 GetEPTxAddr(u8 /*bEpNum*/); |
677 | u16 GetEPRxAddr(u8 /*bEpNum*/); |
708 | u16 GetEPRxAddr(u8 /*bEpNum*/); |
678 | void SetEPCountRxReg(u32 * /*pdwReg*/, u16 /*wCount*/); |
709 | void SetEPCountRxReg(u32 * /*pdwReg*/, u16 /*wCount*/); |
679 | void SetEPTxCount(u8 /*bEpNum*/,u16 /*wCount*/); |
710 | void SetEPTxCount(u8 /*bEpNum*/, u16 /*wCount*/); |
680 | void SetEPRxCount(u8 /*bEpNum*/,u16 /*wCount*/); |
711 | void SetEPRxCount(u8 /*bEpNum*/, u16 /*wCount*/); |
681 | u16 GetEPTxCount(u8 /*bEpNum*/); |
712 | u16 GetEPTxCount(u8 /*bEpNum*/); |
682 | u16 GetEPRxCount(u8 /*bEpNum*/); |
713 | u16 GetEPRxCount(u8 /*bEpNum*/); |
683 | void SetEPDblBuf0Addr(u8 /*bEpNum*/,u16 /*wBuf0Addr*/); |
714 | void SetEPDblBuf0Addr(u8 /*bEpNum*/, u16 /*wBuf0Addr*/); |
684 | void SetEPDblBuf1Addr(u8 /*bEpNum*/,u16 /*wBuf1Addr*/); |
715 | void SetEPDblBuf1Addr(u8 /*bEpNum*/, u16 /*wBuf1Addr*/); |
685 | void SetEPDblBuffAddr(u8 /*bEpNum*/,u16 /*wBuf0Addr*/,u16 /*wBuf1Addr*/); |
716 | void SetEPDblBuffAddr(u8 /*bEpNum*/, u16 /*wBuf0Addr*/, u16 /*wBuf1Addr*/); |
686 | u16 GetEPDblBuf0Addr(u8 /*bEpNum*/); |
717 | u16 GetEPDblBuf0Addr(u8 /*bEpNum*/); |
687 | u16 GetEPDblBuf1Addr(u8 /*bEpNum*/); |
718 | u16 GetEPDblBuf1Addr(u8 /*bEpNum*/); |
688 | void SetEPDblBuffCount(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
719 | void SetEPDblBuffCount(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
689 | void SetEPDblBuf0Count(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
720 | void SetEPDblBuf0Count(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
690 | void SetEPDblBuf1Count(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
721 | void SetEPDblBuf1Count(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
691 | u16 GetEPDblBuf0Count(u8 /*bEpNum*/); |
722 | u16 GetEPDblBuf0Count(u8 /*bEpNum*/); |
692 | u16 GetEPDblBuf1Count(u8 /*bEpNum*/); |
723 | u16 GetEPDblBuf1Count(u8 /*bEpNum*/); |
693 | EP_DBUF_DIR GetEPDblBufDir(u8 /*bEpNum*/); |
724 | EP_DBUF_DIR GetEPDblBufDir(u8 /*bEpNum*/); |
694 | void FreeUserBuffer(u8 bEpNum/*bEpNum*/,u8 bDir); |
725 | void FreeUserBuffer(u8 bEpNum/*bEpNum*/, u8 bDir); |
695 | u16 ToWord(u8,u8); |
726 | u16 ToWord(u8, u8); |
696 | u16 ByteSwap(u16); |
727 | u16 ByteSwap(u16); |
Line 697... | Line 728... | ||
697 | 728 | ||
698 | #ifdef STR91x /*STR91x family*/ |
729 | #ifdef STR91x /*STR91x family*/ |
699 | /* DMA Functions */ |
730 | /* DMA Functions */ |
700 | void SetDMABurstTxSize(u8 /*DestBsize*/); |
731 | void SetDMABurstTxSize(u8 /*DestBsize*/); |
701 | void SetDMABurstRxSize(u8 /*SrcBsize*/); |
732 | void SetDMABurstRxSize(u8 /*SrcBsize*/); |
702 | void DMAUnlinkedModeTxConfig(u8 /*bEpNum*/ ,u8 /*index*/); |
733 | void DMAUnlinkedModeTxConfig(u8 /*bEpNum*/ , u8 /*index*/); |
703 | void DMAUnlinkedModeTxEnable(u8 /*index*/); |
734 | void DMAUnlinkedModeTxEnable(u8 /*index*/); |
704 | void DMAUnlinkedModeTxDisable(u8 /*index*/); |
735 | void DMAUnlinkedModeTxDisable(u8 /*index*/); |
705 | void DMAUnlinkedModeRxEnable(u8 /*bEpNum*/); |
736 | void DMAUnlinkedModeRxEnable(u8 /*bEpNum*/); |
706 | void DMAUnlinkedModeRxDisable(u8 /*bEpNum*/); |
737 | void DMAUnlinkedModeRxDisable(u8 /*bEpNum*/); |
Line 719... | Line 750... | ||
719 | #endif /* End of STR91x family*/ |
750 | #endif /* End of STR91x family*/ |
Line 720... | Line 751... | ||
720 | 751 | ||
Line 721... | Line 752... | ||
721 | #endif /* __USB_REGS_H */ |
752 | #endif /* __USB_REGS_H */ |