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| Rev 1771 | Rev 1777 | ||
|---|---|---|---|
| Line 73... | Line 73... | ||
| 73 | struct str_Data3D Data3D; |
73 | struct str_Data3D Data3D; |
| Line 74... | Line 74... | ||
| 74 | 74 | ||
| 75 | int Display_Timer, Debug_Timer,Kompass_Timer,Timer3D; |
75 | int Display_Timer, Debug_Timer,Kompass_Timer,Timer3D; |
| 76 | unsigned int DebugDataIntervall = 0, Intervall3D = 0, Display_Interval = 0; |
76 | unsigned int DebugDataIntervall = 0, Intervall3D = 0, Display_Interval = 0; |
| - | 77 | unsigned int AboTimeOut = 0; |
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| Line 77... | Line 78... | ||
| 77 | unsigned int AboTimeOut = 0; |
78 | unsigned volatile char JetiUpdateModeActive = 0; |
| 78 | 79 | ||
| 79 | const unsigned char ANALOG_TEXT[32][16] PROGMEM = |
80 | const unsigned char ANALOG_TEXT[32][16] PROGMEM = |
| 80 | { |
81 | { |
| Line 119... | Line 120... | ||
| 119 | //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
120 | //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| 120 | ISR(USART0_TX_vect) |
121 | ISR(USART0_TX_vect) |
| 121 | { |
122 | { |
| 122 | static unsigned int ptr = 0; |
123 | static unsigned int ptr = 0; |
| 123 | unsigned char tmp_tx; |
124 | unsigned char tmp_tx; |
| - | 125 | ||
| 124 | if(!UebertragungAbgeschlossen) |
126 | if(!UebertragungAbgeschlossen) |
| 125 | { |
127 | { |
| 126 | ptr++; // die [0] wurde schon gesendet |
128 | ptr++; // die [0] wurde schon gesendet |
| 127 | tmp_tx = TxdBuffer[ptr]; |
129 | tmp_tx = TxdBuffer[ptr]; |
| 128 | if((tmp_tx == '\r') || (ptr == MAX_SENDE_BUFF)) |
130 | if((tmp_tx == '\r') || (ptr == MAX_SENDE_BUFF)) |
| 129 | { |
131 | { |
| Line 143... | Line 145... | ||
| 143 | static unsigned int crc; |
145 | static unsigned int crc; |
| 144 | static unsigned char crc1,crc2,buf_ptr; |
146 | static unsigned char crc1,crc2,buf_ptr; |
| 145 | static unsigned char UartState = 0; |
147 | static unsigned char UartState = 0; |
| 146 | unsigned char CrcOkay = 0; |
148 | unsigned char CrcOkay = 0; |
| Line -... | Line 149... | ||
| - | 149 | ||
| - | 150 | if (JetiUpdateModeActive) { UDR1 = UDR0; return; } |
|
| 147 | 151 | ||
| - | 152 | SioTmp = UDR0; |
|
| - | 153 | ||
| - | 154 | ||
| 148 | SioTmp = UDR0; |
155 | |
| 149 | if(buf_ptr >= MAX_SENDE_BUFF) UartState = 0; |
156 | if(buf_ptr >= MAX_SENDE_BUFF) UartState = 0; |
| 150 | if(SioTmp == '\r' && UartState == 2) |
157 | if(SioTmp == '\r' && UartState == 2) |
| 151 | { |
158 | { |
| 152 | UartState = 0; |
159 | UartState = 0; |
| Line 165... | Line 172... | ||
| 165 | if(RxdBuffer[2] == 'R') |
172 | if(RxdBuffer[2] == 'R') |
| 166 | { |
173 | { |
| 167 | LcdClear(); |
174 | LcdClear(); |
| 168 | wdt_enable(WDTO_250MS); // Reset-Commando |
175 | wdt_enable(WDTO_250MS); // Reset-Commando |
| 169 | ServoActive = 0; |
176 | ServoActive = 0; |
| 170 | - | ||
| 171 | } |
177 | } |
| - | 178 | ||
| 172 | } |
179 | } |
| 173 | } |
180 | } |
| 174 | else |
181 | else |
| 175 | switch(UartState) |
182 | switch(UartState) |
| 176 | { |
183 | { |
| Line 458... | Line 465... | ||
| 458 | else tempchar1 = 0; // indicate error |
465 | else tempchar1 = 0; // indicate error |
| 459 | while(!UebertragungAbgeschlossen); // wait for previous frame to be sent |
466 | while(!UebertragungAbgeschlossen); // wait for previous frame to be sent |
| 460 | SendOutData('W', FC_ADDRESS,2, &tempchar1, sizeof(tempchar1), &tempchar2, sizeof(tempchar2)); |
467 | SendOutData('W', FC_ADDRESS,2, &tempchar1, sizeof(tempchar1), &tempchar2, sizeof(tempchar2)); |
| 461 | } |
468 | } |
| 462 | break; |
469 | break; |
| - | 470 | case 'j': |
|
| - | 471 | { uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU/ (8 * 38400L) - 1); |
|
| - | 472 | ||
| - | 473 | JetiUpdateModeActive = 1; |
|
| - | 474 | ||
| - | 475 | UBRR1H = (uint8_t)(ubrr>>8); |
|
| - | 476 | UBRR1L = (uint8_t)ubrr; |
|
| - | 477 | ||
| - | 478 | UBRR0H = UBRR1H; |
|
| - | 479 | UBRR0L = UBRR1L; |
|
| - | 480 | ||
| - | 481 | UCSR1C &= ~(1 << UPM11); // 0 = parity disabled |
|
| - | 482 | UCSR1C &= ~(1 << UPM10); |
|
| - | 483 | ||
| - | 484 | // 1 stop bit |
|
| - | 485 | UCSR1C &= ~(1 << USBS1); |
|
| - | 486 | UCSR0C &= ~(1 << USBS0); |
|
| - | 487 | ||
| - | 488 | // 8-bit |
|
| - | 489 | UCSR1B &= ~(1 << UCSZ12); |
|
| - | 490 | UCSR1C |= (1 << UCSZ11); |
|
| - | 491 | UCSR1C |= (1 << UCSZ10); |
|
| - | 492 | ||
| - | 493 | UCSR0B &= ~(1 << TXCIE0); |
|
| - | 494 | UCSR1B &= ~(1 << TXCIE1); |
|
| - | 495 | ||
| - | 496 | UCSR1B |= (1 << RXEN1); // enable RX |
|
| - | 497 | ||
| - | 498 | TIMSK1 &= ~_BV(ICIE1); // disable other Interrupts |
|
| - | 499 | TIMSK2 &= ~(1<<OCIE2A); |
|
| - | 500 | TIMSK0 &= ~_BV(TOIE0); |
|
| - | 501 | ||
| - | 502 | } |
|
| - | 503 | break; |
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| Line 463... | Line 504... | ||
| 463 | 504 | ||
| Line 464... | Line 505... | ||
| 464 | } // case FC_ADDRESS: |
505 | } // case FC_ADDRESS: |