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Line 82... | Line 82... | ||
82 | } SPI_State_t; |
82 | } SPI_State_t; |
Line 83... | Line 83... | ||
83 | 83 | ||
84 | //communication packets |
84 | //communication packets |
85 | volatile FromFlightCtrl_t FromFlightCtrl; |
85 | volatile FromFlightCtrl_t FromFlightCtrl; |
- | 86 | volatile ToFlightCtrl_t ToFlightCtrl; |
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- | 87 | #define SPI0_TIMEOUT 500 // 500 ms |
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Line 86... | Line 88... | ||
86 | volatile ToFlightCtrl_t ToFlightCtrl; |
88 | volatile u32 SPI0_Timeout = 0; |
87 | 89 | ||
88 | // tx packet buffer |
90 | // tx packet buffer |
89 | #define SPI_TXBUFFER_LEN (2 + sizeof(ToFlightCtrl)) // 2 bytes at start are for synchronization |
91 | #define SPI_TXBUFFER_LEN (2 + sizeof(ToFlightCtrl)) // 2 bytes at start are for synchronization |
Line 99... | Line 101... | ||
99 | #define SPI_COMMAND_INDEX 0 |
101 | #define SPI_COMMAND_INDEX 0 |
Line 100... | Line 102... | ||
100 | 102 | ||
101 | s32 FC_Kalman_K = 32; |
103 | s32 FC_Kalman_K = 32; |
102 | s32 Kalman_MaxDrift = 5 * 16; |
104 | s32 Kalman_MaxDrift = 5 * 16; |
103 | s32 Kalman_MaxFusion = 64; |
- | |
Line 104... | Line 105... | ||
104 | u32 CheckSPIOkay = 0; |
105 | s32 Kalman_MaxFusion = 64; |
105 | 106 | ||
Line 106... | Line 107... | ||
106 | u8 SPI_CommandSequence[] = { SPI_KALMAN }; |
107 | u8 SPI_CommandSequence[] = { SPI_KALMAN }; |
Line 198... | Line 199... | ||
198 | if(!SPI_RxBuffer_Request) // block writing to FromFlightCtrl on reading access |
199 | if(!SPI_RxBuffer_Request) // block writing to FromFlightCtrl on reading access |
199 | { |
200 | { |
200 | memcpy((u8 *) &FromFlightCtrl, (u8 *) SPI_RxBuffer, sizeof(FromFlightCtrl)); |
201 | memcpy((u8 *) &FromFlightCtrl, (u8 *) SPI_RxBuffer, sizeof(FromFlightCtrl)); |
201 | SPI_RxBuffer_Request = 1; |
202 | SPI_RxBuffer_Request = 1; |
202 | } |
203 | } |
- | 204 | // reset timeout counter on good packet |
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203 | CheckSPIOkay++; |
205 | SPI0_Timeout = SetDelay(SPI0_TIMEOUT); |
204 | DebugOut.Analog[13]++; |
206 | DebugOut.Analog[13]++; |
205 | } |
207 | } |
206 | else // bad checksum byte |
208 | else // bad checksum byte |
207 | { |
209 | { |
208 | DebugOut.Analog[12]++; // increase SPI chksum error counter |
210 | DebugOut.Analog[12]++; // increase SPI chksum error counter |
Line 276... | Line 278... | ||
276 | Ptr_TxChksum = (u8 *) &(((ToFlightCtrl_t *) &(SPI_TxBuffer[2]))->Chksum); |
278 | Ptr_TxChksum = (u8 *) &(((ToFlightCtrl_t *) &(SPI_TxBuffer[2]))->Chksum); |
Line 277... | Line 279... | ||
277 | 279 | ||
278 | VIC_Config(SSP0_ITLine, VIC_IRQ, PRIORITY_SPI0); |
280 | VIC_Config(SSP0_ITLine, VIC_IRQ, PRIORITY_SPI0); |
Line -... | Line 281... | ||
- | 281 | VIC_ITCmd(SSP0_ITLine, ENABLE); |
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- | 282 | ||
279 | VIC_ITCmd(SSP0_ITLine, ENABLE); |
283 | SPI0_Timeout = SetDelay(4*SPI0_TIMEOUT); |
280 | 284 | ||
Line 281... | Line 285... | ||
281 | UART1_PutString("ok"); |
285 | UART1_PutString("ok"); |
282 | } |
286 | } |