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| Rev 193 | Rev 195 | ||
|---|---|---|---|
| Line 117... | Line 117... | ||
| 117 | #define SPI_SYNC1 0 |
117 | #define SPI_SYNC1 0 |
| 118 | #define SPI_SYNC2 1 |
118 | #define SPI_SYNC2 1 |
| 119 | #define SPI_DATA 2 |
119 | #define SPI_DATA 2 |
| 120 | static u8 SPI_State = SPI_SYNC1; |
120 | static u8 SPI_State = SPI_SYNC1; |
| Line -... | Line 121... | ||
| - | 121 | ||
| - | 122 | IENABLE; |
|
| 121 | 123 | ||
| 122 | // clear pending bits |
124 | // clear pending bits |
| 123 | SSP_ClearITPendingBit(SSP0, SSP_IT_RxTimeOut); |
125 | SSP_ClearITPendingBit(SSP0, SSP_IT_RxTimeOut); |
| Line 124... | Line 126... | ||
| 124 | SSP_ClearITPendingBit(SSP0, SSP_IT_RxFifo); |
126 | SSP_ClearITPendingBit(SSP0, SSP_IT_RxFifo); |
| Line 197... | Line 199... | ||
| 197 | default: |
199 | default: |
| 198 | SPI_State = SPI_SYNC1; |
200 | SPI_State = SPI_SYNC1; |
| 199 | break; |
201 | break; |
| 200 | } |
202 | } |
| 201 | } |
203 | } |
| - | 204 | ||
| - | 205 | IDISABLE; |
|
| 202 | } |
206 | } |
| Line 203... | Line 207... | ||
| 203 | 207 | ||
| 204 | //-------------------------------------------------------------- |
208 | //-------------------------------------------------------------- |
| 205 | void SPI0_Init(void) |
209 | void SPI0_Init(void) |