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| Rev 1777 | Rev 1782 | ||
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| Line 145... | Line 145... | ||
| 145 | static unsigned int crc; |
145 | static unsigned int crc; |
| 146 | static unsigned char crc1,crc2,buf_ptr; |
146 | static unsigned char crc1,crc2,buf_ptr; |
| 147 | static unsigned char UartState = 0; |
147 | static unsigned char UartState = 0; |
| 148 | unsigned char CrcOkay = 0; |
148 | unsigned char CrcOkay = 0; |
| Line 149... | Line 149... | ||
| 149 | 149 | ||
| - | 150 | if (JetiUpdateModeActive == 1) { UDR1 = UDR0; return; } |
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| Line 150... | Line 151... | ||
| 150 | if (JetiUpdateModeActive) { UDR1 = UDR0; return; } |
151 | if (JetiUpdateModeActive == 2) { RxdBuffer[0] = UDR0; return; } |
| Line 151... | Line -... | ||
| 151 | - | ||
| 152 | SioTmp = UDR0; |
- | |
| 153 | 152 | ||
| 154 | 153 | SioTmp = UDR0; |
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| 155 | 154 | ||
| 156 | if(buf_ptr >= MAX_SENDE_BUFF) UartState = 0; |
155 | if(buf_ptr >= MAX_SENDE_BUFF) UartState = 0; |
| 157 | if(SioTmp == '\r' && UartState == 2) |
156 | if(SioTmp == '\r' && UartState == 2) |
| Line 468... | Line 467... | ||
| 468 | } |
467 | } |
| 469 | break; |
468 | break; |
| 470 | case 'j': |
469 | case 'j': |
| 471 | { uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU/ (8 * 38400L) - 1); |
470 | { uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU/ (8 * 38400L) - 1); |
| Line 472... | Line -... | ||
| 472 | - | ||
| - | 471 | ||
| Line 473... | Line -... | ||
| 473 | JetiUpdateModeActive = 1; |
- | |
| 474 | 472 | ||
| Line -... | Line 473... | ||
| - | 473 | ||
| - | 474 | cli(); |
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| 475 | UBRR1H = (uint8_t)(ubrr>>8); |
475 | |
| - | 476 | // disable receiver and transmitter |
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| 476 | UBRR1L = (uint8_t)ubrr; |
477 | UCSR0B &= ~(1 << TXEN0); |
| 477 | 478 | UCSR0B &= ~(1 << RXEN0); |
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| - | 479 | UCSR1B &= ~(1 << TXEN1); |
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| - | 480 | UCSR1B &= ~(1 << RXEN1); |
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| 478 | UBRR0H = UBRR1H; |
481 | |
| - | 482 | // disable RX-Interrupt |
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| - | 483 | UCSR0B &= ~(1 << RXCIE0); |
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| 479 | UBRR0L = UBRR1L; |
484 | UCSR1B &= ~(1 << RXCIE1); |
| Line 480... | Line 485... | ||
| 480 | 485 | // disable TX-Interrupt |
|
| 481 | UCSR1C &= ~(1 << UPM11); // 0 = parity disabled |
486 | UCSR0B &= ~(1 << TXCIE0); |
| 482 | UCSR1C &= ~(1 << UPM10); |
487 | UCSR1B &= ~(1 << TXCIE1); |
| Line 483... | Line -... | ||
| 483 | - | ||
| 484 | // 1 stop bit |
- | |
| 485 | UCSR1C &= ~(1 << USBS1); |
- | |
| 486 | UCSR0C &= ~(1 << USBS0); |
- | |
| Line -... | Line 488... | ||
| - | 488 | ||
| - | 489 | // flush receive buffer explicit |
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| - | 490 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
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| - | 491 | while ( UCSR0A & (1<<RXC0) ) UDR0; |
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| - | 492 | ||
| - | 493 | ||
| - | 494 | if (pRxData[0] == 0) |
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| - | 495 | { |
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| - | 496 | UBRR1H = (uint8_t)(ubrr>>8); |
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| - | 497 | UBRR1L = (uint8_t)ubrr; |
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| - | 498 | ||
| - | 499 | UBRR0H = UBRR1H; |
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| - | 500 | UBRR0L = UBRR1L; |
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| - | 501 | // 8-bit |
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| - | 502 | UCSR1B &= ~(1 << UCSZ12); |
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| - | 503 | UCSR1C |= (1 << UCSZ11); |
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| - | 504 | UCSR1C |= (1 << UCSZ10); |
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| - | 505 | ||
| - | 506 | UCSR1C &= ~(1 << UPM11); // 0 = parity disabled |
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| - | 507 | UCSR1C &= ~(1 << UPM10); |
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| - | 508 | JetiUpdateModeActive = 1; |
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| - | 509 | ||
| 487 | 510 | ||
| - | 511 | } |
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| 488 | // 8-bit |
512 | else JetiUpdateModeActive = 2; |
| Line 489... | Line 513... | ||
| 489 | UCSR1B &= ~(1 << UCSZ12); |
513 | |
| - | 514 | // 1 stop bit |
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| - | 515 | UCSR1C &= ~(1 << USBS1); |
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| - | 516 | UCSR0C &= ~(1 << USBS0); |
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| - | 517 | ||
| - | 518 | UCSR1B &= ~(1<<TXB81); |
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| - | 519 | ||
| - | 520 | UCSR1B |= (1 << RXEN1); // enable RX |
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| - | 521 | UCSR0B |= (1 << RXEN0); // enable RX |
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| Line 490... | Line 522... | ||
| 490 | UCSR1C |= (1 << UCSZ11); |
522 | UCSR1B |= (1 << TXEN1); // enable TX |
| 491 | UCSR1C |= (1 << UCSZ10); |
523 | UCSR0B |= (1 << TXEN0); // enable TX |
| 492 | 524 | ||
| Line -... | Line 525... | ||
| - | 525 | // ensable RX-Interrupt |
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| - | 526 | UCSR0B |= (1 << RXCIE0); |
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| 493 | UCSR0B &= ~(1 << TXCIE0); |
527 | UCSR1B |= (1 << RXCIE1); |
| 494 | UCSR1B &= ~(1 << TXCIE1); |
528 | |
| Line 495... | Line 529... | ||
| 495 | 529 | ||