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| Rev 1782 | Rev 1783 | ||
|---|---|---|---|
| Line 120... | Line 120... | ||
| 120 | //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
120 | //+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
| 121 | ISR(USART0_TX_vect) |
121 | ISR(USART0_TX_vect) |
| 122 | { |
122 | { |
| 123 | static unsigned int ptr = 0; |
123 | static unsigned int ptr = 0; |
| 124 | unsigned char tmp_tx; |
124 | unsigned char tmp_tx; |
| 125 | 125 | ||
| 126 | if(!UebertragungAbgeschlossen) |
126 | if(!UebertragungAbgeschlossen) |
| 127 | { |
127 | { |
| 128 | ptr++; // die [0] wurde schon gesendet |
128 | ptr++; // die [0] wurde schon gesendet |
| 129 | tmp_tx = TxdBuffer[ptr]; |
129 | tmp_tx = TxdBuffer[ptr]; |
| 130 | if((tmp_tx == '\r') || (ptr == MAX_SENDE_BUFF)) |
130 | if((tmp_tx == '\r') || (ptr == MAX_SENDE_BUFF)) |
| 131 | { |
131 | { |
| Line 147... | Line 147... | ||
| 147 | static unsigned char UartState = 0; |
147 | static unsigned char UartState = 0; |
| 148 | unsigned char CrcOkay = 0; |
148 | unsigned char CrcOkay = 0; |
| Line 149... | Line 149... | ||
| 149 | 149 | ||
| 150 | if (JetiUpdateModeActive == 1) { UDR1 = UDR0; return; } |
150 | if (JetiUpdateModeActive == 1) { UDR1 = UDR0; return; } |
| 151 | if (JetiUpdateModeActive == 2) { RxdBuffer[0] = UDR0; return; } |
151 | if (JetiUpdateModeActive == 2) { RxdBuffer[0] = UDR0; return; } |
| 152 | 152 | ||
| 153 | SioTmp = UDR0; |
153 | SioTmp = UDR0; |
| 154 | 154 | ||
| 155 | if(buf_ptr >= MAX_SENDE_BUFF) UartState = 0; |
155 | if(buf_ptr >= MAX_SENDE_BUFF) UartState = 0; |
| 156 | if(SioTmp == '\r' && UartState == 2) |
156 | if(SioTmp == '\r' && UartState == 2) |
| 157 | { |
157 | { |
| 158 | UartState = 0; |
158 | UartState = 0; |
| Line 172... | Line 172... | ||
| 172 | { |
172 | { |
| 173 | LcdClear(); |
173 | LcdClear(); |
| 174 | wdt_enable(WDTO_250MS); // Reset-Commando |
174 | wdt_enable(WDTO_250MS); // Reset-Commando |
| 175 | ServoActive = 0; |
175 | ServoActive = 0; |
| 176 | } |
176 | } |
| 177 | 177 | ||
| 178 | } |
178 | } |
| 179 | } |
179 | } |
| 180 | else |
180 | else |
| 181 | switch(UartState) |
181 | switch(UartState) |
| 182 | { |
182 | { |
| Line 464... | Line 464... | ||
| 464 | else tempchar1 = 0; // indicate error |
464 | else tempchar1 = 0; // indicate error |
| 465 | while(!UebertragungAbgeschlossen); // wait for previous frame to be sent |
465 | while(!UebertragungAbgeschlossen); // wait for previous frame to be sent |
| 466 | SendOutData('W', FC_ADDRESS,2, &tempchar1, sizeof(tempchar1), &tempchar2, sizeof(tempchar2)); |
466 | SendOutData('W', FC_ADDRESS,2, &tempchar1, sizeof(tempchar1), &tempchar2, sizeof(tempchar2)); |
| 467 | } |
467 | } |
| 468 | break; |
468 | break; |
| 469 | case 'j': |
469 | case 'j': |
| 470 | { uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU/ (8 * 38400L) - 1); |
- | |
| 471 | - | ||
| 472 | - | ||
| 473 | - | ||
| 474 | cli(); |
- | |
| 475 | - | ||
| 476 | // disable receiver and transmitter |
- | |
| 477 | UCSR0B &= ~(1 << TXEN0); |
- | |
| 478 | UCSR0B &= ~(1 << RXEN0); |
- | |
| 479 | UCSR1B &= ~(1 << TXEN1); |
- | |
| 480 | UCSR1B &= ~(1 << RXEN1); |
- | |
| 481 | - | ||
| 482 | // disable RX-Interrupt |
- | |
| 483 | UCSR0B &= ~(1 << RXCIE0); |
- | |
| 484 | UCSR1B &= ~(1 << RXCIE1); |
- | |
| 485 | // disable TX-Interrupt |
- | |
| 486 | UCSR0B &= ~(1 << TXCIE0); |
- | |
| 487 | UCSR1B &= ~(1 << TXCIE1); |
470 | tempchar1 = LIBFC_GetCPUType(); |
| 488 | - | ||
| 489 | // flush receive buffer explicit |
- | |
| 490 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
471 | if((tempchar1 == CPU_ATMEGA644P) || (tempchar1 == CPU_ATMEGA1284P)) |
| 491 | while ( UCSR0A & (1<<RXC0) ) UDR0; |
- | |
| 492 | - | ||
| 493 | - | ||
| 494 | if (pRxData[0] == 0) |
- | |
| 495 | { |
472 | { |
| 496 | UBRR1H = (uint8_t)(ubrr>>8); |
- | |
| 497 | UBRR1L = (uint8_t)ubrr; |
- | |
| 498 | - | ||
| 499 | UBRR0H = UBRR1H; |
- | |
| 500 | UBRR0L = UBRR1L; |
- | |
| 501 | // 8-bit |
- | |
| 502 | UCSR1B &= ~(1 << UCSZ12); |
- | |
| 503 | UCSR1C |= (1 << UCSZ11); |
- | |
| 504 | UCSR1C |= (1 << UCSZ10); |
- | |
| 505 | - | ||
| 506 | UCSR1C &= ~(1 << UPM11); // 0 = parity disabled |
473 | uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU/ (8 * 38400L) - 1); |
| 507 | UCSR1C &= ~(1 << UPM10); |
- | |
| 508 | JetiUpdateModeActive = 1; |
- | |
| Line -... | Line 474... | ||
| - | 474 | ||
| 509 | 475 | cli(); |
|
| - | 476 | ||
| - | 477 | // UART0 & UART1 disable RX and TX-Interrupt |
|
| - | 478 | UCSR0B &= ~((1 << RXCIE0)|(1 << TXCIE0)); |
|
| - | 479 | UCSR1B &= ~((1 << RXCIE1)|(1 << TXCIE1)); |
|
| - | 480 | ||
| - | 481 | // UART0 & UART1 disable receiver and transmitter |
|
| - | 482 | UCSR0B &= ~((1 << TXEN0) | (1 << RXEN0)); |
|
| - | 483 | UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1)); |
|
| - | 484 | ||
| - | 485 | // UART0 & UART1 flush receive buffer explicit |
|
| - | 486 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
|
| - | 487 | while ( UCSR0A & (1<<RXC0) ) UDR0; |
|
| - | 488 | ||
| - | 489 | ||
| - | 490 | if (pRxData[0] == 0) |
|
| - | 491 | { |
|
| - | 492 | JetiUpdateModeActive = 1; |
|
| - | 493 | ||
| - | 494 | // UART0 & UART1 set baudrate |
|
| - | 495 | UBRR1H = (uint8_t)(ubrr>>8); |
|
| - | 496 | UBRR1L = (uint8_t)ubrr; |
|
| - | 497 | UBRR0H = UBRR1H; |
|
| - | 498 | UBRR0L = UBRR1L; |
|
| - | 499 | // UART1 no parity |
|
| - | 500 | UCSR1C &= ~(1 << UPM11); |
|
| - | 501 | UCSR1C &= ~(1 << UPM10); |
|
| - | 502 | // UART1 8-bit |
|
| - | 503 | UCSR1B &= ~(1 << UCSZ12); |
|
| - | 504 | UCSR1C |= (1 << UCSZ11); |
|
| 510 | 505 | UCSR1C |= (1 << UCSZ10); |
|
| 511 | } |
506 | } |
| - | 507 | else JetiUpdateModeActive = 2; |
|
| - | 508 | ||
| - | 509 | // UART0 & UART1 1 stop bit |
|
| - | 510 | UCSR1C &= ~(1 << USBS1); |
|
| - | 511 | UCSR0C &= ~(1 << USBS0); |
|
| - | 512 | // UART1 clear 9th bit |
|
| - | 513 | UCSR1B &= ~(1<<TXB81); |
|
| - | 514 | // enable receiver and transmitter for UART0 and UART1 |
|
| - | 515 | UCSR0B |= (1 << TXEN0) | (1 << RXEN0); |
|
| - | 516 | UCSR1B |= (1 << TXEN1) | (1 << RXEN1); |
|
| - | 517 | // enable RX-Interrupt for UART0 and UART1 |
|
| - | 518 | UCSR0B |= (1 << RXCIE0); |
|
| - | 519 | UCSR1B |= (1 << RXCIE1); |
|
| - | 520 | // disable other Interrupts |
|
| - | 521 | TIMSK0 = 0; |
|
| - | 522 | TIMSK1 = 0; |
|
| Line 512... | Line -... | ||
| 512 | else JetiUpdateModeActive = 2; |
- | |
| 513 | - | ||
| 514 | // 1 stop bit |
- | |
| 515 | UCSR1C &= ~(1 << USBS1); |
- | |
| 516 | UCSR0C &= ~(1 << USBS0); |
- | |
| 517 | - | ||
| 518 | UCSR1B &= ~(1<<TXB81); |
- | |
| 519 | - | ||
| 520 | UCSR1B |= (1 << RXEN1); // enable RX |
- | |
| 521 | UCSR0B |= (1 << RXEN0); // enable RX |
- | |
| 522 | UCSR1B |= (1 << TXEN1); // enable TX |
- | |
| 523 | UCSR0B |= (1 << TXEN0); // enable TX |
- | |
| 524 | - | ||
| 525 | // ensable RX-Interrupt |
- | |
| 526 | UCSR0B |= (1 << RXCIE0); |
- | |
| 527 | UCSR1B |= (1 << RXCIE1); |
- | |
| 528 | - | ||
| 529 | - | ||
| 530 | TIMSK1 &= ~_BV(ICIE1); // disable other Interrupts |
- | |
| 531 | TIMSK2 &= ~(1<<OCIE2A); |
- | |
| 532 | TIMSK0 &= ~_BV(TOIE0); |
523 | TIMSK2 = 0; |
| 533 | - | ||
| 534 | sei(); |
524 | |
| 535 | 525 | sei(); |
|
| Line 536... | Line 526... | ||
| 536 | } |
526 | } |