Rev 701 | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 701 | Rev 702 | ||
|---|---|---|---|
| Line 34... | Line 34... | ||
| 34 | // disable RX-Interrupt |
34 | // disable RX-Interrupt |
| 35 | UCSR1B &= ~(1 << RXCIE1); |
35 | UCSR1B &= ~(1 << RXCIE1); |
| 36 | // disable TX-Interrupt |
36 | // disable TX-Interrupt |
| 37 | UCSR1B &= ~(1 << TXCIE1); |
37 | UCSR1B &= ~(1 << TXCIE1); |
| 38 | // disable DRE-Interrupt |
38 | // disable DRE-Interrupt |
| 39 | UCSR1B |= (1 << UDRIE1); |
39 | UCSR1B &= ~(1 << UDRIE1); |
| 40 | - | ||
| 41 | // disable receiver and transmitter (will flush the buffers) |
- | |
| 42 | UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1)); |
- | |
| Line 43... | Line 40... | ||
| 43 | 40 | ||
| 44 | // set direction of RXD1 and TXD1 pins |
41 | // set direction of RXD1 and TXD1 pins |
| 45 | // set RXD1 (PD2) as an input pin |
- | |
| 46 | DDRD &= ~(1 << DDD2); |
42 | // set RXD1 (PD2) as an input pin |
| - | 43 | PORTD |= (1 << PORTD2); |
|
| Line 47... | Line 44... | ||
| 47 | PORTD |= (1 << PORTD2); |
44 | DDRD &= ~(1 << DDD2); |
| 48 | - | ||
| 49 | // set TXD1 (PD3) as an output pin |
45 | |
| - | 46 | // set TXD1 (PD3) as an output pin |
|
| Line 50... | Line 47... | ||
| 50 | DDRD |= (1 << DDD3); |
47 | PORTD |= (1 << PORTD3); |
| 51 | PORTD |= (1 << PORTD3); |
48 | DDRD |= (1 << DDD3); |
| 52 | 49 | ||
| 53 | // USART0 Baud Rate Register |
50 | // USART0 Baud Rate Register |
| Line 77... | Line 74... | ||
| 77 | 74 | ||
| 78 | // enable interrupts at the end |
75 | // enable interrupts at the end |
| 79 | // enable RX-Interrupt |
76 | // enable RX-Interrupt |
| 80 | UCSR1B |= (1 << RXCIE1); |
77 | UCSR1B |= (1 << RXCIE1); |
| 81 | // enable TX-Interrupt |
78 | // enable TX-Interrupt |
| 82 | //UCSR1B |= (1 << TXCIE1); |
79 | UCSR1B |= (1 << TXCIE1); |
| 83 | // enable DRE interrupt |
80 | // enable DRE interrupt |
| Line 84... | Line 81... | ||
| 84 | //UCSR1B |= (1 << UDRIE1); |
81 | //UCSR1B |= (1 << UDRIE1); |
| 85 | 82 | ||
| Line 86... | Line 83... | ||
| 86 | 83 | ||
| 87 | // restore global interrupt flags |
84 | // restore global interrupt flags |
| 88 | SREG = sreg; |
85 | SREG = sreg; |
| 89 | 86 | ||
| Line 90... | Line 87... | ||
| 90 | // inint FIFO buffer |
87 | // inint FIFO buffer |
| 91 | //fifo_init (&infifo, inbuf, BUFSIZE_IN); |
88 | //fifo_init (&infifo, inbuf, BUFSIZE_IN); |
| 92 | fifo_init (&outfifo, outbuf, BUFSIZE_OUT); |
89 | //fifo_init (&outfifo, outbuf, BUFSIZE_OUT); |
| 93 | } |
90 | } |
| 94 | 91 | ||
| Line 95... | Line 92... | ||
| 95 | int16_t USART1_putc (const uint8_t c) |
92 | /*int16_t USART1_putc (const uint8_t c) |
| 96 | { |
93 | { |
| 97 | int16_t ret = fifo_put (&outfifo, c); |
94 | int16_t ret = fifo_put (&outfifo, c); |
| 98 | // create an data register empty interrupt |
95 | // create an data register empty interrupt |
| 99 | UCSR1B |= (1 << UDRIE1); |
96 | UCSR1B |= (1 << UDRIE1); |
| 100 | 97 | ||
| 101 | return ret; |
98 | return ret; |
| Line 114... | Line 111... | ||
| 114 | */ |
111 | */ |
| Line 115... | Line 112... | ||
| 115 | 112 | ||
| 116 | /****************************************************************/ |
113 | /****************************************************************/ |
| 117 | /* USART1 data register empty ISR */ |
114 | /* USART1 data register empty ISR */ |
| 118 | /****************************************************************/ |
115 | /****************************************************************/ |
| 119 | ISR(USART1_UDRE_vect) |
116 | /*ISR(USART1_UDRE_vect) |
| 120 | { |
117 | { |
| 121 | // Move a character from the output buffer to the data register. |
118 | // Move a character from the output buffer to the data register. |
| 122 | // When the character was processed the next interrupt is generated. |
119 | // When the character was processed the next interrupt is generated. |
| 123 | // If the output buffer is empty the DRE-interrupt is disabled. |
120 | // If the output buffer is empty the DRE-interrupt is disabled. |
| 124 | if (outfifo.count > 0) |
121 | if (outfifo.count > 0) |
| 125 | UDR1 = _inline_fifo_get (&outfifo); |
122 | UDR1 = _inline_fifo_get (&outfifo); |
| 126 | else |
123 | else |
| 127 | UCSR1B &= ~(1 << UDRIE1); |
124 | UCSR1B &= ~(1 << UDRIE1); |
| - | 125 | } |
|
| Line 128... | Line 126... | ||
| 128 | } |
126 | */ |
| 129 | 127 | ||
| 130 | /****************************************************************/ |
128 | /****************************************************************/ |
| 131 | /* USART1 transmitter ISR */ |
129 | /* USART1 transmitter ISR */ |
| 132 | /****************************************************************/ |
130 | /****************************************************************/ |
| Line 133... | Line 131... | ||
| 133 | ISR(USART1_TX_vect) |
131 | /*ISR(USART1_TX_vect) |
| 134 | { |
132 | { |
| 135 | 133 | ||
| 136 | } |
134 | } |
| 137 | 135 | */ |
|
| 138 | /****************************************************************/ |
136 | /****************************************************************/ |
| 139 | /* USART1 receiver ISR */ |
137 | /* USART1 receiver ISR */ |
| 140 | /****************************************************************/ |
138 | /****************************************************************/ |
| 141 | ISR(USART1_RX_vect) |
139 | ISR(USART1_RX_vect) |
| 142 | { |
140 | { |
| 143 | uint8_t c; |
141 | uint8_t c; |