Subversion Repositories FlightCtrl

Rev

Rev 773 | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 773 Rev 781
Line 79... Line 79...
79 
        // set SCK (PB7), MOSI (PB5) as output
 79 
        // set SCK (PB7), MOSI (PB5) as output
80 
        DDRB |= (1<<DDB7)|(1<<DDB5);
 80 
        DDRB |= (1<<DDB7)|(1<<DDB5);
81 
        // set MISO (PB6) as input
 81 
        // set MISO (PB6) as input
82 
        DDRB &= ~(1<<DDB6);
 82 
        DDRB &= ~(1<<DDB6);
Line -... Line 83...
- 
 
 83 
 
- 
 
 84 
#ifdef USE_WALTER_EXT // walthers board
- 
 
 85 
        // Output Pins (J9)PC6->MM3_SS ,(J8)PB2->MM3_RESET
- 
 
 86 
        DDRB |= (1<<DDB2);
- 
 
 87 
        DDRC |= (1<<DDC6);
- 
 
 88 
        // set pins permanent to low
- 
 
 89 
        PORTB &= ~((1<<PORTB2));
- 
 
 90 
        PORTC &= ~((1<<PORTC6));
83 
 
 91 
#else // killagregs board
84 
        // Output Pins PC4->MM3_SS ,PC5->MM3_RESET
 92 
        // Output Pins PC4->MM3_SS ,PC5->MM3_RESET
85 
        DDRC |= (1<<DDC4)|(1<<DDC5);
 93 
        DDRC |= (1<<DDC4)|(1<<DDC5);
86 
        // set pins permanent to low
 94 
        // set pins permanent to low
- 
 
 95 
        PORTC &= ~((1<<PORTC4)|(1<<PORTC5));
Line 87... Line 96...
87 
        PORTC &= ~((1<<PORTC4)|(1<<PORTC5));
 96 
#endif
88 
 
 97 
 
89 
        // Initialize SPI-Interface
 98 
        // Initialize SPI-Interface
90 
        // Enable interrupt (SPIE=1)
 99 
        // Enable interrupt (SPIE=1)
91 
        // Enable SPI bus (SPE=1)
 100 
        // Enable SPI bus (SPE=1)
92 
        // MSB transmitted first (DORD = 0)
 101 
        // MSB transmitted first (DORD = 0)
93 
        // Master SPI Mode (MSTR=1)
 102 
        // Master SPI Mode (MSTR=1)
94 
        // Clock polarity low whn idle (CPOL=0)
 103 
        // Clock polarity low when idle (CPOL=0)
95 
        // clock phase sample at leading edge (CPHA=0)
 104 
        // Clock phase sample at leading edge (CPHA=0)
96 
        // clock rate = SYSCLK/128 (SPI2X=0, SPR1=1, SPR0=1) 20MHz/128 = 156.25kHz
 105 
        // Clock rate = SYSCLK/128 (SPI2X=0, SPR1=1, SPR0=1) 20MHz/128 = 156.25kHz
Line 97... Line 106...
97 
        SPCR = (1<<SPIE)|(1<<SPE)|(0<<DORD)|(1<<MSTR)|(0<<CPOL)|(0<<CPHA)|(1<<SPR1)|(1<<SPR0);
 106 
        SPCR = (1<<SPIE)|(1<<SPE)|(0<<DORD)|(1<<MSTR)|(0<<CPOL)|(0<<CPHA)|(1<<SPR1)|(1<<SPR0);
98 
        SPSR &= ~(1<<SPI2X);
 107 
        SPSR &= ~(1<<SPI2X);
Line 121... Line 130...
121 
void MM3_Update(void) // called every 102.4 µs by timer 0 ISR
 130 
void MM3_Update(void) // called every 102.4 µs by timer 0 ISR
122 
{
 131 
{
123 
        switch (MM3.STATE)
 132 
        switch (MM3.STATE)
124 
        {
 133 
        {
125 
        case MM3_STATE_RESET:
 134 
        case MM3_STATE_RESET:
- 
 
 135 
                #ifdef USE_WALTER_EXT // walthers board
- 
 
 136 
                PORTC &= ~(1<<PORTC6);  // select slave
- 
 
 137 
                PORTB |= (1<<PORTB2);   // PB2 to High, MM3 Reset
- 
 
 138 
                #else
126 
                PORTC &= ~(1<<PORTC4);  // select slave
 139 
                PORTC &= ~(1<<PORTC4);  // select slave
127 
                PORTC |= (1<<PORTC5);   // PC5 to High, MM3 Reset
 140 
                PORTC |= (1<<PORTC5);   // PC5 to High, MM3 Reset
- 
 
 141 
                #endif
128 
                MM3.STATE = MM3_STATE_START_TRANSFER;
 142 
                MM3.STATE = MM3_STATE_START_TRANSFER;
129 
                return;
 143 
                return;
Line 130... Line 144...
130 
 
 144 
 
- 
 
 145 
        case MM3_STATE_START_TRANSFER:
- 
 
 146 
                #ifdef USE_WALTER_EXT // walthers board
- 
 
 147 
                PORTB &= ~(1<<PORTB2);  // PB2 auf Low (was 102.4 µs at high level)
131 
        case MM3_STATE_START_TRANSFER:
 148 
                #else
132 
                PORTC &= ~(1<<PORTC5);  // PC4 auf Low (was 102.4 µs at high level)
 149 
                PORTC &= ~(1<<PORTC5);  // PC4 auf Low (was 102.4 µs at high level)
133 
 
 150 
                #endif
134 
                // write to SPDR triggers automatically the transfer MOSI MISO
 151 
                // write to SPDR triggers automatically the transfer MOSI MISO
135 
                // MM3 Period, + AXIS code
 152 
                // MM3 Period, + AXIS code
136 
                switch(MM3.AXIS)
 153 
                switch(MM3.AXIS)
137 
                {
 154 
                {
Line 209... Line 226...
209 
                        default:
 226 
                        default:
210 
                                MM3.AXIS = MM3_X_AXIS;
 227 
                                MM3.AXIS = MM3_X_AXIS;
211 
                                break;
 228 
                                break;
212 
                        }
 229 
                        }
213 
                }
 230 
                }
- 
 
 231 
                #ifdef USE_WALTER_EXT // walthers board
- 
 
 232 
                PORTC |= (1<<PORTC6); // deselect slave
- 
 
 233 
                #else
214 
                PORTC |= (1<<PORTC4); // deselect slave
 234 
                PORTC |= (1<<PORTC4); // deselect slave
- 
 
 235 
                #endif
215 
                MM3.STATE = MM3_STATE_RESET;
 236 
                MM3.STATE = MM3_STATE_RESET;
216 
                // Update timeout is called every 102.4 µs.
 237 
                // Update timeout is called every 102.4 µs.
217 
                // It takes 2 cycles to write a measurement data request for one axis and
 238 
                // It takes 2 cycles to write a measurement data request for one axis and
218 
                // at at least 8 ms / 102.4 µs = 79 cycles to read the requested data back.
 239 
                // at at least 8 ms / 102.4 µs = 79 cycles to read the requested data back.
219 
                // I.e. 81 cycles * 102.4 µs = 8.3ms per axis.
 240 
                // I.e. 81 cycles * 102.4 µs = 8.3ms per axis.