Rev 194 | Rev 196 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 194 | Rev 195 | ||
|---|---|---|---|
| Line 265... | Line 265... | ||
| 265 | void UART1_IRQHandler(void) |
265 | void UART1_IRQHandler(void) |
| 266 | { |
266 | { |
| 267 | static u8 abortState = 0; |
267 | static u8 abortState = 0; |
| 268 | u8 c; |
268 | u8 c; |
| Line -... | Line 269... | ||
| - | 269 | ||
| - | 270 | IENABLE; |
|
| 269 | 271 | ||
| 270 | if((UART_GetITStatus(UART1, UART_IT_Receive) != RESET) || (UART_GetITStatus(UART1, UART_IT_ReceiveTimeOut) != RESET) ) |
272 | if((UART_GetITStatus(UART1, UART_IT_Receive) != RESET) || (UART_GetITStatus(UART1, UART_IT_ReceiveTimeOut) != RESET) ) |
| 271 | { |
273 | { |
| 272 | // clear the pending bits! |
274 | // clear the pending bits! |
| 273 | UART_ClearITPendingBit(UART1, UART_IT_Receive); |
275 | UART_ClearITPendingBit(UART1, UART_IT_Receive); |
| Line 334... | Line 336... | ||
| 334 | //fifo_purge(&UART1_rx_fifo); // flush the whole buffer |
336 | //fifo_purge(&UART1_rx_fifo); // flush the whole buffer |
| 335 | } |
337 | } |
| 336 | } // EOF while some byes in the hardware fifo |
338 | } // EOF while some byes in the hardware fifo |
| 337 | } // eof DebugUart = UART1 |
339 | } // eof DebugUart = UART1 |
| 338 | } |
340 | } |
| - | 341 | ||
| - | 342 | IDISABLE; |
|
| 339 | } |
343 | } |
| Line 340... | Line 344... | ||
| 340 | 344 | ||
| 341 | /**************************************************************/ |
345 | /**************************************************************/ |
| 342 | /* Process incomming data from debug uart */ |
346 | /* Process incomming data from debug uart */ |