Rev 1782 | Go to most recent revision | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 1782 | Rev 1783 | ||
|---|---|---|---|
| Line 465... | Line 465... | ||
| 465 | while(!UebertragungAbgeschlossen); // wait for previous frame to be sent |
465 | while(!UebertragungAbgeschlossen); // wait for previous frame to be sent |
| 466 | SendOutData('W', FC_ADDRESS,2, &tempchar1, sizeof(tempchar1), &tempchar2, sizeof(tempchar2)); |
466 | SendOutData('W', FC_ADDRESS,2, &tempchar1, sizeof(tempchar1), &tempchar2, sizeof(tempchar2)); |
| 467 | } |
467 | } |
| 468 | break; |
468 | break; |
| 469 | case 'j': |
469 | case 'j': |
| - | 470 | tempchar1 = LIBFC_GetCPUType(); |
|
| - | 471 | if((tempchar1 == CPU_ATMEGA644P) || (tempchar1 == CPU_ATMEGA1284P)) |
|
| - | 472 | { |
|
| 470 | { uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU/ (8 * 38400L) - 1); |
473 | uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU/ (8 * 38400L) - 1); |
| 471 | - | ||
| 472 | - | ||
| Line 473... | Line 474... | ||
| 473 | 474 | ||
| Line 474... | Line 475... | ||
| 474 | cli(); |
475 | cli(); |
| 475 | - | ||
| 476 | // disable receiver and transmitter |
476 | |
| 477 | UCSR0B &= ~(1 << TXEN0); |
- | |
| 478 | UCSR0B &= ~(1 << RXEN0); |
477 | // UART0 & UART1 disable RX and TX-Interrupt |
| 479 | UCSR1B &= ~(1 << TXEN1); |
478 | UCSR0B &= ~((1 << RXCIE0)|(1 << TXCIE0)); |
| 480 | UCSR1B &= ~(1 << RXEN1); |
- | |
| 481 | - | ||
| 482 | // disable RX-Interrupt |
- | |
| 483 | UCSR0B &= ~(1 << RXCIE0); |
479 | UCSR1B &= ~((1 << RXCIE1)|(1 << TXCIE1)); |
| 484 | UCSR1B &= ~(1 << RXCIE1); |
480 | |
| 485 | // disable TX-Interrupt |
481 | // UART0 & UART1 disable receiver and transmitter |
| Line 486... | Line 482... | ||
| 486 | UCSR0B &= ~(1 << TXCIE0); |
482 | UCSR0B &= ~((1 << TXEN0) | (1 << RXEN0)); |
| 487 | UCSR1B &= ~(1 << TXCIE1); |
483 | UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1)); |
| 488 | 484 | ||
| Line 489... | Line 485... | ||
| 489 | // flush receive buffer explicit |
485 | // UART0 & UART1 flush receive buffer explicit |
| 490 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
486 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
| - | 487 | while ( UCSR0A & (1<<RXC0) ) UDR0; |
|
| - | 488 | ||
| - | 489 | ||
| 491 | while ( UCSR0A & (1<<RXC0) ) UDR0; |
490 | if (pRxData[0] == 0) |
| 492 | 491 | { |
|
| 493 | - | ||
| 494 | if (pRxData[0] == 0) |
492 | JetiUpdateModeActive = 1; |
| 495 | { |
493 | |
| - | 494 | // UART0 & UART1 set baudrate |
|
| - | 495 | UBRR1H = (uint8_t)(ubrr>>8); |
|
| - | 496 | UBRR1L = (uint8_t)ubrr; |
|
| 496 | UBRR1H = (uint8_t)(ubrr>>8); |
497 | UBRR0H = UBRR1H; |
| 497 | UBRR1L = (uint8_t)ubrr; |
498 | UBRR0L = UBRR1L; |
| 498 | 499 | // UART1 no parity |
|
| 499 | UBRR0H = UBRR1H; |
500 | UCSR1C &= ~(1 << UPM11); |
| 500 | UBRR0L = UBRR1L; |
- | |
| 501 | // 8-bit |
- | |
| 502 | UCSR1B &= ~(1 << UCSZ12); |
- | |
| 503 | UCSR1C |= (1 << UCSZ11); |
- | |
| 504 | UCSR1C |= (1 << UCSZ10); |
- | |
| 505 | - | ||
| 506 | UCSR1C &= ~(1 << UPM11); // 0 = parity disabled |
501 | UCSR1C &= ~(1 << UPM10); |
| 507 | UCSR1C &= ~(1 << UPM10); |
502 | // UART1 8-bit |
| Line 508... | Line 503... | ||
| 508 | JetiUpdateModeActive = 1; |
503 | UCSR1B &= ~(1 << UCSZ12); |
| 509 | 504 | UCSR1C |= (1 << UCSZ11); |
|
| 510 | 505 | UCSR1C |= (1 << UCSZ10); |
|
| 511 | } |
- | |
| - | 506 | } |
|
| 512 | else JetiUpdateModeActive = 2; |
507 | else JetiUpdateModeActive = 2; |
| 513 | - | ||
| 514 | // 1 stop bit |
508 | |
| 515 | UCSR1C &= ~(1 << USBS1); |
509 | // UART0 & UART1 1 stop bit |
| 516 | UCSR0C &= ~(1 << USBS0); |
510 | UCSR1C &= ~(1 << USBS1); |
| 517 | - | ||
| 518 | UCSR1B &= ~(1<<TXB81); |
- | |
| 519 | 511 | UCSR0C &= ~(1 << USBS0); |
|
| 520 | UCSR1B |= (1 << RXEN1); // enable RX |
512 | // UART1 clear 9th bit |
| 521 | UCSR0B |= (1 << RXEN0); // enable RX |
513 | UCSR1B &= ~(1<<TXB81); |
| 522 | UCSR1B |= (1 << TXEN1); // enable TX |
- | |
| 523 | UCSR0B |= (1 << TXEN0); // enable TX |
- | |
| 524 | 514 | // enable receiver and transmitter for UART0 and UART1 |
|
| - | 515 | UCSR0B |= (1 << TXEN0) | (1 << RXEN0); |
|
| 525 | // ensable RX-Interrupt |
516 | UCSR1B |= (1 << TXEN1) | (1 << RXEN1); |
| 526 | UCSR0B |= (1 << RXCIE0); |
517 | // enable RX-Interrupt for UART0 and UART1 |
| Line 527... | Line 518... | ||
| 527 | UCSR1B |= (1 << RXCIE1); |
518 | UCSR0B |= (1 << RXCIE0); |
| 528 | - | ||
| 529 | 519 | UCSR1B |= (1 << RXCIE1); |
|
| 530 | TIMSK1 &= ~_BV(ICIE1); // disable other Interrupts |
520 | // disable other Interrupts |
| Line 531... | Line 521... | ||
| 531 | TIMSK2 &= ~(1<<OCIE2A); |
521 | TIMSK0 = 0; |