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Rev 1796 Rev 1821
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        UCSR1B &= ~(1 << UCSZ12);
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        UCSR1B &= ~(1 << UCSZ12);
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        UCSR1C |=  (1 << UCSZ11);
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        UCSR1C |= (1 << UCSZ11);
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        UCSR1C |=  (1 << UCSZ10);
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        UCSR1C |= (1 << UCSZ10);
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        // flush receive buffer explicit
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        // flush receive buffer explicit
- 
 
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        while (UCSR1A & (1 << RXC1))
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        while ( UCSR1A & (1<<RXC1) ) UDR1;
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                UDR1;
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        // enable interrupts at the end
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        // enable interrupts at the end
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        // enable RX-Interrupt
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        // enable RX-Interrupt
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}
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 }
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*/
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 */
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/****************************************************************/
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/****************************************************************/
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/*               USART1 receiver ISR                            */
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/*               USART1 receiver ISR                            */
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/****************************************************************/
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/****************************************************************/
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ISR(USART1_RX_vect) {
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ISR(USART1_RX_vect)
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{
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        uint8_t c;
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        uint8_t c;
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        c = UDR1; // get data byte
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        c = UDR1; // get data byte
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        #ifdef USE_RC_DSL
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#ifdef USE_RC_DSL
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        dsl_parser(c);                  // parse dsl data stream
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        dsl_parser(c); // parse dsl data stream
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        #endif
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#endif