WebSVN - NaviCtrl - Diff - Rev 369 and 376


 
        .include "startup_generic.s"
 
# reference to external interrupt handlers
#
                .extern SWI_Handler
                .extern Prefetch_Handler
                .extern Abort_Handler
                .extern Undefined_Handler
                .extern FIQ_Handler
 
 
	.equ	VectorAddress,		0xFFFFF030	/* VIC Vector address register address. */
	.equ	VectorAddressDaisy,	0xFC000030	/* Daisy VIC Vector address register */
 
 
#		
# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
#
        .equ    Mode_USR,   0x10
        .equ    Mode_FIQ,   0x11
        .equ    Mode_IRQ,   0x12
        .equ    Mode_SVC,   0x13
        .equ    Mode_ABT,   0x17
        .equ    Mode_UND,   0x1B
        .equ    Mode_SYS,   0x1F
#
        .equ    I_BIT, 0x80        /* when I bit is set, IRQ is disabled */
        .equ    F_BIT, 0x40        /* when F bit is set, FIQ is disabled */
#
#
# System Memory definitions
#
#  Internal RAM definitions
        .equ    RAM_Size,      0x0018000      /* 96K */
        .equ    RAM_Base,      0x4000000
 
#*************************************************************************
# Control Startup Code Operation
#*************************************************************************
.equ 	SRAM_SETUP  ,   1     /* Enable setup of SRAM */
.equ	FMI_SETUP   ,   0     /* Enable FMI Setup */   /* already done by bootloader */
.equ	CLOCK_SETUP ,   1 	  /* Enable clock setup */
.equ	ETM_SETUP ,   0 	  /* Enable ETM setup */
 
#*************************************************************************
# Hardware Definitions 
#*************************************************************************
 
# Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses)
.equ  	FMI_BASE      	,     0x54000000      /* FMI Base Address (non-buffered) */
.equ 	FMI_BBSR_OFS  	,     0x00            /* Boot Bank Size Register */
.equ 	FMI_NBBSR_OFS 	,     0x04            /* Non-boot Bank Size Register	   */
.equ 	FMI_BBADR_OFS 	,     0x0C            /* Boot Bank Base Address Register       #!!! Documentation page 30,*/
.equ 	FMI_NBBADR_OFS 	,     0x10            /* Non-boot Bank Base Address Register   #!!! adresseses do not correspond*/
.equ 	FMI_CR_OFS    	,     0x18            /* Control Register */
.equ	FMI_SR_OFS		,	  0x1C            /* Status Register */
			   
 
.equ	FMI_CR_Val      ,     0x00000018
.equ	FMI_BBSR_Val    ,     0x00000004  /* 04 */
.equ	FMI_BBADR_Val   ,     0x00000000  /* 00 */
.equ	FMI_NBBSR_Val   ,     0x00000002  /* 02 */
.equ	FMI_NBBADR_Val  ,     0x00080000  /* 80000 */
.equ	FLASH_CFG_Val   ,     0x00001010
.equ	FMI_SR_Val      ,     0x00000003      /* Clear status errors (register not in STR912 manual! */
	
 
# System Control Unit (SCU) definitions
.equ	SCU_BASE        ,     0x5C002000      /* SCU Base Address (non-buffered)	       */
.equ	SCU_CLKCNTR_OFS ,     0x00            /* Clock Control register Offset		       */
.equ	SCU_PLLCONF_OFS ,     0x04            /* PLL Configuration register Offset		   */
.equ	SCU_SYSTAT_OFS	,	  0x08            /* SCU status register offset                */
.equ	SCU_PCGR0_OFS   ,     0x14            /* Peripheral Clock Gating Register 0 Offset */
.equ	SCU_PCGR1_OFS   ,     0x18            /* Peripheral Clock Gating Register 1 Offset */
.equ	SCU_SCR0_OFS    ,     0x34            /* System Configuration Register 0 Offset	   */
 
 
.equ	SCU_CLKCNTR_Val ,     0x00031004      /* Use PLL, external memory ratio/2 */
.equ	SCU_PLLCONF_Val ,     0x000BC019
.equ	SCU_PCGR0_Val   ,     0x00000FFB	  /* Setup ext mem clock, EMI, SRAM, Prefetch Queue/Branch cache, FMI */
.equ	SCU_PCGR1_Val   ,     0x00FEC801	  /* Setup GPIO8, 9 & 4 										      */
.equ 	SCU_SCR0_Val 	,     0x00000196      /* Disable Prefetch Queue and Branch cache, SRAM = 96kb */
.equ	SCU_SYSSTAT_LOCK ,    0x01      	  /* Check for PLL locked 								  */
.equ	SCU_PRR0_OFS    ,     0x1C            /*; Peripheral Reset Register        0 Offset	*/
.equ	SCU_PRR1_OFS    ,     0x20            /* Peripheral Reset Register        1 Offset */
 
 
.equ  	P_RESET_SETUP   ,	    1
.equ	SCU_PRR0_Val    ,		0x00001B73
.equ 	SCU_PRR1_Val    ,		0x00FEC801
 
# APB Bridge 1 & 2 definitions (Peripherals)
.equ	APB0_BUF_BASE   ,     0x48001802      /* APB Bridge 0 Buffered Base Address		 */
.equ	APB0_NBUF_BASE  ,     0x58000000      /* APB Bridge 0 Non-buffered Base Address	 */
.equ	APB1_BUF_BASE   ,     0x4C000000      /* APB Bridge 1 Buffered Base Address		 */
.equ	APB1_NBUF_BASE  ,     0x5C000000      /* APB Bridge 1 Non-buffered Base Address	 */
 
# ETM Definitions
.equ	IOPORT2_ETM_ENABLE_BASE ,     0x5C00204C
.equ	IOPORT6_ETM_ENABLE_BASE ,     0x5C00205C
 
.equ	IOPORT2_ETM_ENABLE_VAL  ,     0x0000FFFF
.equ	IOPORT6_ETM_ENABLE_VAL  ,     0x0000FFFF
 
#*************************************************************************
# Stack definitions
#*************************************************************************
 
        .equ    UND_Stack_Size,    64*4
        .equ    SVC_Stack_Size,    64*4
        .equ    ABT_Stack_Size,    64*4
        .equ    FIQ_Stack_Size,    64*4
        .equ    IRQ_Stack_Size,    1024*4
        .equ    USR_Stack_Size,    1024*4
        .equ    Top_Stack,     RAM_Base + RAM_Size
 
# NOTE: Startup Code must be linked first at Address at which it expects to run.
 
#*************************************************************************
# STARTUP EXECUTABLE CODE
#*************************************************************************
 
        .text
		.arm
		.extern main
		.global _app_entry
        .global start_up
		
 
        .func   start_up
#start_up:
 
ENTRY:
 
#*************************************************************************
# Exception Vectors
#*************************************************************************
Vectors:
        LDR     PC, Reset_Addr 		/* 0x0000 */        
        LDR     PC, Undef_Addr 		/* 0x0004 */        
        LDR     PC, SWI_Addr 		/* 0x0008 */        
        LDR     PC, PAbt_Addr 		/* 0x000C */        
        LDR     PC, DAbt_Addr 		/* 0x0010 */        
        NOP 						/* 0x0014 Reserved Vector */
		LDR     PC, IRQ_Addr  		/* 0x0018 wraps around address space to 0xFFFFFF030. Vector from VicVECAddr */
        LDR     PC, FIQ_Addr		/* 0x001C FIQ has no VIC vector slot!	*/
 
#*************************************************************************
# Interrupt Vectors
#*************************************************************************
 
Reset_Addr:     .word   Hard_Reset			  /* CPU reset vector and entry point */
Undef_Addr:     .word   _Undef_Handler
SWI_Addr:       .word   _SWI_Handler
PAbt_Addr:      .word   _PAbt_Handler
DAbt_Addr:      .word   _DAbt_Handler
                .word   0                      /* Reserved Address */
IRQ_Addr:       .word   _IRQ_Handler			   /* Does not get used due to "LDR PC, [PC, #-0xFF0]" above */
FIQ_Addr:       .word   _FIQ_Handler			   
 
# Dummy Interrupt Vector Table (real service routines in INTERRUPT.C)
 
	_Undef_Handler:  B       Undefined_Handler
	_SWI_Handler:    B       SWIHandler
	_PAbt_Handler:   B       Prefetch_Handler
	_DAbt_Handler:   B       Abort_Handler
	_IRQ_Handler:	 B		 IRQHandler 		
	_FIQ_Handler:    B       FIQHandler
 
 
 
/*******************************************************************************
                       Exception Handlers
*******************************************************************************/
 
/*******************************************************************************
* Macro Name     : SaveContext
* Description    : This macro used to save the context before entering
                   an exception handler.
* Input          : The range of registers to store.
* Output         : none
*******************************************************************************/
 
.macro	SaveContext reg1 reg2
		STMFD	sp!,{\reg1-\reg2,lr}	/* Save The workspace plus the current return */
										/* address lr_ mode into the stack */
		MRS		r1, spsr				/* Save the spsr_mode into r1 */
		STMFD	sp!, {r1}				/* Save spsr */
.endm
 
/*******************************************************************************
* Macro Name     : RestoreContext
* Description    : This macro used to restore the context to return from
                   an exception handler and continue the program execution.
* Input          : The range of registers to restore.
* Output         : none
*******************************************************************************/
 
.macro	RestoreContext reg1 reg2
		LDMFD	sp!, {r1}				/* Restore the saved spsr_mode into r1 */
		MSR		spsr_cxsf, r1			/* Restore spsr_mode */
		LDMFD	sp!, {\reg1-\reg2,pc}^	/* Return to the instruction following */
										/* the exception interrupt */
.endm
 
/*******************************************************************************
* Function Name  : IRQHandler
* Description    : This function called when IRQ exception is entered.
* Input          : none
* Output         : none
*******************************************************************************/
IRQHandler:
       SUB    lr, lr, #4				/* Update the link register */
       SaveContext r0, r12				/* Save the workspace plus the current */
										/* return address lr_irq and spsr_irq */
		LDR    r0, =VectorAddress
		LDR    r0, [r0]					/* Read the routine address of VIC0 */
		LDR    r1, =VectorAddressDaisy
		LDR    r1, [r1]				    /* Read the routine address of VIC1 */
		/* Padding between the acknowledge and re-enable of interrupts */
		/* For more details, please refer to the following URL */
		/* http://www.arm.com/support/faqip/3682.html */
		NOP
		NOP
#		MSR		cpsr_c, #Mode_SYS		/* Switch to SYS mode and enable IRQ */
#		STMFD	sp!, {lr}				/* Save the link register. */
		LDR		lr, =ReturnAddress		/* Read the return address. */
		CMP		r0, #0					/* Is VIC0 VAR zero? */
		BEQ		SkipVic0
		BX		r0						/* Branch to the IRQ handler. */
SkipVic0:
		CMP		r1, #0					/* Is VIC1 VAR zero? */
		BEQ		ReturnAddress
		BX		r1						/* Branch to the IRQ handler. */
ReturnAddress:
#		LDMFD	sp!, {lr}				/* Restore the link register. */
#		MSR		cpsr_c, #Mode_IRQ|I_BIT	/* Switch to IRQ mode and disable IRQ */
		LDR		r0, =VectorAddress		/* Write to the VectorAddress to clear the */
		STR		r0, [r0]				/* respective interrupt in the internal interrupt */
		LDR		r1, =VectorAddressDaisy	/* Write to the VectorAddressDaisy to clear the */
		STR		r1, [r1]				/* respective interrupt in the internal interrupt */
		RestoreContext r0, r12			/* Restore the context and return to the program execution. */
 
/*******************************************************************************
* Function Name  : SWIHandler
* Description    : This function called when SWI instruction executed.
* Input          : none
* Output         : none
*******************************************************************************/
 
SWIHandler:
		SaveContext r0, r12			/* r0 holds swi number */
		MOV 	r1, sp				/* load regs */
		BL		SWI_Handler
		RestoreContext r0, r12
 
/*******************************************************************************
* Function Name  : UndefinedHandler
* Description    : This function called when undefined instruction
                   exception is entered.
* Input          : none
* Output         : none
*******************************************************************************/
 
UndefinedHandler:
		SaveContext r0, r12
		BL		Undefined_Handler
		RestoreContext r0, r12
 
/*******************************************************************************
* Function Name  : PrefetchAbortHandler
* Description    : This function called when Prefetch Abort
                   exception is entered.
* Input          : none
* Output         : none
*******************************************************************************/
 
PrefetchHandler:
		SUB		lr, lr, #4			/* Update the link register. */
		SaveContext r0, r12
		BL		Prefetch_Handler
		RestoreContext r0, r12
 
/*******************************************************************************
* Function Name  : DataAbortHandler
* Description    : This function is called when Data Abort
                   exception is entered.
* Input          : none
* Output         : none
*******************************************************************************/
 
AbortHandler:
		SUB		lr, lr, #8			/* Update the link register. */
		SaveContext r0, r12
		BL		Abort_Handler
		RestoreContext r0, r12
 
/*******************************************************************************
* Function Name  : FIQHandler
* Description    : This function is called when FIQ
                   exception is entered.
* Input          : none
* Output         : none
*******************************************************************************/
 
FIQHandler:
		SUB		lr, lr, #4			/* Update the link register. */
		SaveContext r0, r7
		BL		FIQ_Handler
		RestoreContext r0, r7
 
	
 
 
#*************************************************************************
# Reset Handler Entry Point
#*************************************************************************
Hard_Reset: 
app_entry:
 		 StartupDelay 500000
Start_init_s:
 
#*************************************************************************
# Setup SRAM Size
 
                .IF      SRAM_SETUP == 1
 
                LDR     R0, =SCU_BASE
                LDR     R1, =SCU_SCR0_Val
                STR     R1, [R0, #SCU_SCR0_OFS]
 #               ORR     R1, R1, #0x00000200
 #               STR     R1, [R0, #SCU_SCR0_OFS]
 
                .ENDIF
 
#*************************************************************************
# Setup Flash Memory Interface (FMI)
 
                .IF      FMI_SETUP == 1
 
                LDR     R0, =FMI_BASE
                LDR     R1, =FMI_BBSR_Val
                STR     R1, [R0, #FMI_BBSR_OFS]
                LDR     R1, =FMI_NBBSR_Val
                STR     R1, [R0, #FMI_NBBSR_OFS]
                LDR     R1, =(FMI_BBADR_Val >> 2)
                STR     R1, [R0, #FMI_BBADR_OFS]
                LDR     R1, =(FMI_NBBADR_Val >> 2)
                STR     R1, [R0, #FMI_NBBADR_OFS]
                LDR     R2, =FMI_CR_Val
                STR     R2, [R0, #FMI_CR_OFS]
 
    			LDR     R2, =FMI_SR_Val
                STR     R2, [R0, #FMI_SR_OFS]
 
	            # Write "Write flash configuration" command (60h)
                MOV     R0, R1, LSL #2
                MOV     R1, #0x60
                STRH    R1, [R0, #0]
 
                # Write "Write flash configuration confirm" command (03h)
                LDR     R2, =(FLASH_CFG_Val >> 2)
                ADD     R0, R0, R2
                MOV     R1, #0x03
                STRH    R1, [R0, #0]
 
                .ENDIF
 
#*************************************************************************
# Setup Clock PLL
 
                .IF      CLOCK_SETUP == 1
 
                LDR     R0, =SCU_BASE
                LDR     R1, =0x00020002
                STR     R1, [R0, #SCU_CLKCNTR_OFS]    /* Select OSC as clock src */
 
                NOP     /* Wait for oscillator stabilisation */
                NOP     /* Must be more than 10 oscillator periods */
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
                NOP
/*
                LDR     R1, =0x0003C019               // Disable PLL 
                STR     R1, [R0, #SCU_PLLCONF_OFS]
                LDR     R1, =SCU_PLLCONF_Val 
                STR     R1, [R0, #SCU_PLLCONF_OFS]    // Set new PLL values 
 
				.IF      (SCU_PLLCONF_Val & 0x8000)	  // See if PLL is being used 
 
                LDR     R1, =SCU_SYSSTAT_LOCK
PLL_LOCK_LOOP:
				LDR		R2,[R0, #SCU_SYSTAT_OFS]      // Wait for PLL lock 
				ANDS	R2, R2, R1
				BEQ		PLL_LOCK_LOOP
 
				.ENDIF
 
                LDR     R1, =SCU_PLLCONF_Val
                STR     R1, [R0, #SCU_PLLCONF_OFS]
                LDR     R1, =SCU_CLKCNTR_Val
                STR     R1, [R0, #SCU_CLKCNTR_OFS]
 
                LDR     R1, =SCU_PCGR0_Val            // Enable clock gating 
                STR     R1, [R0, #SCU_PCGR0_OFS]
                LDR     R1, =SCU_PCGR1_Val
                STR     R1, [R0, #SCU_PCGR1_OFS]
                .ENDIF
  */
  /*; --- wait states Flash confguration */
 
        LDR     R6, = 0x00080000            /*;Write a Write Flash Configuration */
        LDR     R7, =0x60                   /*;Register command (60h) to any word*/
        STRH    R7, [R6]                    /*;address in Bank 1.*/
 
 
        LDR     R6, = 0x00083040            /*;Write a Write Flash Configuration  */
        LDR     R7, = 0x3                   /*;Register Confirm command (03h)*/
        STRH    R7, [R6]                    /*;2Wstaites in read,PWD,LVD enabled, */
                                            /*;High BUSCFG.*/
 
/*; --- PLL configuration      */
    
 
        LDR     R1, = SCU_PLLCONF_Val               /*;Set PLL ENABLE, to 96Mhz */
        STR     R1, [R0, #SCU_PLLCONF_OFS]
        
       
Wait_Loop:      
 
        LDR     R1,[R0, #SCU_SYSTAT_OFS]   /*;Wait until PLL is Locked*/
		  ANDS    R1, R1, #0x01 
		  BEQ     Wait_Loop
        
        
        LDR     R1, = 0x00020080             /*;Set PLL as clock source after pll */
        STR     R1, [R0, #SCU_CLKCNTR_OFS ] /*;is locked and  FMICLK=RCLK,*/
        .ENDIF                                     /*;PCLK=RCLK/2*/
 
# Setup Peripheral Reset
                .IF      P_RESET_SETUP == 1
                LDR     R1, =SCU_PRR0_Val
                STR     R1, [R0, #SCU_PRR0_OFS]
                LDR     R1, =SCU_PRR1_Val
                STR     R1, [R0, #SCU_PRR1_OFS]
                .ENDIF
 
#*************************************************************************
# Embedded Trace Module Setup
#*************************************************************************
 
                .IF     ETM_SETUP == 1
 
# Configure IOPORT2 for ETM operation
                LDR     R0, =IOPORT2_ETM_ENABLE_BASE
                LDR     R1, =IOPORT2_ETM_ENABLE_VAL
                STR     R1, [R0, #0]  
 
# Configure IOPORT6 for ETM operation				
                LDR     R0, =IOPORT6_ETM_ENABLE_BASE
                LDR     R1, =IOPORT6_ETM_ENABLE_VAL
                STR     R1, [R0, #0]  
			  
				.ENDIF
 
 
#*************************************************************************
# Compiler Runtime Environment Setup
#*************************************************************************
# Note: R13 = SP
 
# Setup Stack for each mode
	   			LDR     R0, =Top_Stack
 
# Set up Fast Interrupt Mode and set FIQ Mode Stack
        		MSR     CPSR_c, #Mode_FIQ|I_BIT|F_BIT
    		    mov     r13, r0                     
    		    sub     r0, r0, #FIQ_Stack_Size
 
# Set up Interrupt Mode and set IRQ Mode Stack
    		    msr     CPSR_c, #Mode_IRQ|I_BIT|F_BIT
    			mov     r13, r0                     
     		   	sub     r0, r0, #IRQ_Stack_Size
 
# Set up Abort Mode and set Abort Mode Stack
      			msr     CPSR_c, #Mode_ABT|I_BIT|F_BIT
        		mov     r13, r0                     
        		sub     r0, r0, #ABT_Stack_Size
 
# Set up Undefined Instruction Mode and set Undef Mode Stack
        		msr     CPSR_c, #Mode_UND|I_BIT|F_BIT
        		mov     r13, r0                     
        		sub     r0, r0, #UND_Stack_Size
 
# 	Set up Supervisor Mode and set Supervisor Mode Stack
        		msr     CPSR_c, #Mode_SVC|I_BIT|F_BIT
        		mov     r13, r0                     
        		sub     r0, r0, #SVC_Stack_Size
 
# 	Set up User Mode and set User Mode Stack
        		msr     CPSR_c, #Mode_USR /* #Mode_USR */  /* Leave interrupts enabled in user mode                 */
        		mov     r13, r0             /* Note: interrupts will not happen until VIC is enabled */         
 
#  Setup a default Stack Limit (when compiled with "-mapcs-stack-check")
        		SUB     SL, SP, #1<<10         /* 1kB */
 
# Initialise current CPU status to prevent unwanted interrupts
#				msr		CPSR_c,#0xD3
 
#*************************************************************************
# Initialise RAM For Compiler Variables
#*************************************************************************
 
            	copy_section2 data, _etext, __data_start__, _edata
 
#*************************************************************************
# Clear .bss section
#*************************************************************************
 
                clear_section bss, __bss_start__, __bss_end__
                clear_section bss2, __bss2_start__, __bss2_end__
 
#*************************************************************************
# Enter the C code
#*************************************************************************
# Jump to main()
 
	    B       main
 
 
        .size   _startup, . - _startup
        .endfunc
 
#*************************************************************************
# END
#*************************************************************************	
        .end

Rev 369	Rev 376
1		1
2	.include "startup_generic.s"	2	.include "startup_generic.s"
3		3
4	# reference to external interrupt handlers	4	# reference to external interrupt handlers
5	#	5	#
6	.extern SWI_Handler	6	.extern SWI_Handler
7	.extern Prefetch_Handler	7	.extern Prefetch_Handler
8	.extern Abort_Handler	8	.extern Abort_Handler
9	.extern Undefined_Handler	9	.extern Undefined_Handler
10	.extern FIQ_Handler	10	.extern FIQ_Handler
11		11
12		12
13	.equ VectorAddress, 0xFFFFF030 /* VIC Vector address register address. */	13	.equ VectorAddress, 0xFFFFF030 /* VIC Vector address register address. */
14	.equ VectorAddressDaisy, 0xFC000030 /* Daisy VIC Vector address register */	14	.equ VectorAddressDaisy, 0xFC000030 /* Daisy VIC Vector address register */
15		15
16		16
17	#	17	#
18	# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs	18	# Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
19	#	19	#
20	.equ Mode_USR, 0x10	20	.equ Mode_USR, 0x10
21	.equ Mode_FIQ, 0x11	21	.equ Mode_FIQ, 0x11
22	.equ Mode_IRQ, 0x12	22	.equ Mode_IRQ, 0x12
23	.equ Mode_SVC, 0x13	23	.equ Mode_SVC, 0x13
24	.equ Mode_ABT, 0x17	24	.equ Mode_ABT, 0x17
25	.equ Mode_UND, 0x1B	25	.equ Mode_UND, 0x1B
26	.equ Mode_SYS, 0x1F	26	.equ Mode_SYS, 0x1F
27	#	27	#
28	.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */	28	.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
29	.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */	29	.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
30	#	30	#
31	#	31	#
32	# System Memory definitions	32	# System Memory definitions
33	#	33	#
34	# Internal RAM definitions	34	# Internal RAM definitions
35	.equ RAM_Size, 0x0018000 /* 96K */	35	.equ RAM_Size, 0x0018000 /* 96K */
36	.equ RAM_Base, 0x4000000	36	.equ RAM_Base, 0x4000000
37		37
38	#*************************************************************************	38	#*************************************************************************
39	# Control Startup Code Operation	39	# Control Startup Code Operation
40	#*************************************************************************	40	#*************************************************************************
41	.equ SRAM_SETUP , 1 /* Enable setup of SRAM */	41	.equ SRAM_SETUP , 1 /* Enable setup of SRAM */
42	.equ FMI_SETUP , 0 /* Enable FMI Setup / / already done by bootloader */	42	.equ FMI_SETUP , 0 /* Enable FMI Setup / / already done by bootloader */
43	.equ CLOCK_SETUP , 1 /* Enable clock setup */	43	.equ CLOCK_SETUP , 1 /* Enable clock setup */
44	.equ ETM_SETUP , 0 /* Enable ETM setup */	44	.equ ETM_SETUP , 0 /* Enable ETM setup */
45		45
46	#*************************************************************************	46	#*************************************************************************
47	# Hardware Definitions	47	# Hardware Definitions
48	#*************************************************************************	48	#*************************************************************************
49		49
50	# Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses)	50	# Flash Memory Interface (FMI) definitions (Flash banks sizes and addresses)
51	.equ FMI_BASE , 0x54000000 /* FMI Base Address (non-buffered) */	51	.equ FMI_BASE , 0x54000000 /* FMI Base Address (non-buffered) */
52	.equ FMI_BBSR_OFS , 0x00 /* Boot Bank Size Register */	52	.equ FMI_BBSR_OFS , 0x00 /* Boot Bank Size Register */
53	.equ FMI_NBBSR_OFS , 0x04 /* Non-boot Bank Size Register */	53	.equ FMI_NBBSR_OFS , 0x04 /* Non-boot Bank Size Register */
54	.equ FMI_BBADR_OFS , 0x0C /* Boot Bank Base Address Register #!!! Documentation page 30,*/	54	.equ FMI_BBADR_OFS , 0x0C /* Boot Bank Base Address Register #!!! Documentation page 30,*/
55	.equ FMI_NBBADR_OFS , 0x10 /* Non-boot Bank Base Address Register #!!! adresseses do not correspond*/	55	.equ FMI_NBBADR_OFS , 0x10 /* Non-boot Bank Base Address Register #!!! adresseses do not correspond*/
56	.equ FMI_CR_OFS , 0x18 /* Control Register */	56	.equ FMI_CR_OFS , 0x18 /* Control Register */
57	.equ FMI_SR_OFS , 0x1C /* Status Register */	57	.equ FMI_SR_OFS , 0x1C /* Status Register */
58		58
59		59
60	.equ FMI_CR_Val , 0x00000018	60	.equ FMI_CR_Val , 0x00000018
61	.equ FMI_BBSR_Val , 0x00000004 /* 04 */	61	.equ FMI_BBSR_Val , 0x00000004 /* 04 */
62	.equ FMI_BBADR_Val , 0x00000000 /* 00 */	62	.equ FMI_BBADR_Val , 0x00000000 /* 00 */
63	.equ FMI_NBBSR_Val , 0x00000002 /* 02 */	63	.equ FMI_NBBSR_Val , 0x00000002 /* 02 */
64	.equ FMI_NBBADR_Val , 0x00080000 /* 80000 */	64	.equ FMI_NBBADR_Val , 0x00080000 /* 80000 */
65	.equ FLASH_CFG_Val , 0x00001010	65	.equ FLASH_CFG_Val , 0x00001010
66	.equ FMI_SR_Val , 0x00000003 /* Clear status errors (register not in STR912 manual! */	66	.equ FMI_SR_Val , 0x00000003 /* Clear status errors (register not in STR912 manual! */
67		67
68		68
69	# System Control Unit (SCU) definitions	69	# System Control Unit (SCU) definitions
70	.equ SCU_BASE , 0x5C002000 /* SCU Base Address (non-buffered) */	70	.equ SCU_BASE , 0x5C002000 /* SCU Base Address (non-buffered) */
71	.equ SCU_CLKCNTR_OFS , 0x00 /* Clock Control register Offset */	71	.equ SCU_CLKCNTR_OFS , 0x00 /* Clock Control register Offset */
72	.equ SCU_PLLCONF_OFS , 0x04 /* PLL Configuration register Offset */	72	.equ SCU_PLLCONF_OFS , 0x04 /* PLL Configuration register Offset */
73	.equ SCU_SYSTAT_OFS , 0x08 /* SCU status register offset */	73	.equ SCU_SYSTAT_OFS , 0x08 /* SCU status register offset */
74	.equ SCU_PCGR0_OFS , 0x14 /* Peripheral Clock Gating Register 0 Offset */	74	.equ SCU_PCGR0_OFS , 0x14 /* Peripheral Clock Gating Register 0 Offset */
75	.equ SCU_PCGR1_OFS , 0x18 /* Peripheral Clock Gating Register 1 Offset */	75	.equ SCU_PCGR1_OFS , 0x18 /* Peripheral Clock Gating Register 1 Offset */
76	.equ SCU_SCR0_OFS , 0x34 /* System Configuration Register 0 Offset */	76	.equ SCU_SCR0_OFS , 0x34 /* System Configuration Register 0 Offset */
77		77
78		78
79	.equ SCU_CLKCNTR_Val , 0x00031004 /* Use PLL, external memory ratio/2 */	79	.equ SCU_CLKCNTR_Val , 0x00031004 /* Use PLL, external memory ratio/2 */
80	.equ SCU_PLLCONF_Val , 0x000BC019	80	.equ SCU_PLLCONF_Val , 0x000BC019
81	.equ SCU_PCGR0_Val , 0x00000FFB /* Setup ext mem clock, EMI, SRAM, Prefetch Queue/Branch cache, FMI */	81	.equ SCU_PCGR0_Val , 0x00000FFB /* Setup ext mem clock, EMI, SRAM, Prefetch Queue/Branch cache, FMI */
82	.equ SCU_PCGR1_Val , 0x00FEC801 /* Setup GPIO8, 9 & 4 */	82	.equ SCU_PCGR1_Val , 0x00FEC801 /* Setup GPIO8, 9 & 4 */
83	.equ SCU_SCR0_Val , 0x00000196 /* Disable Prefetch Queue and Branch cache, SRAM = 96kb */	83	.equ SCU_SCR0_Val , 0x00000196 /* Disable Prefetch Queue and Branch cache, SRAM = 96kb */
84	.equ SCU_SYSSTAT_LOCK , 0x01 /* Check for PLL locked */	84	.equ SCU_SYSSTAT_LOCK , 0x01 /* Check for PLL locked */
85	.equ SCU_PRR0_OFS , 0x1C /; Peripheral Reset Register 0 Offset /	85	.equ SCU_PRR0_OFS , 0x1C /; Peripheral Reset Register 0 Offset /
86	.equ SCU_PRR1_OFS , 0x20 /* Peripheral Reset Register 1 Offset */	86	.equ SCU_PRR1_OFS , 0x20 /* Peripheral Reset Register 1 Offset */
87		87
88		88
89	.equ P_RESET_SETUP , 1	89	.equ P_RESET_SETUP , 1
90	.equ SCU_PRR0_Val , 0x00001B73	90	.equ SCU_PRR0_Val , 0x00001B73
91	.equ SCU_PRR1_Val , 0x00FEC801	91	.equ SCU_PRR1_Val , 0x00FEC801
92		92
93	# APB Bridge 1 & 2 definitions (Peripherals)	93	# APB Bridge 1 & 2 definitions (Peripherals)
94	.equ APB0_BUF_BASE , 0x48001802 /* APB Bridge 0 Buffered Base Address */	94	.equ APB0_BUF_BASE , 0x48001802 /* APB Bridge 0 Buffered Base Address */
95	.equ APB0_NBUF_BASE , 0x58000000 /* APB Bridge 0 Non-buffered Base Address */	95	.equ APB0_NBUF_BASE , 0x58000000 /* APB Bridge 0 Non-buffered Base Address */
96	.equ APB1_BUF_BASE , 0x4C000000 /* APB Bridge 1 Buffered Base Address */	96	.equ APB1_BUF_BASE , 0x4C000000 /* APB Bridge 1 Buffered Base Address */
97	.equ APB1_NBUF_BASE , 0x5C000000 /* APB Bridge 1 Non-buffered Base Address */	97	.equ APB1_NBUF_BASE , 0x5C000000 /* APB Bridge 1 Non-buffered Base Address */
98		98
99	# ETM Definitions	99	# ETM Definitions
100	.equ IOPORT2_ETM_ENABLE_BASE , 0x5C00204C	100	.equ IOPORT2_ETM_ENABLE_BASE , 0x5C00204C
101	.equ IOPORT6_ETM_ENABLE_BASE , 0x5C00205C	101	.equ IOPORT6_ETM_ENABLE_BASE , 0x5C00205C
102		102
103	.equ IOPORT2_ETM_ENABLE_VAL , 0x0000FFFF	103	.equ IOPORT2_ETM_ENABLE_VAL , 0x0000FFFF
104	.equ IOPORT6_ETM_ENABLE_VAL , 0x0000FFFF	104	.equ IOPORT6_ETM_ENABLE_VAL , 0x0000FFFF
105		105
106	#*************************************************************************	106	#*************************************************************************
107	# Stack definitions	107	# Stack definitions
108	#*************************************************************************	108	#*************************************************************************
109		109
110	.equ UND_Stack_Size, 64*4	110	.equ UND_Stack_Size, 64*4
111	.equ SVC_Stack_Size, 64*4	111	.equ SVC_Stack_Size, 64*4
112	.equ ABT_Stack_Size, 64*4	112	.equ ABT_Stack_Size, 64*4
113	.equ FIQ_Stack_Size, 64*4	113	.equ FIQ_Stack_Size, 64*4
114	.equ IRQ_Stack_Size, 1024*4	114	.equ IRQ_Stack_Size, 1024*4
115	.equ USR_Stack_Size, 1024*4	115	.equ USR_Stack_Size, 1024*4
116	.equ Top_Stack, RAM_Base + RAM_Size	116	.equ Top_Stack, RAM_Base + RAM_Size
117		117
118	# NOTE: Startup Code must be linked first at Address at which it expects to run.	118	# NOTE: Startup Code must be linked first at Address at which it expects to run.
119		119
120	#*************************************************************************	120	#*************************************************************************
121	# STARTUP EXECUTABLE CODE	121	# STARTUP EXECUTABLE CODE
122	#*************************************************************************	122	#*************************************************************************
123		123
124	.text	124	.text
125	.arm	125	.arm
126	.extern main	126	.extern main
127	.global _app_entry	127	.global _app_entry
128	.global start_up	128	.global start_up
129		129
130		130
131	.func start_up	131	.func start_up
132	#start_up:	132	#start_up:
133		133
134	ENTRY:	134	ENTRY:
135		135
136	#*************************************************************************	136	#*************************************************************************
137	# Exception Vectors	137	# Exception Vectors
138	#*************************************************************************	138	#*************************************************************************
139	Vectors:	139	Vectors:
140	LDR PC, Reset_Addr /* 0x0000 */	140	LDR PC, Reset_Addr /* 0x0000 */
141	LDR PC, Undef_Addr /* 0x0004 */	141	LDR PC, Undef_Addr /* 0x0004 */
142	LDR PC, SWI_Addr /* 0x0008 */	142	LDR PC, SWI_Addr /* 0x0008 */
143	LDR PC, PAbt_Addr /* 0x000C */	143	LDR PC, PAbt_Addr /* 0x000C */
144	LDR PC, DAbt_Addr /* 0x0010 */	144	LDR PC, DAbt_Addr /* 0x0010 */
145	NOP /* 0x0014 Reserved Vector */	145	NOP /* 0x0014 Reserved Vector */
146	LDR PC, IRQ_Addr /* 0x0018 wraps around address space to 0xFFFFFF030. Vector from VicVECAddr */	146	LDR PC, IRQ_Addr /* 0x0018 wraps around address space to 0xFFFFFF030. Vector from VicVECAddr */
147	LDR PC, FIQ_Addr /* 0x001C FIQ has no VIC vector slot! */	147	LDR PC, FIQ_Addr /* 0x001C FIQ has no VIC vector slot! */
148		148
149	#*************************************************************************	149	#*************************************************************************
150	# Interrupt Vectors	150	# Interrupt Vectors
151	#*************************************************************************	151	#*************************************************************************
152		152
153	Reset_Addr: .word Hard_Reset /* CPU reset vector and entry point */	153	Reset_Addr: .word Hard_Reset /* CPU reset vector and entry point */
154	Undef_Addr: .word _Undef_Handler	154	Undef_Addr: .word _Undef_Handler
155	SWI_Addr: .word _SWI_Handler	155	SWI_Addr: .word _SWI_Handler
156	PAbt_Addr: .word _PAbt_Handler	156	PAbt_Addr: .word _PAbt_Handler
157	DAbt_Addr: .word _DAbt_Handler	157	DAbt_Addr: .word _DAbt_Handler
158	.word 0 /* Reserved Address */	158	.word 0 /* Reserved Address */
159	IRQ_Addr: .word _IRQ_Handler /* Does not get used due to "LDR PC, [PC, #-0xFF0]" above */	159	IRQ_Addr: .word _IRQ_Handler /* Does not get used due to "LDR PC, [PC, #-0xFF0]" above */
160	FIQ_Addr: .word _FIQ_Handler	160	FIQ_Addr: .word _FIQ_Handler
161		161
162	# Dummy Interrupt Vector Table (real service routines in INTERRUPT.C)	162	# Dummy Interrupt Vector Table (real service routines in INTERRUPT.C)
163		163
164	_Undef_Handler: B UndefinedHandler	164	_Undef_Handler: B Undefined_Handler
165	_SWI_Handler: B SWIHandler	165	_SWI_Handler: B SWIHandler
166	_PAbt_Handler: B PrefetchHandler	166	_PAbt_Handler: B Prefetch_Handler
167	_DAbt_Handler: B AbortHandler	167	_DAbt_Handler: B Abort_Handler
168	_IRQ_Handler: B IRQHandler	168	_IRQ_Handler: B IRQHandler
169	_FIQ_Handler: B FIQHandler	169	_FIQ_Handler: B FIQHandler
170		170
171		171
172		172
173	/*******************************************************************************	173	/*******************************************************************************
174	Exception Handlers	174	Exception Handlers
175	*******************************************************************************/	175	*******************************************************************************/
176		176
177	/*******************************************************************************	177	/*******************************************************************************
178	* Macro Name : SaveContext	178	* Macro Name : SaveContext
179	* Description : This macro used to save the context before entering	179	* Description : This macro used to save the context before entering
180	an exception handler.	180	an exception handler.
181	* Input : The range of registers to store.	181	* Input : The range of registers to store.
182	* Output : none	182	* Output : none
183	*******************************************************************************/	183	*******************************************************************************/
184		184
185	.macro SaveContext reg1 reg2	185	.macro SaveContext reg1 reg2
186	STMFD sp!,{\reg1-\reg2,lr} /* Save The workspace plus the current return */	186	STMFD sp!,{\reg1-\reg2,lr} /* Save The workspace plus the current return */
187	/* address lr_ mode into the stack */	187	/* address lr_ mode into the stack */
188	MRS r1, spsr /* Save the spsr_mode into r1 */	188	MRS r1, spsr /* Save the spsr_mode into r1 */
189	STMFD sp!, {r1} /* Save spsr */	189	STMFD sp!, {r1} /* Save spsr */
190	.endm	190	.endm
191		191
192	/*******************************************************************************	192	/*******************************************************************************
193	* Macro Name : RestoreContext	193	* Macro Name : RestoreContext
194	* Description : This macro used to restore the context to return from	194	* Description : This macro used to restore the context to return from
195	an exception handler and continue the program execution.	195	an exception handler and continue the program execution.
196	* Input : The range of registers to restore.	196	* Input : The range of registers to restore.
197	* Output : none	197	* Output : none
198	*******************************************************************************/	198	*******************************************************************************/
199		199
200	.macro RestoreContext reg1 reg2	200	.macro RestoreContext reg1 reg2
201	LDMFD sp!, {r1} /* Restore the saved spsr_mode into r1 */	201	LDMFD sp!, {r1} /* Restore the saved spsr_mode into r1 */
202	MSR spsr_cxsf, r1 /* Restore spsr_mode */	202	MSR spsr_cxsf, r1 /* Restore spsr_mode */
203	LDMFD sp!, {\reg1-\reg2,pc}^ /* Return to the instruction following */	203	LDMFD sp!, {\reg1-\reg2,pc}^ /* Return to the instruction following */
204	/* the exception interrupt */	204	/* the exception interrupt */
205	.endm	205	.endm
206		206
207	/*******************************************************************************	207	/*******************************************************************************
208	* Function Name : IRQHandler	208	* Function Name : IRQHandler
209	* Description : This function called when IRQ exception is entered.	209	* Description : This function called when IRQ exception is entered.
210	* Input : none	210	* Input : none
211	* Output : none	211	* Output : none
212	*******************************************************************************/	212	*******************************************************************************/
213	IRQHandler:	213	IRQHandler:
214	SUB lr, lr, #4 /* Update the link register */	214	SUB lr, lr, #4 /* Update the link register */
215	SaveContext r0, r12 /* Save the workspace plus the current */	215	SaveContext r0, r12 /* Save the workspace plus the current */
216	/* return address lr_irq and spsr_irq */	216	/* return address lr_irq and spsr_irq */
217	LDR r0, =VectorAddress	217	LDR r0, =VectorAddress
218	LDR r0, [r0] /* Read the routine address of VIC0 */	218	LDR r0, [r0] /* Read the routine address of VIC0 */
219	LDR r1, =VectorAddressDaisy	219	LDR r1, =VectorAddressDaisy
220	LDR r1, [r1] /* Read the routine address of VIC1 */	220	LDR r1, [r1] /* Read the routine address of VIC1 */
221	/* Padding between the acknowledge and re-enable of interrupts */	221	/* Padding between the acknowledge and re-enable of interrupts */
222	/* For more details, please refer to the following URL */	222	/* For more details, please refer to the following URL */
223	/* http://www.arm.com/support/faqip/3682.html */	223	/* http://www.arm.com/support/faqip/3682.html */
224	NOP	224	NOP
225	NOP	225	NOP
226	# MSR cpsr_c, #Mode_SYS /* Switch to SYS mode and enable IRQ */	226	# MSR cpsr_c, #Mode_SYS /* Switch to SYS mode and enable IRQ */
227	# STMFD sp!, {lr} /* Save the link register. */	227	# STMFD sp!, {lr} /* Save the link register. */
228	LDR lr, =ReturnAddress /* Read the return address. */	228	LDR lr, =ReturnAddress /* Read the return address. */
229	CMP r0, #0 /* Is VIC0 VAR zero? */	229	CMP r0, #0 /* Is VIC0 VAR zero? */
230	BEQ SkipVic0	230	BEQ SkipVic0
231	BX r0 /* Branch to the IRQ handler. */	231	BX r0 /* Branch to the IRQ handler. */
232	SkipVic0:	232	SkipVic0:
233	CMP r1, #0 /* Is VIC1 VAR zero? */	233	CMP r1, #0 /* Is VIC1 VAR zero? */
234	BEQ ReturnAddress	234	BEQ ReturnAddress
235	BX r1 /* Branch to the IRQ handler. */	235	BX r1 /* Branch to the IRQ handler. */
236	ReturnAddress:	236	ReturnAddress:
237	# LDMFD sp!, {lr} /* Restore the link register. */	237	# LDMFD sp!, {lr} /* Restore the link register. */
238	# MSR cpsr_c, #Mode_IRQ\|I_BIT /* Switch to IRQ mode and disable IRQ */	238	# MSR cpsr_c, #Mode_IRQ\|I_BIT /* Switch to IRQ mode and disable IRQ */
239	LDR r0, =VectorAddress /* Write to the VectorAddress to clear the */	239	LDR r0, =VectorAddress /* Write to the VectorAddress to clear the */
240	STR r0, [r0] /* respective interrupt in the internal interrupt */	240	STR r0, [r0] /* respective interrupt in the internal interrupt */
241	LDR r1, =VectorAddressDaisy /* Write to the VectorAddressDaisy to clear the */	241	LDR r1, =VectorAddressDaisy /* Write to the VectorAddressDaisy to clear the */
242	STR r1, [r1] /* respective interrupt in the internal interrupt */	242	STR r1, [r1] /* respective interrupt in the internal interrupt */
243	RestoreContext r0, r12 /* Restore the context and return to the program execution. */	243	RestoreContext r0, r12 /* Restore the context and return to the program execution. */
244		244
245	/*******************************************************************************	245	/*******************************************************************************
246	* Function Name : SWIHandler	246	* Function Name : SWIHandler
247	* Description : This function called when SWI instruction executed.	247	* Description : This function called when SWI instruction executed.
248	* Input : none	248	* Input : none
249	* Output : none	249	* Output : none
250	*******************************************************************************/	250	*******************************************************************************/
251		251
252	SWIHandler:	252	SWIHandler:
253	SaveContext r0, r12 /* r0 holds swi number */	253	SaveContext r0, r12 /* r0 holds swi number */
254	MOV r1, sp /* load regs */	254	MOV r1, sp /* load regs */
255	BL SWI_Handler	255	BL SWI_Handler
256	RestoreContext r0, r12	256	RestoreContext r0, r12
257		257
258	/*******************************************************************************	258	/*******************************************************************************
259	* Function Name : UndefinedHandler	259	* Function Name : UndefinedHandler
260	* Description : This function called when undefined instruction	260	* Description : This function called when undefined instruction
261	exception is entered.	261	exception is entered.
262	* Input : none	262	* Input : none
263	* Output : none	263	* Output : none
264	*******************************************************************************/	264	*******************************************************************************/
265		265
266	UndefinedHandler:	266	UndefinedHandler:
267	SaveContext r0, r12	267	SaveContext r0, r12
268	BL Undefined_Handler	268	BL Undefined_Handler
269	RestoreContext r0, r12	269	RestoreContext r0, r12
270		270
271	/*******************************************************************************	271	/*******************************************************************************
272	* Function Name : PrefetchAbortHandler	272	* Function Name : PrefetchAbortHandler
273	* Description : This function called when Prefetch Abort	273	* Description : This function called when Prefetch Abort
274	exception is entered.	274	exception is entered.
275	* Input : none	275	* Input : none
276	* Output : none	276	* Output : none
277	*******************************************************************************/	277	*******************************************************************************/
278		278
279	PrefetchHandler:	279	PrefetchHandler:
280	SUB lr, lr, #4 /* Update the link register. */	280	SUB lr, lr, #4 /* Update the link register. */
281	SaveContext r0, r12	281	SaveContext r0, r12
282	BL Prefetch_Handler	282	BL Prefetch_Handler
283	RestoreContext r0, r12	283	RestoreContext r0, r12
284		284
285	/*******************************************************************************	285	/*******************************************************************************
286	* Function Name : DataAbortHandler	286	* Function Name : DataAbortHandler
287	* Description : This function is called when Data Abort	287	* Description : This function is called when Data Abort
288	exception is entered.	288	exception is entered.
289	* Input : none	289	* Input : none
290	* Output : none	290	* Output : none
291	*******************************************************************************/	291	*******************************************************************************/
292		292
293	AbortHandler:	293	AbortHandler:
294	SUB lr, lr, #8 /* Update the link register. */	294	SUB lr, lr, #8 /* Update the link register. */
295	SaveContext r0, r12	295	SaveContext r0, r12
296	BL Abort_Handler	296	BL Abort_Handler
297	RestoreContext r0, r12	297	RestoreContext r0, r12
298		298
299	/*******************************************************************************	299	/*******************************************************************************
300	* Function Name : FIQHandler	300	* Function Name : FIQHandler
301	* Description : This function is called when FIQ	301	* Description : This function is called when FIQ
302	exception is entered.	302	exception is entered.
303	* Input : none	303	* Input : none
304	* Output : none	304	* Output : none
305	*******************************************************************************/	305	*******************************************************************************/
306		306
307	FIQHandler:	307	FIQHandler:
308	SUB lr, lr, #4 /* Update the link register. */	308	SUB lr, lr, #4 /* Update the link register. */
309	SaveContext r0, r7	309	SaveContext r0, r7
310	BL FIQ_Handler	310	BL FIQ_Handler
311	RestoreContext r0, r7	311	RestoreContext r0, r7
312		312
313		313
314		314
315		315
316	#*************************************************************************	316	#*************************************************************************
317	# Reset Handler Entry Point	317	# Reset Handler Entry Point
318	#*************************************************************************	318	#*************************************************************************
319	Hard_Reset:	319	Hard_Reset:
320	app_entry:	320	app_entry:
321	StartupDelay 500000	321	StartupDelay 500000
322	Start_init_s:	322	Start_init_s:
323		323
324	#*************************************************************************	324	#*************************************************************************
325	# Setup SRAM Size	325	# Setup SRAM Size
326		326
327	.IF SRAM_SETUP == 1	327	.IF SRAM_SETUP == 1
328		328
329	LDR R0, =SCU_BASE	329	LDR R0, =SCU_BASE
330	LDR R1, =SCU_SCR0_Val	330	LDR R1, =SCU_SCR0_Val
331	STR R1, [R0, #SCU_SCR0_OFS]	331	STR R1, [R0, #SCU_SCR0_OFS]
332	# ORR R1, R1, #0x00000200	332	# ORR R1, R1, #0x00000200
333	# STR R1, [R0, #SCU_SCR0_OFS]	333	# STR R1, [R0, #SCU_SCR0_OFS]
334		334
335	.ENDIF	335	.ENDIF
336		336
337	#*************************************************************************	337	#*************************************************************************
338	# Setup Flash Memory Interface (FMI)	338	# Setup Flash Memory Interface (FMI)
339		339
340	.IF FMI_SETUP == 1	340	.IF FMI_SETUP == 1
341		341
342	LDR R0, =FMI_BASE	342	LDR R0, =FMI_BASE
343	LDR R1, =FMI_BBSR_Val	343	LDR R1, =FMI_BBSR_Val
344	STR R1, [R0, #FMI_BBSR_OFS]	344	STR R1, [R0, #FMI_BBSR_OFS]
345	LDR R1, =FMI_NBBSR_Val	345	LDR R1, =FMI_NBBSR_Val
346	STR R1, [R0, #FMI_NBBSR_OFS]	346	STR R1, [R0, #FMI_NBBSR_OFS]
347	LDR R1, =(FMI_BBADR_Val >> 2)	347	LDR R1, =(FMI_BBADR_Val >> 2)
348	STR R1, [R0, #FMI_BBADR_OFS]	348	STR R1, [R0, #FMI_BBADR_OFS]
349	LDR R1, =(FMI_NBBADR_Val >> 2)	349	LDR R1, =(FMI_NBBADR_Val >> 2)
350	STR R1, [R0, #FMI_NBBADR_OFS]	350	STR R1, [R0, #FMI_NBBADR_OFS]
351	LDR R2, =FMI_CR_Val	351	LDR R2, =FMI_CR_Val
352	STR R2, [R0, #FMI_CR_OFS]	352	STR R2, [R0, #FMI_CR_OFS]
353		353
354	LDR R2, =FMI_SR_Val	354	LDR R2, =FMI_SR_Val
355	STR R2, [R0, #FMI_SR_OFS]	355	STR R2, [R0, #FMI_SR_OFS]
356		356
357	# Write "Write flash configuration" command (60h)	357	# Write "Write flash configuration" command (60h)
358	MOV R0, R1, LSL #2	358	MOV R0, R1, LSL #2
359	MOV R1, #0x60	359	MOV R1, #0x60
360	STRH R1, [R0, #0]	360	STRH R1, [R0, #0]
361		361
362	# Write "Write flash configuration confirm" command (03h)	362	# Write "Write flash configuration confirm" command (03h)
363	LDR R2, =(FLASH_CFG_Val >> 2)	363	LDR R2, =(FLASH_CFG_Val >> 2)
364	ADD R0, R0, R2	364	ADD R0, R0, R2
365	MOV R1, #0x03	365	MOV R1, #0x03
366	STRH R1, [R0, #0]	366	STRH R1, [R0, #0]
367		367
368	.ENDIF	368	.ENDIF
369		369
370	#*************************************************************************	370	#*************************************************************************
371	# Setup Clock PLL	371	# Setup Clock PLL
372		372
373	.IF CLOCK_SETUP == 1	373	.IF CLOCK_SETUP == 1
374		374
375	LDR R0, =SCU_BASE	375	LDR R0, =SCU_BASE
376	LDR R1, =0x00020002	376	LDR R1, =0x00020002
377	STR R1, [R0, #SCU_CLKCNTR_OFS] /* Select OSC as clock src */	377	STR R1, [R0, #SCU_CLKCNTR_OFS] /* Select OSC as clock src */
378		378
379	NOP /* Wait for oscillator stabilisation */	379	NOP /* Wait for oscillator stabilisation */
380	NOP /* Must be more than 10 oscillator periods */	380	NOP /* Must be more than 10 oscillator periods */
381	NOP	381	NOP
382	NOP	382	NOP
383	NOP	383	NOP
384	NOP	384	NOP
385	NOP	385	NOP
386	NOP	386	NOP
387	NOP	387	NOP
388	NOP	388	NOP
389	NOP	389	NOP
390	NOP	390	NOP
391	NOP	391	NOP
392	NOP	392	NOP
393	NOP	393	NOP
394	NOP	394	NOP
395	/*	395	/*
396	LDR R1, =0x0003C019 // Disable PLL	396	LDR R1, =0x0003C019 // Disable PLL
397	STR R1, [R0, #SCU_PLLCONF_OFS]	397	STR R1, [R0, #SCU_PLLCONF_OFS]
398	LDR R1, =SCU_PLLCONF_Val	398	LDR R1, =SCU_PLLCONF_Val
399	STR R1, [R0, #SCU_PLLCONF_OFS] // Set new PLL values	399	STR R1, [R0, #SCU_PLLCONF_OFS] // Set new PLL values
400		400
401	.IF (SCU_PLLCONF_Val & 0x8000) // See if PLL is being used	401	.IF (SCU_PLLCONF_Val & 0x8000) // See if PLL is being used
402		402
403	LDR R1, =SCU_SYSSTAT_LOCK	403	LDR R1, =SCU_SYSSTAT_LOCK
404	PLL_LOCK_LOOP:	404	PLL_LOCK_LOOP:
405	LDR R2,[R0, #SCU_SYSTAT_OFS] // Wait for PLL lock	405	LDR R2,[R0, #SCU_SYSTAT_OFS] // Wait for PLL lock
406	ANDS R2, R2, R1	406	ANDS R2, R2, R1
407	BEQ PLL_LOCK_LOOP	407	BEQ PLL_LOCK_LOOP
408		408
409	.ENDIF	409	.ENDIF
410		410
411	LDR R1, =SCU_PLLCONF_Val	411	LDR R1, =SCU_PLLCONF_Val
412	STR R1, [R0, #SCU_PLLCONF_OFS]	412	STR R1, [R0, #SCU_PLLCONF_OFS]
413	LDR R1, =SCU_CLKCNTR_Val	413	LDR R1, =SCU_CLKCNTR_Val
414	STR R1, [R0, #SCU_CLKCNTR_OFS]	414	STR R1, [R0, #SCU_CLKCNTR_OFS]
415		415
416	LDR R1, =SCU_PCGR0_Val // Enable clock gating	416	LDR R1, =SCU_PCGR0_Val // Enable clock gating
417	STR R1, [R0, #SCU_PCGR0_OFS]	417	STR R1, [R0, #SCU_PCGR0_OFS]
418	LDR R1, =SCU_PCGR1_Val	418	LDR R1, =SCU_PCGR1_Val
419	STR R1, [R0, #SCU_PCGR1_OFS]	419	STR R1, [R0, #SCU_PCGR1_OFS]
420	.ENDIF	420	.ENDIF
421	*/	421	*/
422	/; --- wait states Flash confguration /	422	/; --- wait states Flash confguration /
423		423
424	LDR R6, = 0x00080000 /;Write a Write Flash Configuration /	424	LDR R6, = 0x00080000 /;Write a Write Flash Configuration /
425	LDR R7, =0x60 /;Register command (60h) to any word/	425	LDR R7, =0x60 /;Register command (60h) to any word/
426	STRH R7, [R6] /;address in Bank 1./	426	STRH R7, [R6] /;address in Bank 1./
427		427
428		428
429	LDR R6, = 0x00083040 /;Write a Write Flash Configuration /	429	LDR R6, = 0x00083040 /;Write a Write Flash Configuration /
430	LDR R7, = 0x3 /;Register Confirm command (03h)/	430	LDR R7, = 0x3 /;Register Confirm command (03h)/
431	STRH R7, [R6] /;2Wstaites in read,PWD,LVD enabled, /	431	STRH R7, [R6] /;2Wstaites in read,PWD,LVD enabled, /
432	/;High BUSCFG./	432	/;High BUSCFG./
433		433
434	/; --- PLL configuration /	434	/; --- PLL configuration /
435		435
436		436
437	LDR R1, = SCU_PLLCONF_Val /;Set PLL ENABLE, to 96Mhz /	437	LDR R1, = SCU_PLLCONF_Val /;Set PLL ENABLE, to 96Mhz /
438	STR R1, [R0, #SCU_PLLCONF_OFS]	438	STR R1, [R0, #SCU_PLLCONF_OFS]
439		439
440		440
441	Wait_Loop:	441	Wait_Loop:
442		442
443	LDR R1,[R0, #SCU_SYSTAT_OFS] /;Wait until PLL is Locked/	443	LDR R1,[R0, #SCU_SYSTAT_OFS] /;Wait until PLL is Locked/
444	ANDS R1, R1, #0x01	444	ANDS R1, R1, #0x01
445	BEQ Wait_Loop	445	BEQ Wait_Loop
446		446
447		447
448	LDR R1, = 0x00020080 /;Set PLL as clock source after pll /	448	LDR R1, = 0x00020080 /;Set PLL as clock source after pll /
449	STR R1, [R0, #SCU_CLKCNTR_OFS ] /;is locked and FMICLK=RCLK,/	449	STR R1, [R0, #SCU_CLKCNTR_OFS ] /;is locked and FMICLK=RCLK,/
450	.ENDIF /;PCLK=RCLK/2/	450	.ENDIF /;PCLK=RCLK/2/
451		451
452	# Setup Peripheral Reset	452	# Setup Peripheral Reset
453	.IF P_RESET_SETUP == 1	453	.IF P_RESET_SETUP == 1
454	LDR R1, =SCU_PRR0_Val	454	LDR R1, =SCU_PRR0_Val
455	STR R1, [R0, #SCU_PRR0_OFS]	455	STR R1, [R0, #SCU_PRR0_OFS]
456	LDR R1, =SCU_PRR1_Val	456	LDR R1, =SCU_PRR1_Val
457	STR R1, [R0, #SCU_PRR1_OFS]	457	STR R1, [R0, #SCU_PRR1_OFS]
458	.ENDIF	458	.ENDIF
459		459
460	#*************************************************************************	460	#*************************************************************************
461	# Embedded Trace Module Setup	461	# Embedded Trace Module Setup
462	#*************************************************************************	462	#*************************************************************************
463		463
464	.IF ETM_SETUP == 1	464	.IF ETM_SETUP == 1
465		465
466	# Configure IOPORT2 for ETM operation	466	# Configure IOPORT2 for ETM operation
467	LDR R0, =IOPORT2_ETM_ENABLE_BASE	467	LDR R0, =IOPORT2_ETM_ENABLE_BASE
468	LDR R1, =IOPORT2_ETM_ENABLE_VAL	468	LDR R1, =IOPORT2_ETM_ENABLE_VAL
469	STR R1, [R0, #0]	469	STR R1, [R0, #0]
470		470
471	# Configure IOPORT6 for ETM operation	471	# Configure IOPORT6 for ETM operation
472	LDR R0, =IOPORT6_ETM_ENABLE_BASE	472	LDR R0, =IOPORT6_ETM_ENABLE_BASE
473	LDR R1, =IOPORT6_ETM_ENABLE_VAL	473	LDR R1, =IOPORT6_ETM_ENABLE_VAL
474	STR R1, [R0, #0]	474	STR R1, [R0, #0]
475		475
476	.ENDIF	476	.ENDIF
477		477
478		478
479	#*************************************************************************	479	#*************************************************************************
480	# Compiler Runtime Environment Setup	480	# Compiler Runtime Environment Setup
481	#*************************************************************************	481	#*************************************************************************
482	# Note: R13 = SP	482	# Note: R13 = SP
483		483
484	# Setup Stack for each mode	484	# Setup Stack for each mode
485	LDR R0, =Top_Stack	485	LDR R0, =Top_Stack
486		486
487	# Set up Fast Interrupt Mode and set FIQ Mode Stack	487	# Set up Fast Interrupt Mode and set FIQ Mode Stack
488	MSR CPSR_c, #Mode_FIQ\|I_BIT\|F_BIT	488	MSR CPSR_c, #Mode_FIQ\|I_BIT\|F_BIT
489	mov r13, r0	489	mov r13, r0
490	sub r0, r0, #FIQ_Stack_Size	490	sub r0, r0, #FIQ_Stack_Size
491		491
492	# Set up Interrupt Mode and set IRQ Mode Stack	492	# Set up Interrupt Mode and set IRQ Mode Stack
493	msr CPSR_c, #Mode_IRQ\|I_BIT\|F_BIT	493	msr CPSR_c, #Mode_IRQ\|I_BIT\|F_BIT
494	mov r13, r0	494	mov r13, r0
495	sub r0, r0, #IRQ_Stack_Size	495	sub r0, r0, #IRQ_Stack_Size
496		496
497	# Set up Abort Mode and set Abort Mode Stack	497	# Set up Abort Mode and set Abort Mode Stack
498	msr CPSR_c, #Mode_ABT\|I_BIT\|F_BIT	498	msr CPSR_c, #Mode_ABT\|I_BIT\|F_BIT
499	mov r13, r0	499	mov r13, r0
500	sub r0, r0, #ABT_Stack_Size	500	sub r0, r0, #ABT_Stack_Size

Subversion Repositories NaviCtrl

(root)/tags/V2.00a/startup912.s @ 537 - Rev 369 → 376