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1 | /*############################################################################ |
1 | /*############################################################################ |
2 | ############################################################################*/ |
2 | ############################################################################*/ |
3 | 3 | ||
4 | #ifndef BLMC_H_ |
4 | #ifndef BLMC_H_ |
5 | #define BLMC_H_ |
5 | #define BLMC_H_ |
6 | 6 | ||
7 | extern volatile unsigned char Phase; |
7 | extern volatile unsigned char Phase; |
8 | extern volatile unsigned char ShadowTCCR1A; |
8 | extern volatile unsigned char ShadowTCCR1A; |
9 | extern volatile unsigned char CompInterruptFreigabe; |
9 | extern volatile unsigned char CompInterruptFreigabe; |
10 | 10 | ||
11 | void Blc(void); |
11 | void Blc(void); |
12 | void Manuell(void); |
12 | void Manuell(void); |
13 | 13 | ||
14 | // anselm |
14 | // anselm |
15 | /* |
15 | /* |
16 | #define COM1A ((0 << COM1A0) | (1 << COM1A1)) // COM1A-> OC1A non inverting mode |
16 | #define COM1A ((0 << COM1A0) | (1 << COM1A1)) // COM1A-> OC1A non inverting mode |
17 | #define COM1B ((0 << COM1B0) | (1 << COM1B1)) // COM1B-> OC1B non inverting mode |
17 | #define COM1B ((0 << COM1B0) | (1 << COM1B1)) // COM1B-> OC1B non inverting mode |
18 | #define COM2 ((0 << COM20) | (1 << COM21)) // COM2-> OC2 non inverting mode |
18 | #define COM2 ((0 << COM20) | (1 << COM21)) // COM2-> OC2 non inverting mode |
19 | 19 | ||
20 | #ifdef _32KHZ |
20 | #ifdef _32KHZ |
21 | #define WGM1 ((1 << WGM10) | (0 << WGM11)) // WGM10:13-> fast PWM 8bit |
21 | #define WGM1 ((1 << WGM10) | (0 << WGM11)) // WGM10:13-> fast PWM 8bit |
22 | #define WGMCS2 ((1 << WGM20) | (1 << WGM21) | (1 << CS20)) // WGM20:21-> fast PWM, no prescale |
22 | #define WGMCS2 ((1 << WGM20) | (1 << WGM21) | (1 << CS20)) // WGM20:21-> fast PWM, no prescale |
23 | #endif |
23 | #endif |
24 | 24 | ||
25 | #ifdef _16KHZ |
25 | #ifdef _16KHZ |
26 | #define WGM1 ((1 << WGM10) | (0 << WGM11)) // WGM10:13-> phase corr, PWM 8bit |
26 | #define WGM1 ((1 << WGM10) | (0 << WGM11)) // WGM10:13-> phase corr, PWM 8bit |
27 | #define WGMCS2 ((1 << WGM20) | (0 << WGM21) | (1 << CS20)) // WGM20:21-> phase corr. PWM, no prescale |
27 | #define WGMCS2 ((1 << WGM20) | (0 << WGM21) | (1 << CS20)) // WGM20:21-> phase corr. PWM, no prescale |
28 | #endif |
28 | #endif |
29 | 29 | ||
30 | #define PWM_C_ON {TCCR1A = COM1A | WGM1 | COM1B; TCCR2 = WGMCS2; |
30 | #define PWM_C_ON {TCCR1A = COM1A | WGM1 | COM1B; TCCR2 = WGMCS2; |
31 | DDRB = 0x02;} // Steuer_C+ output |
31 | DDRB = 0x02;} // Steuer_C+ output |
32 | #define PWM_B_ON {TCCR1A = COM1B | WGM1 | COM1A; TCCR2 = WGMCS2; \ |
32 | #define PWM_B_ON {TCCR1A = COM1B | WGM1 | COM1A; TCCR2 = WGMCS2; \ |
33 | DDRB = 0x04;} // Steuer_B+ output |
33 | DDRB = 0x04;} // Steuer_B+ output |
34 | #define PWM_A_ON {TCCR1A = WGM1; TCCR2 = COM2 | WGMCS2; \ |
34 | #define PWM_A_ON {TCCR1A = WGM1; TCCR2 = COM2 | WGMCS2; \ |
35 | DDRB = 0x08;} // Steuer_A+ output |
35 | DDRB = 0x08;} // Steuer_A+ output |
36 | #define PWM_OFF {TCCR1A = WGM1; \ |
36 | #define PWM_OFF {TCCR1A = WGM1; \ |
37 | TCCR2 = WGMCS2; \ |
37 | TCCR2 = WGMCS2; \ |
38 | PORTB &= ~0x0E; DDRB = 0x0E;} // OC1x & OC2 disconnected, Steuer_X+ output low |
38 | PORTB &= ~0x0E; DDRB = 0x0E;} // OC1x & OC2 disconnected, Steuer_X+ output low |
39 | // anselm |
39 | // anselm |
40 | */ |
40 | */ |
41 | 41 | ||
42 | #ifdef _32KHZ |
42 | #ifdef _32KHZ |
43 | #define PWM_C_ON {TCCR1A = 0xAD; TCCR2 = 0x49;DDRB = 0x0A;} |
43 | #define PWM_C_ON {TCCR1A = 0xAD; TCCR2 = 0x49;DDRB = 0x0A;} |
44 | #define PWM_B_ON {TCCR1A = 0xAD; TCCR2 = 0x49;DDRB = 0x0C;} |
44 | #define PWM_B_ON {TCCR1A = 0xAD; TCCR2 = 0x49;DDRB = 0x0C;} |
45 | #define PWM_A_ON {TCCR1A = 0xAD; TCCR2 = 0x69;DDRB = 0x08;} |
45 | #define PWM_A_ON {TCCR1A = 0xAD; TCCR2 = 0x69;DDRB = 0x08;} |
46 | #define PWM_OFF {TCCR1A = 0x0D; TCCR2 = 0x49;PORTC &= ~0x0E;} |
46 | #define PWM_OFF {TCCR1A = 0x0D; TCCR2 = 0x49;PORTC &= ~0x0E;} |
47 | #endif |
47 | #endif |
48 | 48 | ||
49 | #ifdef _16KHZ |
49 | #ifdef _16KHZ |
50 | // #define PWM_C_ON {TCCR1A = 0xA2; TCCR2 = 0x41; DDRB = 0x0A;} |
50 | // #define PWM_C_ON {TCCR1A = 0xA2; TCCR2 = 0x41; DDRB = 0x0A;} |
51 | // #define PWM_B_ON {TCCR1A = 0xA2; TCCR2 = 0x41; DDRB = 0x0C;} |
51 | // #define PWM_B_ON {TCCR1A = 0xA2; TCCR2 = 0x41; DDRB = 0x0C;} |
52 | // #define PWM_A_ON {TCCR1A = 0xA2; TCCR2 = 0x61; DDRB = 0x08;} |
52 | // #define PWM_A_ON {TCCR1A = 0xA2; TCCR2 = 0x61; DDRB = 0x08;} |
53 | 53 | ||
54 | // #define PWM_C_ON {TCCR2 = 0x41; if(PPM_Betrieb) { TCCR1A = 0xA1;DDRB = 0x0A;} else { TCCR1A = 0x81; DDRB = 0x0E;}} |
54 | // #define PWM_C_ON {TCCR2 = 0x41; if(PPM_Betrieb) { TCCR1A = 0xA1;DDRB = 0x0A;} else { TCCR1A = 0x81; DDRB = 0x0E;}} |
55 | // #define PWM_B_ON {TCCR2 = 0x41; if(PPM_Betrieb) { TCCR1A = 0xA1;DDRB = 0x0C;} else { TCCR1A = 0x21; DDRB = 0x0E;}} |
55 | // #define PWM_B_ON {TCCR2 = 0x41; if(PPM_Betrieb) { TCCR1A = 0xA1;DDRB = 0x0C;} else { TCCR1A = 0x21; DDRB = 0x0E;}} |
56 | // #define PWM_A_ON {TCCR2 = 0x61; if(PPM_Betrieb) { TCCR1A = 0xA1;DDRB = 0x08;} else { TCCR1A = 0x01; DDRB = 0x0E;}} |
56 | // #define PWM_A_ON {TCCR2 = 0x61; if(PPM_Betrieb) { TCCR1A = 0xA1;DDRB = 0x08;} else { TCCR1A = 0x01; DDRB = 0x0E;}} |
57 | 57 | ||
58 | #define PWM_C_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x02;} |
58 | #define PWM_C_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x02;} |
59 | #define PWM_B_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x04;} |
59 | #define PWM_B_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x04;} |
60 | #define PWM_A_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x08;} |
60 | #define PWM_A_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x08;} |
61 | 61 | ||
62 | 62 | ||
63 | // #define PWM_C_ON {TCCR1A = 0x82; TCCR2 = 0x41; PORTB &= ~0x04; DDRB = 0x0E;} |
63 | // #define PWM_C_ON {TCCR1A = 0x82; TCCR2 = 0x41; PORTB &= ~0x04; DDRB = 0x0E;} |
64 | // #define PWM_B_ON {TCCR1A = 0x22; TCCR2 = 0x41; PORTB &= ~0x02; DDRB = 0x0E;} |
64 | // #define PWM_B_ON {TCCR1A = 0x22; TCCR2 = 0x41; PORTB &= ~0x02; DDRB = 0x0E;} |
65 | // #define PWM_A_ON {TCCR1A = 0x02; TCCR2 = 0x61; PORTB &= ~0x06; DDRB = 0x0E;} |
65 | // #define PWM_A_ON {TCCR1A = 0x02; TCCR2 = 0x61; PORTB &= ~0x06; DDRB = 0x0E;} |
66 | 66 | ||
67 | #define PWM_OFF {OCR1A = 0; OCR1B = 0; OCR2 = 0; TCCR1A = 0x01; TCCR2 = 0x41; DDRB = 0x0E; PORTB &= ~0x0E;} |
67 | #define PWM_OFF {OCR1A = 0; OCR1B = 0; OCR2 = 0; TCCR1A = 0x01; TCCR2 = 0x41; DDRB = 0x0E; PORTB &= ~0x0E;} |
68 | #endif |
68 | #endif |
69 | 69 | ||
70 | #define STEUER_A_H {PWM_A_ON} |
70 | #define STEUER_A_H {PWM_A_ON} |
71 | #define STEUER_B_H {PWM_B_ON} |
71 | #define STEUER_B_H {PWM_B_ON} |
72 | #define STEUER_C_H {PWM_C_ON} |
72 | #define STEUER_C_H {PWM_C_ON} |
73 | 73 | ||
74 | #define STEUER_A_L {PORTD &= ~0x30; PORTD |= 0x08;} |
74 | #define STEUER_A_L {PORTD &= ~0x30; PORTD |= 0x08;} |
75 | #define STEUER_B_L {PORTD &= ~0x28; PORTD |= 0x10;} |
75 | #define STEUER_B_L {PORTD &= ~0x28; PORTD |= 0x10;} |
76 | #define STEUER_C_L {PORTD &= ~0x18; PORTD |= 0x20;} |
76 | #define STEUER_C_L {PORTD &= ~0x18; PORTD |= 0x20;} |
77 | #define STEUER_OFF {PORTD &= ~0x38; PWM_OFF; } |
77 | #define STEUER_OFF {PORTD &= ~0x38; PWM_OFF; } |
78 | #define FETS_OFF {PORTD &= ~0x38; PORTB &= ~0x0E; } |
78 | #define FETS_OFF {PORTD &= ~0x38; PORTB &= ~0x0E; } |
79 | 79 | ||
80 | #define SENSE_A ADMUX = 0 | IntRef; |
80 | #define SENSE_A ADMUX = 0 | IntRef; |
81 | #define SENSE_B ADMUX = 1 | IntRef; |
81 | #define SENSE_B ADMUX = 1 | IntRef; |
82 | #define SENSE_C ADMUX = 2 | IntRef; |
82 | #define SENSE_C ADMUX = 2 | IntRef; |
83 | 83 | ||
84 | #define ClrSENSE ACSR |= 0x10 |
84 | #define ClrSENSE ACSR |= 0x10 |
85 | #define SENSE ((ACSR & 0x10)) |
85 | #define SENSE ((ACSR & 0x10)) |
86 | #define SENSE_L (!(ACSR & 0x20)) |
86 | #define SENSE_L (!(ACSR & 0x20)) |
87 | #define SENSE_H ((ACSR & 0x20)) |
87 | #define SENSE_H ((ACSR & 0x20)) |
88 | #define ENABLE_SENSE_INT {CompInterruptFreigabe = 1;ACSR |= 0x0A; } |
88 | #define ENABLE_SENSE_INT {CompInterruptFreigabe = 1;ACSR |= 0x0A; } |
89 | #define DISABLE_SENSE_INT {CompInterruptFreigabe = 0; ACSR &= ~0x08; } |
89 | #define DISABLE_SENSE_INT {CompInterruptFreigabe = 0; ACSR &= ~0x08; } |
90 | 90 | ||
91 | 91 | ||
92 | #define SENSE_FALLING_INT ACSR &= ~0x01 |
92 | #define SENSE_FALLING_INT ACSR &= ~0x01 |
93 | #define SENSE_RISING_INT ACSR |= 0x03 |
93 | #define SENSE_RISING_INT ACSR |= 0x03 |
94 | #define SENSE_TOGGLE_INT ACSR &= ~0x03 |
94 | #define SENSE_TOGGLE_INT ACSR &= ~0x03 |
95 | 95 | ||
96 | #endif //BLMC_H_ |
96 | #endif //BLMC_H_ |
97 | 97 | ||
98 | 98 |