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1 | /******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** |
1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** |
2 | * File Name : 91x_dma.c |
2 | * File Name : 91x_dma.c |
3 | * Author : MCD Application Team |
3 | * Author : MCD Application Team |
- | 4 | * Version : V2.1 |
|
4 | * Date First Issued : 05/18/2006 : Version 1.0 |
5 | * Date : 12/22/2008 |
5 | * Description : This file provides all the DMA software functions |
6 | * Description : This file provides all the DMA firmware functions |
6 | * needed to access all DMA registers. |
7 | * needed to access all DMA registers. |
7 | ******************************************************************************** |
8 | ******************************************************************************** |
8 | * History:v 1.0 |
- | |
9 | * 05/22/2007 : Version 1.2 |
- | |
10 | * 05/24/2006 : Version 1.1 |
- | |
11 | * 05/18/2006 : Version 1.0 |
- | |
12 | ******************************************************************************** |
- | |
13 | * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
9 | * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
14 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
15 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
16 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
17 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
13 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
18 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
19 | *******************************************************************************/ |
15 | *******************************************************************************/ |
20 | 16 | ||
21 | /* Includes ------------------------------------------------------------------*/ |
17 | /* Includes ------------------------------------------------------------------*/ |
22 | 18 | ||
23 | # include"91x_dma.h" |
19 | # include"91x_dma.h" |
24 | # include"91x_scu.h" |
20 | # include"91x_scu.h" |
25 | 21 | ||
26 | /* Private typedef -----------------------------------------------------------*/ |
22 | /* Private typedef -----------------------------------------------------------*/ |
27 | /* Private define ------------------------------------------------------------*/ |
23 | /* Private define ------------------------------------------------------------*/ |
28 | /* Private macro -------------------------------------------------------------*/ |
24 | /* Private macro -------------------------------------------------------------*/ |
29 | /* Private variables ---------------------------------------------------------*/ |
25 | /* Private variables ---------------------------------------------------------*/ |
30 | 26 | ||
31 | 27 | ||
32 | /* DMA Masks "used" only in this module */ |
28 | /* DMA Masks "used" only in this module */ |
33 | 29 | ||
34 | #define DMA_Width_DES_MASK 0xFF1FFFFF |
30 | #define DMA_Width_DES_MASK 0xFF1FFFFF |
35 | #define DMA_Width_SRC_MASK 0xFFE3FFFF |
31 | #define DMA_Width_SRC_MASK 0xFFE3FFFF |
36 | #define DMA_Bst_DES_MASK 0xFFFC7FFF |
32 | #define DMA_Bst_DES_MASK 0xFFFC7FFF |
37 | #define DMA_Bst_SRC_MASK 0xFFFF8FFF |
33 | #define DMA_Bst_SRC_MASK 0xFFFF8FFF |
38 | #define DMA_FlowCntrl_Mask 0xFFFFC7FF |
34 | #define DMA_FlowCntrl_Mask 0xFFFFC7FF |
39 | #define DMA_TrsfSisze_Mask 0xFFFFF000 |
35 | #define DMA_TrsfSisze_Mask 0xFFFFF000 |
40 | #define SRC_Mask 0xFFFFFFE1 |
36 | #define SRC_Mask 0xFFFFFFE1 |
41 | #define DES_Mask 0xFFFFFC3F |
37 | #define DES_Mask 0xFFFFFC3F |
42 | #define DMA_TCIE 0x80000000 |
38 | #define DMA_TCIE 0x80000000 |
43 | #define DMA_ChannelDESInc 0x08000000 |
39 | #define DMA_ChannelDESInc 0x08000000 |
44 | #define DMA_ChannelSRCInc 0x04000000 |
40 | #define DMA_ChannelSRCInc 0x04000000 |
45 | #define DMA_BufferChannel 0x20000000 |
41 | #define DMA_BufferChannel 0x20000000 |
46 | #define DMA_HaltChannel 0x00040000 |
42 | #define DMA_HaltChannel 0x00040000 |
47 | #define DMA_LockChannel 0x00010000 |
43 | #define DMA_LockChannel 0x00010000 |
48 | #define DMA_CacheChannel 0x40000000 |
44 | #define DMA_CacheChannel 0x40000000 |
49 | #define DMA_ChannelActive 0x00020000 |
45 | #define DMA_ChannelActive 0x00020000 |
50 | #define DMA_Enable 0x00000001 |
46 | #define DMA_Enable 0x00000001 |
51 | #define DMA_ChannelEnable 0x00000001 |
47 | #define DMA_ChannelEnable 0x00000001 |
- | 48 | ||
- | 49 | /*LLI Masks used for linked list's control word stucture*/ |
|
- | 50 | ||
- | 51 | #define DMA_SrcIncrement_MASK 0xFBFFFFFF |
|
- | 52 | #define DMA_DesIncrement_MASK 0xF7FFFFFF |
|
- | 53 | #define DMA_CacheableAccess_MASK 0xEFFFFFFF |
|
- | 54 | #define DMA_BufferableAccess_MASK 0xDFFFFFFF |
|
- | 55 | #define DMA_PrivilegedAccess_MASK 0xBFFFFFFF |
|
52 | 56 | #define DMA_TCInterrupt_MASK 0x7FFFFFFF |
|
53 | 57 | ||
54 | 58 | ||
55 | 59 | ||
56 | /* Private function prototypes -----------------------------------------------*/ |
60 | /* Private function prototypes -----------------------------------------------*/ |
57 | /* Private functions ---------------------------------------------------------*/ |
61 | /* Private functions ---------------------------------------------------------*/ |
58 | 62 | ||
59 | /******************************************************************************* |
63 | /******************************************************************************* |
60 | * Function Name : DMA_ITMaskConfig |
64 | * Function Name : DMA_ITMaskConfig |
61 | * Description : Enables or disables the specified DMA_Channelx Mask interrupt. |
65 | * Description : Enables or disables the specified DMA_Channelx Mask interrupt. |
62 | * Input : |
66 | * Input : |
63 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
67 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
64 | * -DMA_ITMask: specifies the DMA interrupt mask source to be enabled or disabled. |
68 | * -DMA_ITMask: specifies the DMA interrupt mask source to be enabled or disabled. |
65 | * This parameter can be: |
69 | * This parameter can be: |
66 | * - DMA_ITMask_IE (Interrupt error mask). |
70 | * - DMA_ITMask_IE (Interrupt error mask). |
67 | * - DMA_ITMask_ITC (Terminal count interrupt mask). |
71 | * - DMA_ITMask_ITC (Terminal count interrupt mask). |
68 | * - DMA_ITMask_ALL ( All interrupts mask) |
72 | * - DMA_ITMask_ALL ( All interrupts mask) |
69 | * |
73 | * |
70 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
74 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
71 | * This parameter can be: ENABLE or DISABLE. |
75 | * This parameter can be: ENABLE or DISABLE. |
72 | * Output : None. |
76 | * Output : None. |
73 | * Return : None. |
77 | * Return : None. |
74 | *******************************************************************************/ |
78 | *******************************************************************************/ |
75 | 79 | ||
76 | 80 | ||
77 | void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask , FunctionalState NewState) |
81 | void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask , FunctionalState NewState) |
78 | 82 | ||
79 | { |
83 | { |
80 | if (NewState==ENABLE) /* Mask the Interrupt */ |
84 | if (NewState==ENABLE) /* Mask the Interrupt */ |
81 | { |
85 | { |
82 | DMA_Channelx-> CCNF |= DMA_ITMask ; |
86 | DMA_Channelx-> CCNF |= DMA_ITMask ; |
83 | } |
87 | } |
84 | 88 | ||
85 | else /* Disable the Interrupt Mask*/ |
89 | else /* Disable the Interrupt Mask*/ |
86 | { |
90 | { |
87 | DMA_Channelx-> CCNF &= ~ DMA_ITMask ; |
91 | DMA_Channelx-> CCNF &= ~ DMA_ITMask ; |
88 | } |
92 | } |
89 | } |
93 | } |
90 | 94 | ||
91 | 95 | ||
92 | 96 | ||
93 | 97 | ||
94 | 98 | ||
95 | /******************************************************************************* |
99 | /******************************************************************************* |
96 | * Function Name : DMA_ITConfig |
100 | * Function Name : DMA_ITConfig |
97 | * Description : Enables or disables the DMA_Channelx Terminal Count interrupt. |
101 | * Description : Enables or disables the DMA_Channelx Terminal Count interrupt. |
98 | * Input : |
102 | * Input : |
99 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
103 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
100 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
104 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
101 | * This parameter can be: ENABLE or DISABLE. |
105 | * This parameter can be: ENABLE or DISABLE. |
102 | * Output : None. |
106 | * Output : None. |
103 | * Return : None. |
107 | * Return : None. |
104 | *******************************************************************************/ |
108 | *******************************************************************************/ |
105 | 109 | ||
106 | 110 | ||
107 | void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
111 | void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
108 | 112 | ||
109 | { |
113 | { |
110 | if (NewState==ENABLE) /* Enable the Terminal Count Interrupt */ |
114 | if (NewState==ENABLE) /* Enable the Terminal Count Interrupt */ |
111 | { |
115 | { |
112 | DMA_Channelx->CC |= DMA_TCIE ; |
116 | DMA_Channelx->CC |= DMA_TCIE ; |
113 | } |
117 | } |
114 | 118 | ||
115 | else /* Disable the Terminal Count Interrupt */ |
119 | else /* Disable the Terminal Count Interrupt */ |
116 | { |
120 | { |
117 | DMA_Channelx-> CC &= ~ DMA_TCIE ; |
121 | DMA_Channelx-> CC &= ~ DMA_TCIE ; |
118 | } |
122 | } |
119 | } |
123 | } |
120 | 124 | ||
121 | 125 | ||
122 | /******************************************************************************** |
126 | /******************************************************************************** |
123 | * Function Name : DMA_SyncConfig |
127 | * Function Name : DMA_SyncConfig |
124 | * Description : Enables or disables synchronization logic for the corresponding DMA Request Signal. |
128 | * Description : Enables or disables synchronization logic for the corresponding DMA Request Signal. |
125 | * Input : |
129 | * Input : |
126 | * -SRCReq:specifies the DMA Request Source. |
130 | * -SRCReq:specifies the DMA Request Source. |
127 | * This parameter can be: |
131 | * This parameter can be: |
128 | * -DMA_USB_RX_Mask |
132 | * -DMA_USB_RX_Mask |
129 | * -DMA_USB_TX_Mask |
133 | * -DMA_USB_TX_Mask |
130 | * -DMA_TIM0_Mask |
134 | * -DMA_TIM0_Mask |
131 | * -DMA_TIM1_Mask |
135 | * -DMA_TIM1_Mask |
132 | * -DMA_UART0_RX_Mask |
136 | * -DMA_UART0_RX_Mask |
133 | * -DMA_UART0_TX_Mask |
137 | * -DMA_UART0_TX_Mask |
134 | * -DMA_UART1_RX_Mask |
138 | * -DMA_UART1_RX_Mask |
135 | * -DMA_UART1_TX_Mask |
139 | * -DMA_UART1_TX_Mask |
136 | * -DMA_External_Req0_Mask |
140 | * -DMA_External_Req0_Mask |
137 | * -DMA_External_Req1_Mask |
141 | * -DMA_External_Req1_Mask |
138 | * -DMA_I2C0_Mask |
142 | * -DMA_I2C0_Mask |
139 | * -DMA_I2C1_Mask |
143 | * -DMA_I2C1_Mask |
140 | * -DMA_SSP0_RX_Mask |
144 | * -DMA_SSP0_RX_Mask |
141 | * -DMA_SSP0_TX_Mask |
145 | * -DMA_SSP0_TX_Mask |
142 | * -DMA_SSP1_RX_Mask |
146 | * -DMA_SSP1_RX_Mask |
143 | * -DMA_SSP1_TX_Mask |
147 | * -DMA_SSP1_TX_Mask |
144 | * |
148 | * |
145 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
149 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
146 | * This parameter can be: ENABLE or DISABLE. |
150 | * This parameter can be: ENABLE or DISABLE. |
147 | * Output : None. |
151 | * Output : None. |
148 | * Return : None. |
152 | * Return : None. |
149 | *******************************************************************************/ |
153 | *******************************************************************************/ |
150 | 154 | ||
151 | 155 | ||
152 | void DMA_SyncConfig(u16 SRCReq, FunctionalState NewState) |
156 | void DMA_SyncConfig(u16 SRCReq, FunctionalState NewState) |
153 | 157 | ||
154 | { |
158 | { |
155 | if (NewState==ENABLE) /* Enable the synchronization logic for the corresponding DMA Request Signal */ |
159 | if (NewState==ENABLE) /* Enable the synchronization logic for the corresponding DMA Request Signal */ |
156 | { |
160 | { |
157 | 161 | ||
158 | DMA->SYNR &= ~ SRCReq ; |
162 | DMA->SYNR &= ~ SRCReq ; |
159 | 163 | ||
160 | } |
164 | } |
161 | 165 | ||
162 | else /* Disable the synchronization logic for the corresponding DMA Request Signal. */ |
166 | else /* Disable the synchronization logic for the corresponding DMA Request Signal. */ |
163 | { |
167 | { |
164 | DMA->SYNR |= SRCReq ; |
168 | DMA->SYNR |= SRCReq ; |
165 | 169 | ||
166 | } |
170 | } |
167 | } |
171 | } |
168 | 172 | ||
169 | 173 | ||
170 | /******************************************************************************** |
174 | /******************************************************************************** |
171 | * Function Name : DMA_SetSReq |
175 | * Function Name : DMA_SetSReq |
172 | * Description : Set the DMA to generate a Single transfer request for the corresponding DMA Request Source. |
176 | * Description : Set the DMA to generate a Single transfer request for the corresponding DMA Request Source. |
173 | * Input : |
177 | * Input : |
174 | * -SRCReq:specifies the DMA Request Source. |
178 | * -SRCReq:specifies the DMA Request Source. |
175 | * This parameter can be: |
179 | * This parameter can be: |
176 | * -DMA_USB_RX_Mask |
180 | * -DMA_USB_RX_Mask |
177 | * -DMA_USB_TX_Mask |
181 | * -DMA_USB_TX_Mask |
178 | * -DMA_TIM0_Mask |
182 | * -DMA_TIM0_Mask |
179 | * -DMA_TIM1_Mask |
183 | * -DMA_TIM1_Mask |
180 | * -DMA_UART0_RX_Mask |
184 | * -DMA_UART0_RX_Mask |
181 | * -DMA_UART0_TX_Mask |
185 | * -DMA_UART0_TX_Mask |
182 | * -DMA_UART1_RX_Mask |
186 | * -DMA_UART1_RX_Mask |
183 | * -DMA_UART1_TX_Mask |
187 | * -DMA_UART1_TX_Mask |
184 | * -DMA_External_Req0_Mask |
188 | * -DMA_External_Req0_Mask |
185 | * -DMA_External_Req1_Mask |
189 | * -DMA_External_Req1_Mask |
186 | * -DMA_I2C0_Mask |
190 | * -DMA_I2C0_Mask |
187 | * -DMA_I2C1_Mask |
191 | * -DMA_I2C1_Mask |
188 | * -DMA_SSP0_RX_Mask |
192 | * -DMA_SSP0_RX_Mask |
189 | * -DMA_SSP0_TX_Mask |
193 | * -DMA_SSP0_TX_Mask |
190 | * -DMA_SSP1_RX_Mask |
194 | * -DMA_SSP1_RX_Mask |
191 | * -DMA_SSP1_TX_Mask |
195 | * -DMA_SSP1_TX_Mask |
192 | * |
196 | * |
193 | * Output : None. |
197 | * Output : None. |
194 | * Return : None. |
198 | * Return : None. |
195 | *******************************************************************************/ |
199 | *******************************************************************************/ |
196 | 200 | ||
197 | 201 | ||
198 | void DMA_SetSReq(u16 SRCReq) |
202 | void DMA_SetSReq(u16 SRCReq) |
199 | 203 | ||
200 | { /* Set the DMA to generate a Single transfer request for the corresponding DMA Request Source */ |
204 | { /* Set the DMA to generate a Single transfer request for the corresponding DMA Request Source */ |
201 | DMA->SSRR |= SRCReq ; |
205 | DMA->SSRR |= SRCReq ; |
202 | } |
206 | } |
203 | 207 | ||
204 | 208 | ||
205 | 209 | ||
206 | 210 | ||
207 | /******************************************************************************** |
211 | /******************************************************************************** |
208 | * Function Name : DMA_SetLSReq |
212 | * Function Name : DMA_SetLSReq |
209 | * Description : Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source. |
213 | * Description : Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source. |
210 | * Input : |
214 | * Input : |
211 | * -SRCReq:specifies the DMA Request Source. |
215 | * -SRCReq:specifies the DMA Request Source. |
212 | * This parameter can be: |
216 | * This parameter can be: |
213 | * -DMA_USB_RX_Mask |
217 | * -DMA_USB_RX_Mask |
214 | * -DMA_USB_TX_Mask |
218 | * -DMA_USB_TX_Mask |
215 | * -DMA_TIM0_Mask |
219 | * -DMA_TIM0_Mask |
216 | * -DMA_TIM1_Mask |
220 | * -DMA_TIM1_Mask |
217 | * -DMA_UART0_RX_Mask |
221 | * -DMA_UART0_RX_Mask |
218 | * -DMA_UART0_TX_Mask |
222 | * -DMA_UART0_TX_Mask |
219 | * -DMA_UART1_RX_Mask |
223 | * -DMA_UART1_RX_Mask |
220 | * -DMA_UART1_TX_Mask |
224 | * -DMA_UART1_TX_Mask |
221 | * -DMA_External_Req0_Mask |
225 | * -DMA_External_Req0_Mask |
222 | * -DMA_External_Req1_Mask |
226 | * -DMA_External_Req1_Mask |
223 | * -DMA_I2C0_Mask |
227 | * -DMA_I2C0_Mask |
224 | * -DMA_I2C1_Mask |
228 | * -DMA_I2C1_Mask |
225 | * -DMA_SSP0_RX_Mask |
229 | * -DMA_SSP0_RX_Mask |
226 | * -DMA_SSP0_TX_Mask |
230 | * -DMA_SSP0_TX_Mask |
227 | * -DMA_SSP1_RX_Mask |
231 | * -DMA_SSP1_RX_Mask |
228 | * -DMA_SSP1_TX_Mask |
232 | * -DMA_SSP1_TX_Mask |
229 | * Output : None. |
233 | * Output : None. |
230 | * Return : None. |
234 | * Return : None. |
231 | *******************************************************************************/ |
235 | *******************************************************************************/ |
232 | 236 | ||
233 | void DMA_SetLSReq(u16 SRCReq ) |
237 | void DMA_SetLSReq(u16 SRCReq ) |
234 | { /* Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source */ |
238 | { /* Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source */ |
235 | DMA->SLSRR |= SRCReq ; |
239 | DMA->SLSRR |= SRCReq ; |
236 | } |
240 | } |
237 | 241 | ||
238 | 242 | ||
239 | /******************************************************************************** |
243 | /******************************************************************************** |
240 | * Function Name : DMA_SetBReq |
244 | * Function Name : DMA_SetBReq |
241 | * Description : Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source. |
245 | * Description : Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source. |
242 | * Input : |
246 | * Input : |
243 | * -SRCReq:specifies the DMA Request Source. |
247 | * -SRCReq:specifies the DMA Request Source. |
244 | * This parameter can be: |
248 | * This parameter can be: |
245 | * -DMA_USB_RX_Mask |
249 | * -DMA_USB_RX_Mask |
246 | * -DMA_USB_TX_Mask |
250 | * -DMA_USB_TX_Mask |
247 | * -DMA_TIM0_Mask |
251 | * -DMA_TIM0_Mask |
248 | * -DMA_TIM1_Mask |
252 | * -DMA_TIM1_Mask |
249 | * -DMA_UART0_RX_Mask |
253 | * -DMA_UART0_RX_Mask |
250 | * -DMA_UART0_TX_Mask |
254 | * -DMA_UART0_TX_Mask |
251 | * -DMA_UART1_RX_Mask |
255 | * -DMA_UART1_RX_Mask |
252 | * -DMA_UART1_TX_Mask |
256 | * -DMA_UART1_TX_Mask |
253 | * -DMA_External_Req0_Mask |
257 | * -DMA_External_Req0_Mask |
254 | * -DMA_External_Req1_Mask |
258 | * -DMA_External_Req1_Mask |
255 | * -DMA_I2C0_Mask |
259 | * -DMA_I2C0_Mask |
256 | * -DMA_I2C1_Mask |
260 | * -DMA_I2C1_Mask |
257 | * -DMA_SSP0_RX_Mask |
261 | * -DMA_SSP0_RX_Mask |
258 | * -DMA_SSP0_TX_Mask |
262 | * -DMA_SSP0_TX_Mask |
259 | * -DMA_SSP1_RX_Mask |
263 | * -DMA_SSP1_RX_Mask |
260 | * -DMA_SSP1_TX_Mask |
264 | * -DMA_SSP1_TX_Mask |
261 | * Output : None. |
265 | * Output : None. |
262 | * Return : None. |
266 | * Return : None. |
263 | *******************************************************************************/ |
267 | *******************************************************************************/ |
264 | 268 | ||
265 | 269 | ||
266 | void DMA_SetBReq(u16 SRCReq) |
270 | void DMA_SetBReq(u16 SRCReq) |
267 | 271 | ||
268 | { /* Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source */ |
272 | { /* Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source */ |
269 | DMA->SBRR |= SRCReq ; |
273 | DMA->SBRR |= SRCReq ; |
270 | } |
274 | } |
271 | 275 | ||
272 | 276 | ||
273 | 277 | ||
274 | /******************************************************************************** |
278 | /******************************************************************************** |
275 | * Function Name : DMA_SetLBReq |
279 | * Function Name : DMA_SetLBReq |
276 | * Description : Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source. |
280 | * Description : Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source. |
277 | * Input : |
281 | * Input : |
278 | * -SRCReq:specifies the DMA Request Source. |
282 | * -SRCReq:specifies the DMA Request Source. |
279 | * This parameter can be: |
283 | * This parameter can be: |
280 | * -DMA_USB_RX_Mask |
284 | * -DMA_USB_RX_Mask |
281 | * -DMA_USB_TX_Mask |
285 | * -DMA_USB_TX_Mask |
282 | * -DMA_TIM0_Mask |
286 | * -DMA_TIM0_Mask |
283 | * -DMA_TIM1_Mask |
287 | * -DMA_TIM1_Mask |
284 | * -DMA_UART0_RX_Mask |
288 | * -DMA_UART0_RX_Mask |
285 | * -DMA_UART0_TX_Mask |
289 | * -DMA_UART0_TX_Mask |
286 | * -DMA_UART1_RX_Mask |
290 | * -DMA_UART1_RX_Mask |
287 | * -DMA_UART1_TX_Mask |
291 | * -DMA_UART1_TX_Mask |
288 | * -DMA_External_Req0_Mask |
292 | * -DMA_External_Req0_Mask |
289 | * -DMA_External_Req1_Mask |
293 | * -DMA_External_Req1_Mask |
290 | * -DMA_I2C0_Mask |
294 | * -DMA_I2C0_Mask |
291 | * -DMA_I2C1_Mask |
295 | * -DMA_I2C1_Mask |
292 | * -DMA_SSP0_RX_Mask |
296 | * -DMA_SSP0_RX_Mask |
293 | * -DMA_SSP0_TX_Mask |
297 | * -DMA_SSP0_TX_Mask |
294 | * -DMA_SSP1_RX_Mask |
298 | * -DMA_SSP1_RX_Mask |
295 | * -DMA_SSP1_TX_Mask |
299 | * -DMA_SSP1_TX_Mask |
296 | * Output : None. |
300 | * Output : None. |
297 | * Return : None. |
301 | * Return : None. |
298 | *******************************************************************************/ |
302 | *******************************************************************************/ |
299 | 303 | ||
300 | 304 | ||
301 | void DMA_SetLBReq(u16 SRCReq) |
305 | void DMA_SetLBReq(u16 SRCReq) |
302 | 306 | ||
303 | { /* Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source */ |
307 | { /* Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source */ |
304 | DMA->SLBRR |= SRCReq ; |
308 | DMA->SLBRR |= SRCReq ; |
305 | } |
309 | } |
306 | 310 | ||
307 | 311 | ||
308 | /******************************************************************************** |
312 | /******************************************************************************** |
309 | * Function Name : DMA_GetSReq |
313 | * Function Name : DMA_GetSReq |
310 | * Description : Check for a specific source if it request a Single transfer . |
314 | * Description : Check for a specific source if it request a Single transfer . |
311 | * Input : |
315 | * Input : |
312 | * Input : |
316 | * Input : |
313 | * -SRCReq:specifies the DMA Request Source. |
317 | * -SRCReq:specifies the DMA Request Source. |
314 | * This parameter can be: |
318 | * This parameter can be: |
315 | * -DMA_USB_RX_Mask |
319 | * -DMA_USB_RX_Mask |
316 | * -DMA_USB_TX_Mask |
320 | * -DMA_USB_TX_Mask |
317 | * -DMA_TIM0_Mask |
321 | * -DMA_TIM0_Mask |
318 | * -DMA_TIM1_Mask |
322 | * -DMA_TIM1_Mask |
319 | * -DMA_UART0_RX_Mask |
323 | * -DMA_UART0_RX_Mask |
320 | * -DMA_UART0_TX_Mask |
324 | * -DMA_UART0_TX_Mask |
321 | * -DMA_UART1_RX_Mask |
325 | * -DMA_UART1_RX_Mask |
322 | * -DMA_UART1_TX_Mask |
326 | * -DMA_UART1_TX_Mask |
323 | * -DMA_External_Req0_Mask |
327 | * -DMA_External_Req0_Mask |
324 | * -DMA_External_Req1_Mask |
328 | * -DMA_External_Req1_Mask |
325 | * -DMA_I2C0_Mask |
329 | * -DMA_I2C0_Mask |
326 | * -DMA_I2C1_Mask |
330 | * -DMA_I2C1_Mask |
327 | * -DMA_SSP0_RX_Mask |
331 | * -DMA_SSP0_RX_Mask |
328 | * -DMA_SSP0_TX_Mask |
332 | * -DMA_SSP0_TX_Mask |
329 | * -DMA_SSP1_RX_Mask |
333 | * -DMA_SSP1_RX_Mask |
330 | * -DMA_SSP1_TX_Mask |
334 | * -DMA_SSP1_TX_Mask |
331 | * Output : None. |
335 | * Output : None. |
332 | * Return : SET or RESET. |
336 | * Return : SET or RESET. |
333 | *******************************************************************************/ |
337 | *******************************************************************************/ |
334 | 338 | ||
335 | 339 | ||
336 | FlagStatus DMA_GetSReq(u16 SRCReq) |
340 | FlagStatus DMA_GetSReq(u16 SRCReq) |
337 | 341 | ||
338 | { /* Check for a specific source if it request a Single transfer . */ |
342 | { /* Check for a specific source if it request a Single transfer . */ |
339 | if ( (DMA->SSRR & SRCReq )!= RESET ) |
343 | if ( (DMA->SSRR & SRCReq )!= RESET ) |
340 | { |
344 | { |
341 | return SET; |
345 | return SET; |
342 | } |
346 | } |
343 | 347 | ||
344 | else |
348 | else |
345 | { |
349 | { |
346 | return RESET; |
350 | return RESET; |
347 | } |
351 | } |
348 | } |
352 | } |
349 | 353 | ||
350 | 354 | ||
351 | /******************************************************************************** |
355 | /******************************************************************************** |
352 | * Function Name : DMA_GetLSReq |
356 | * Function Name : DMA_GetLSReq |
353 | * Description : Check for a specific source if it request a Last Single transfer . |
357 | * Description : Check for a specific source if it request a Last Single transfer . |
354 | * Input : |
358 | * Input : |
355 | * -SRCReq:specifies the DMA Request Source. |
359 | * -SRCReq:specifies the DMA Request Source. |
356 | * This parameter can be: |
360 | * This parameter can be: |
357 | * -DMA_USB_RX_Mask |
361 | * -DMA_USB_RX_Mask |
358 | * -DMA_USB_TX_Mask |
362 | * -DMA_USB_TX_Mask |
359 | * -DMA_TIM0_Mask |
363 | * -DMA_TIM0_Mask |
360 | * -DMA_TIM1_Mask |
364 | * -DMA_TIM1_Mask |
361 | * -DMA_UART0_RX_Mask |
365 | * -DMA_UART0_RX_Mask |
362 | * -DMA_UART0_TX_Mask |
366 | * -DMA_UART0_TX_Mask |
363 | * -DMA_UART1_RX_Mask |
367 | * -DMA_UART1_RX_Mask |
364 | * -DMA_UART1_TX_Mask |
368 | * -DMA_UART1_TX_Mask |
365 | * -DMA_External_Req0_Mask |
369 | * -DMA_External_Req0_Mask |
366 | * -DMA_External_Req1_Mask |
370 | * -DMA_External_Req1_Mask |
367 | * -DMA_I2C0_Mask |
371 | * -DMA_I2C0_Mask |
368 | * -DMA_I2C1_Mask |
372 | * -DMA_I2C1_Mask |
369 | * -DMA_SSP0_RX_Mask |
373 | * -DMA_SSP0_RX_Mask |
370 | * -DMA_SSP0_TX_Mask |
374 | * -DMA_SSP0_TX_Mask |
371 | * -DMA_SSP1_RX_Mask |
375 | * -DMA_SSP1_RX_Mask |
372 | * -DMA_SSP1_TX_Mask |
376 | * -DMA_SSP1_TX_Mask |
373 | * Output : None. |
377 | * Output : None. |
374 | * Return : SET or RESET. |
378 | * Return : SET or RESET. |
375 | *******************************************************************************/ |
379 | *******************************************************************************/ |
376 | 380 | ||
377 | 381 | ||
378 | FlagStatus DMA_GetLSReq(u16 SRCReq) |
382 | FlagStatus DMA_GetLSReq(u16 SRCReq) |
379 | 383 | ||
380 | { /* Check for a specific source if it request a Last Single transfer . */ |
384 | { /* Check for a specific source if it request a Last Single transfer . */ |
381 | if ( (DMA->SLSRR & SRCReq)!= RESET ) |
385 | if ( (DMA->SLSRR & SRCReq)!= RESET ) |
382 | { |
386 | { |
383 | return SET; |
387 | return SET; |
384 | } |
388 | } |
385 | 389 | ||
386 | else |
390 | else |
387 | { |
391 | { |
388 | return RESET; |
392 | return RESET; |
389 | } |
393 | } |
390 | } |
394 | } |
391 | 395 | ||
392 | /******************************************************************************** |
396 | /******************************************************************************** |
393 | * Function Name : DMA_GetBReq |
397 | * Function Name : DMA_GetBReq |
394 | * Description : Check for a specific source if it request a Burst transfer . |
398 | * Description : Check for a specific source if it request a Burst transfer . |
395 | * Input : |
399 | * Input : |
396 | * -SRCReq:specifies the DMA Request Source. |
400 | * -SRCReq:specifies the DMA Request Source. |
397 | * This parameter can be: |
401 | * This parameter can be: |
398 | * -DMA_USB_RX_Mask |
402 | * -DMA_USB_RX_Mask |
399 | * -DMA_USB_TX_Mask |
403 | * -DMA_USB_TX_Mask |
400 | * -DMA_TIM0_Mask |
404 | * -DMA_TIM0_Mask |
401 | * -DMA_TIM1_Mask |
405 | * -DMA_TIM1_Mask |
402 | * -DMA_UART0_RX_Mask |
406 | * -DMA_UART0_RX_Mask |
403 | * -DMA_UART0_TX_Mask |
407 | * -DMA_UART0_TX_Mask |
404 | * -DMA_UART1_RX_Mask |
408 | * -DMA_UART1_RX_Mask |
405 | * -DMA_UART1_TX_Mask |
409 | * -DMA_UART1_TX_Mask |
406 | * -DMA_External_Req0_Mask |
410 | * -DMA_External_Req0_Mask |
407 | * -DMA_External_Req1_Mask |
411 | * -DMA_External_Req1_Mask |
408 | * -DMA_I2C0_Mask |
412 | * -DMA_I2C0_Mask |
409 | * -DMA_I2C1_Mask |
413 | * -DMA_I2C1_Mask |
410 | * -DMA_SSP0_RX_Mask |
414 | * -DMA_SSP0_RX_Mask |
411 | * -DMA_SSP0_TX_Mask |
415 | * -DMA_SSP0_TX_Mask |
412 | * -DMA_SSP1_RX_Mask |
416 | * -DMA_SSP1_RX_Mask |
413 | * -DMA_SSP1_TX_Mask |
417 | * -DMA_SSP1_TX_Mask |
414 | * Output : None. |
418 | * Output : None. |
415 | * Return : SET or RESET. |
419 | * Return : SET or RESET. |
416 | *******************************************************************************/ |
420 | *******************************************************************************/ |
417 | 421 | ||
418 | 422 | ||
419 | FlagStatus DMA_GetBReq(u16 SRCReq) |
423 | FlagStatus DMA_GetBReq(u16 SRCReq) |
420 | 424 | ||
421 | { /* Check for a specific source if it request a Burst transfer . */ |
425 | { /* Check for a specific source if it request a Burst transfer . */ |
422 | if (( DMA->SBRR & SRCReq ) != RESET ) |
426 | if (( DMA->SBRR & SRCReq ) != RESET ) |
423 | { |
427 | { |
424 | return SET; |
428 | return SET; |
425 | } |
429 | } |
426 | 430 | ||
427 | else |
431 | else |
428 | { |
432 | { |
429 | return RESET; |
433 | return RESET; |
430 | } |
434 | } |
431 | } |
435 | } |
432 | 436 | ||
433 | /******************************************************************************** |
437 | /******************************************************************************** |
434 | * Function Name : DMA_GetLSReq |
438 | * Function Name : DMA_GetLSReq |
435 | * Description : Check for a specific source if it request a Last Burst transfer . |
439 | * Description : Check for a specific source if it request a Last Burst transfer . |
436 | * Input : |
440 | * Input : |
437 | * Input : |
441 | * Input : |
438 | * - SRCReq:specifies the DMA Request Source. |
442 | * - SRCReq:specifies the DMA Request Source. |
439 | * This parameter can be: |
443 | * This parameter can be: |
440 | * -DMA_USB_RX_Mask |
444 | * -DMA_USB_RX_Mask |
441 | * -DMA_USB_TX_Mask |
445 | * -DMA_USB_TX_Mask |
442 | * -DMA_TIM0_Mask |
446 | * -DMA_TIM0_Mask |
443 | * -DMA_TIM1_Mask |
447 | * -DMA_TIM1_Mask |
444 | * -DMA_UART0_RX_Mask |
448 | * -DMA_UART0_RX_Mask |
445 | * -DMA_UART0_TX_Mask |
449 | * -DMA_UART0_TX_Mask |
446 | * -DMA_UART1_RX_Mask |
450 | * -DMA_UART1_RX_Mask |
447 | * -DMA_UART1_TX_Mask |
451 | * -DMA_UART1_TX_Mask |
448 | * -DMA_External_Req0_Mask |
452 | * -DMA_External_Req0_Mask |
449 | * -DMA_External_Req1_Mask |
453 | * -DMA_External_Req1_Mask |
450 | * -DMA_I2C0_Mask |
454 | * -DMA_I2C0_Mask |
451 | * -DMA_I2C1_Mask |
455 | * -DMA_I2C1_Mask |
452 | * -DMA_SSP0_RX_Mask |
456 | * -DMA_SSP0_RX_Mask |
453 | * -DMA_SSP0_TX_Mask |
457 | * -DMA_SSP0_TX_Mask |
454 | * -DMA_SSP1_RX_Mask |
458 | * -DMA_SSP1_RX_Mask |
455 | * -DMA_SSP1_TX_Mask |
459 | * -DMA_SSP1_TX_Mask |
456 | * Output : None. |
460 | * Output : None. |
457 | * Return : SET or RESET. |
461 | * Return : SET or RESET. |
458 | *******************************************************************************/ |
462 | *******************************************************************************/ |
459 | 463 | ||
460 | 464 | ||
461 | FlagStatus DMA_GetLBReq(u16 SRCReq) |
465 | FlagStatus DMA_GetLBReq(u16 SRCReq) |
462 | 466 | ||
463 | { /* Check for a specific source if it request a Last Burst transfer . */ |
467 | { /* Check for a specific source if it request a Last Burst transfer . */ |
464 | if ( ( DMA->SLBRR & SRCReq ) != RESET ) |
468 | if ( ( DMA->SLBRR & SRCReq ) != RESET ) |
465 | { |
469 | { |
466 | return SET; |
470 | return SET; |
467 | } |
471 | } |
468 | 472 | ||
469 | else |
473 | else |
470 | { |
474 | { |
471 | return RESET; |
475 | return RESET; |
472 | } |
476 | } |
473 | } |
477 | } |
474 | 478 | ||
475 | 479 | ||
476 | 480 | ||
477 | /******************************************************************************* |
481 | /******************************************************************************* |
478 | * Function Name : DMA_ChannelHalt |
482 | * Function Name : DMA_ChannelHalt |
479 | * Description : Enables DMA requests or ignore extra source DMA requests for |
483 | * Description : Enables DMA requests or ignore extra source DMA requests for |
480 | the specified channel. |
484 | the specified channel. |
481 | * Input : |
485 | * Input : |
482 | -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
486 | -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
483 | -NewState: new state of the specified DMA_Channelx mask interrupt. |
487 | -NewState: new state of the specified DMA_Channelx mask interrupt. |
484 | This parameter can be: ENABLE or DISABLE. |
488 | This parameter can be: ENABLE or DISABLE. |
485 | * Output : None. |
489 | * Output : None. |
486 | * Return : None. |
490 | * Return : None. |
487 | *******************************************************************************/ |
491 | *******************************************************************************/ |
488 | 492 | ||
489 | 493 | ||
490 | void DMA_ChannelHalt(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
494 | void DMA_ChannelHalt(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
491 | 495 | ||
492 | { |
496 | { |
493 | if (NewState==ENABLE) /* Enables DMA requests */ |
497 | if (NewState==ENABLE) /* Enables DMA requests */ |
494 | 498 | ||
495 | { |
499 | { |
496 | DMA_Channelx->CCNF |= DMA_HaltChannel ; |
500 | DMA_Channelx->CCNF |= DMA_HaltChannel ; |
497 | } |
501 | } |
498 | 502 | ||
499 | else /* Ignore extra source DMA request */ |
503 | else /* Ignore extra source DMA request */ |
500 | { |
504 | { |
501 | DMA_Channelx->CCNF &= ~ DMA_HaltChannel ; |
505 | DMA_Channelx->CCNF &= ~ DMA_HaltChannel ; |
502 | } |
506 | } |
503 | } |
507 | } |
504 | 508 | ||
505 | 509 | ||
506 | /******************************************************************************* |
510 | /******************************************************************************* |
507 | * Function Name : DMA_ChannelLockTrsf |
511 | * Function Name : DMA_ChannelLockTrsf |
508 | * Description : Enables or disables the Locked Transfers Feature for the specified DMA_Channelx |
512 | * Description : Enables or disables the Locked Transfers Feature for the specified DMA_Channelx |
509 | * Input : |
513 | * Input : |
510 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
514 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
511 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
515 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
512 | * This parameter can be: ENABLE or DISABLE. |
516 | * This parameter can be: ENABLE or DISABLE. |
513 | * Output : None. |
517 | * Output : None. |
514 | * Return : None. |
518 | * Return : None. |
515 | *******************************************************************************/ |
519 | *******************************************************************************/ |
516 | 520 | ||
517 | 521 | ||
518 | void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
522 | void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
519 | 523 | ||
520 | { |
524 | { |
521 | if (NewState==ENABLE) /* Locked transfers enabled on channel x */ |
525 | if (NewState==ENABLE) /* Locked transfers enabled on channel x */ |
522 | 526 | ||
523 | { |
527 | { |
524 | DMA_Channelx->CCNF |= DMA_LockChannel ; |
528 | DMA_Channelx->CCNF |= DMA_LockChannel ; |
525 | } |
529 | } |
526 | 530 | ||
527 | else /* Locked transfers disabled on channel xt */ |
531 | else /* Locked transfers disabled on channel xt */ |
528 | { |
532 | { |
529 | DMA_Channelx->CCNF &= ~ DMA_LockChannel; |
533 | DMA_Channelx->CCNF &= ~ DMA_LockChannel; |
530 | } |
534 | } |
531 | } |
535 | } |
532 | 536 | ||
533 | 537 | ||
534 | /******************************************************************************* |
538 | /******************************************************************************* |
535 | * Function Name : DMA_ChannelCache |
539 | * Function Name : DMA_ChannelCache |
536 | * Description : Enables or disables the cacheability Feature for the specified DMA_Channelx |
540 | * Description : Enables or disables the cacheability Feature for the specified DMA_Channelx |
537 | * Input : |
541 | * Input : |
538 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
542 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
539 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
543 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
540 | * This parameter can be: ENABLE or DISABLE. |
544 | * This parameter can be: ENABLE or DISABLE. |
541 | * Output : None. |
545 | * Output : None. |
542 | * Return : None. |
546 | * Return : None. |
543 | *******************************************************************************/ |
547 | *******************************************************************************/ |
544 | 548 | ||
545 | 549 | ||
546 | void DMA_ChannelCache (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
550 | void DMA_ChannelCache (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
547 | 551 | ||
548 | { |
552 | { |
549 | if (NewState==ENABLE) /* Cacheability Feature enabled on channelx */ |
553 | if (NewState==ENABLE) /* Cacheability Feature enabled on channelx */ |
550 | 554 | ||
551 | { |
555 | { |
552 | DMA_Channelx->CC |= DMA_CacheChannel ; |
556 | DMA_Channelx->CC |= DMA_CacheChannel ; |
553 | } |
557 | } |
554 | 558 | ||
555 | else /* Cacheability Feature disabled on channelx */ |
559 | else /* Cacheability Feature disabled on channelx */ |
556 | { |
560 | { |
557 | DMA_Channelx->CC &= ~ DMA_CacheChannel ; |
561 | DMA_Channelx->CC &= ~ DMA_CacheChannel ; |
558 | } |
562 | } |
559 | } |
563 | } |
560 | 564 | ||
561 | 565 | ||
562 | /******************************************************************************* |
566 | /******************************************************************************* |
563 | * Function Name : DMA_ChannelBuffering |
567 | * Function Name : DMA_ChannelBuffering |
564 | * Description : Enables or disables the Buffering Feature for the specified DMA_Channelx |
568 | * Description : Enables or disables the Buffering Feature for the specified DMA_Channelx |
565 | * Input : |
569 | * Input : |
566 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
570 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
567 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
571 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
568 | * This parameter can be: ENABLE or DISABLE. |
572 | * This parameter can be: ENABLE or DISABLE. |
569 | * Output : None. |
573 | * Output : None. |
570 | * Return : None. |
574 | * Return : None. |
571 | *******************************************************************************/ |
575 | *******************************************************************************/ |
572 | 576 | ||
573 | 577 | ||
574 | void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
578 | void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
575 | 579 | ||
576 | { |
580 | { |
577 | if (NewState==ENABLE) /* Cacheability Feature enabled on channel x */ |
581 | if (NewState==ENABLE) /* Cacheability Feature enabled on channel x */ |
578 | 582 | ||
579 | { |
583 | { |
580 | DMA_Channelx->CC |= DMA_BufferChannel ; |
584 | DMA_Channelx->CC |= DMA_BufferChannel ; |
581 | } |
585 | } |
582 | 586 | ||
583 | else /* Cacheability Feature disabled on channel xt */ |
587 | else /* Cacheability Feature disabled on channel xt */ |
584 | { |
588 | { |
585 | DMA_Channelx->CC &= ~ DMA_BufferChannel ; |
589 | DMA_Channelx->CC &= ~ DMA_BufferChannel ; |
586 | } |
590 | } |
587 | } |
591 | } |
588 | 592 | ||
589 | /******************************************************************************* |
593 | /******************************************************************************* |
590 | * Function Name : MA_ChannelProt0Mod |
594 | * Function Name : MA_ChannelProt0Mod |
591 | * Description : Sets The User or Privileged mode for the specified DMA_Channelx |
595 | * Description : Sets The User or Privileged mode for the specified DMA_Channelx |
592 | * Input : |
596 | * Input : |
593 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
597 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
594 | * -Prot0Mode: Specifies the Privileged mode Or the User mode. |
598 | * -Prot0Mode: Specifies the Privileged mode Or the User mode. |
595 | * This parameter can be: |
599 | * This parameter can be: |
596 | * - DMA_PrevilegedMode |
600 | * - DMA_PrevilegedMode |
597 | * - DMA_UserMode |
601 | * - DMA_UserMode |
598 | * |
602 | * |
599 | * |
603 | * |
600 | * Output : None. |
604 | * Output : None. |
601 | * Return : None. |
605 | * Return : None. |
602 | *******************************************************************************/ |
606 | *******************************************************************************/ |
603 | 607 | ||
604 | 608 | ||
605 | void DMA_ChannelProt0Mode (DMA_Channel_TypeDef * DMA_Channelx, u32 Prot0Mode) |
609 | void DMA_ChannelProt0Mode (DMA_Channel_TypeDef * DMA_Channelx, u32 Prot0Mode) |
606 | 610 | ||
607 | { |
611 | { |
608 | if (Prot0Mode==DMA_PrevilegedMode) /* Privileged mode */ |
612 | if (Prot0Mode==DMA_PrevilegedMode) /* Privileged mode */ |
609 | { |
613 | { |
610 | DMA_Channelx->CC |= DMA_PrevilegedMode ; |
614 | DMA_Channelx->CC |= DMA_PrevilegedMode ; |
611 | } |
615 | } |
612 | 616 | ||
613 | else /* User mode */ |
617 | else /* User mode */ |
614 | { |
618 | { |
615 | DMA_Channelx->CC &= DMA_UserMode ; |
619 | DMA_Channelx->CC &= DMA_UserMode ; |
616 | } |
620 | } |
617 | } |
621 | } |
618 | 622 | ||
619 | 623 | ||
620 | 624 | ||
621 | 625 | ||
622 | 626 | ||
623 | /******************************************************************************* |
627 | /******************************************************************************* |
624 | * Function Name : DMA_ChannelSRCIncConfig |
628 | * Function Name : DMA_ChannelSRCIncConfig |
625 | * Description : Enables or disables the Source address incrementation after each transfer for |
629 | * Description : Enables or disables the Source address incrementation after each transfer for |
626 | * the specified DMA_Channelx |
630 | * the specified DMA_Channelx |
627 | * Input : |
631 | * Input : |
628 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
632 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
629 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
633 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
630 | * This parameter can be: ENABLE or DISABLE. |
634 | * This parameter can be: ENABLE or DISABLE. |
631 | * Output : None. |
635 | * Output : None. |
632 | * Return : None. |
636 | * Return : None. |
633 | *******************************************************************************/ |
637 | *******************************************************************************/ |
634 | 638 | ||
635 | 639 | ||
636 | void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
640 | void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
637 | 641 | ||
638 | { |
642 | { |
639 | if (NewState==ENABLE) /* The Source address is incremented after each transfer */ |
643 | if (NewState==ENABLE) /* The Source address is incremented after each transfer */ |
640 | 644 | ||
641 | { |
645 | { |
642 | DMA_Channelx->CC |= DMA_ChannelSRCInc ; |
646 | DMA_Channelx->CC |= DMA_ChannelSRCInc ; |
643 | } |
647 | } |
644 | 648 | ||
645 | else /* The Source address is not incremented after each Transfer */ |
649 | else /* The Source address is not incremented after each Transfer */ |
646 | { |
650 | { |
647 | DMA_Channelx->CC &= ~ DMA_ChannelSRCInc ; |
651 | DMA_Channelx->CC &= ~ DMA_ChannelSRCInc ; |
648 | } |
652 | } |
649 | } |
653 | } |
650 | 654 | ||
651 | 655 | ||
652 | /******************************************************************************* |
656 | /******************************************************************************* |
653 | * Function Name : DMA_ChannelDESIncConfig |
657 | * Function Name : DMA_ChannelDESIncConfig |
654 | * Description : Enables or disables the Destination address incrementation after each transfer for |
658 | * Description : Enables or disables the Destination address incrementation after each transfer for |
655 | * the specified DMA_Channelx |
659 | * the specified DMA_Channelx |
656 | * Input : |
660 | * Input : |
657 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
661 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
658 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
662 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
659 | * This parameter can be: ENABLE or DISABLE. |
663 | * This parameter can be: ENABLE or DISABLE. |
660 | * Output : None. |
664 | * Output : None. |
661 | * Return : None. |
665 | * Return : None. |
662 | *******************************************************************************/ |
666 | *******************************************************************************/ |
663 | 667 | ||
664 | 668 | ||
665 | void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
669 | void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
666 | 670 | ||
667 | { |
671 | { |
668 | if (NewState==ENABLE) /* The Destination address is incremented after each transfer */ |
672 | if (NewState==ENABLE) /* The Destination address is incremented after each transfer */ |
669 | 673 | ||
670 | { |
674 | { |
671 | DMA_Channelx->CC |= DMA_ChannelDESInc ; |
675 | DMA_Channelx->CC |= DMA_ChannelDESInc ; |
672 | } |
676 | } |
673 | 677 | ||
674 | else /* The Destination address is not incremented after each Transfer */ |
678 | else /* The Destination address is not incremented after each Transfer */ |
675 | { |
679 | { |
676 | DMA_Channelx->CC &= ~ DMA_ChannelDESInc ; |
680 | DMA_Channelx->CC &= ~ DMA_ChannelDESInc ; |
677 | } |
681 | } |
678 | } |
682 | } |
679 | 683 | ||
680 | 684 | ||
681 | 685 | ||
682 | /******************************************************************************** |
686 | /******************************************************************************** |
683 | * Function Name : DMA_GetChannelStatus |
687 | * Function Name : DMA_GetChannelStatus |
684 | * Description : Checks the status of DMA channelx ( Enabled or Disabled). |
688 | * Description : Checks the status of DMA channelx ( Enabled or Disabled). |
685 | * - ChannelIndx:specifies the DMA Channel to be checked. |
689 | * - ChannelIndx:specifies the DMA Channel to be checked. |
686 | * This parameter can be: |
690 | * This parameter can be: |
687 | * - Channel0 |
691 | * - Channel0 |
688 | * - Channel1 |
692 | * - Channel1 |
689 | * - Channel2 |
693 | * - Channel2 |
690 | * - Channel3 |
694 | * - Channel3 |
691 | * - Channel4 |
695 | * - Channel4 |
692 | * - Channel5 |
696 | * - Channel5 |
693 | * - Channel6 |
697 | * - Channel6 |
694 | * - Channel7 |
698 | * - Channel7 |
695 | * Output : None. |
699 | * Output : None. |
696 | * |
700 | * |
697 | * Return : SET or RESET. |
701 | * Return : SET or RESET. |
698 | *******************************************************************************/ |
702 | *******************************************************************************/ |
699 | 703 | ||
700 | 704 | ||
701 | FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ) |
705 | FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ) |
702 | 706 | ||
703 | { |
707 | { |
704 | 708 | ||
705 | if ( ( DMA->ENCSR & (1 << ChannelIndx )) != RESET ) |
709 | if ( ( DMA->ENCSR & (1 << ChannelIndx )) != RESET ) |
706 | { |
710 | { |
707 | return SET; /* Channelx Enabled */ |
711 | return SET; /* Channelx Enabled */ |
708 | } |
712 | } |
709 | 713 | ||
710 | else |
714 | else |
711 | 715 | ||
712 | { |
716 | { |
713 | 717 | ||
714 | return RESET; /* Channelx Disabled */ |
718 | return RESET; /* Channelx Disabled */ |
715 | 719 | ||
716 | } |
720 | } |
717 | 721 | ||
718 | } |
722 | } |
719 | 723 | ||
720 | 724 | ||
721 | 725 | ||
722 | /******************************************************************************** |
726 | /******************************************************************************** |
723 | * Function Name : DMA_GetITStatus |
727 | * Function Name : DMA_GetITStatus |
724 | * Description : Checks the status of Terminal Count and Error interrupts request after and before Masking. |
728 | * Description : Checks the status of Terminal Count and Error interrupts request after and before Masking. |
725 | * Input : |
729 | * Input : |
726 | * - ChannelIndx:specifies the DMA Channel to be checked. |
730 | * - ChannelIndx:specifies the DMA Channel to be checked. |
727 | * This parameter can be: |
731 | * This parameter can be: |
728 | * - Channel0 |
732 | * - Channel0 |
729 | * - Channel1 |
733 | * - Channel1 |
730 | * - Channel2 |
734 | * - Channel2 |
731 | * - Channel3 |
735 | * - Channel3 |
732 | * - Channel4 |
736 | * - Channel4 |
733 | * - Channel5 |
737 | * - Channel5 |
734 | * - Channel6 |
738 | * - Channel6 |
735 | * - Channel7 |
739 | * - Channel7 |
736 | * |
740 | * |
737 | *. - DMA_ITReq: specifies the DMA interrupt request status to be checked. |
741 | *. - DMA_ITReq: specifies the DMA interrupt request status to be checked. |
738 | * This parameter can be: |
742 | * This parameter can be: |
739 | * |
743 | * |
740 | * - DMA_IS |
744 | * - DMA_IS |
741 | * - DMA_TCS |
745 | * - DMA_TCS |
742 | * - DMA_ES |
746 | * - DMA_ES |
743 | * - DMA_TCRS |
747 | * - DMA_TCRS |
744 | * - DMA_ERS. |
748 | * - DMA_ERS. |
745 | * |
749 | * |
746 | * Output : None. |
750 | * Output : None. |
747 | * |
751 | * |
748 | * Return : SET or RESET. |
752 | * Return : SET or RESET. |
749 | *******************************************************************************/ |
753 | *******************************************************************************/ |
750 | 754 | ||
751 | 755 | ||
752 | ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq) |
756 | ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq) |
753 | 757 | ||
754 | { |
758 | { |
755 | u32 DMAReg = 0; |
759 | u32 DMAReg = 0; |
756 | 760 | ||
757 | switch(DMA_ITReq) |
761 | switch(DMA_ITReq) |
758 | 762 | ||
759 | { |
763 | { |
760 | 764 | ||
761 | case (DMA_IS): /*The status of the interrupts after masking : logical or of all Interrupts after Masking*/ |
765 | case (DMA_IS): /*The status of the interrupts after masking : logical or of all Interrupts after Masking*/ |
762 | DMAReg = DMA->ISR; |
766 | DMAReg = DMA->ISR; |
763 | break; |
767 | break; |
764 | 768 | ||
765 | 769 | ||
766 | 770 | ||
767 | case (DMA_TCS): /* The status of the Terminal count request after masking */ |
771 | case (DMA_TCS): /* The status of the Terminal count request after masking */ |
768 | DMAReg = DMA->TCISR; |
772 | DMAReg = DMA->TCISR; |
769 | break; |
773 | break; |
770 | 774 | ||
771 | 775 | ||
772 | case (DMA_ES): /* The status of the error request after masking */ |
776 | case (DMA_ES): /* The status of the error request after masking */ |
773 | DMAReg = DMA->EISR; |
777 | DMAReg = DMA->EISR; |
774 | break; |
778 | break; |
775 | 779 | ||
776 | 780 | ||
777 | case (DMA_TCRS): /* Indicates if the DMA channel is requesting a transfer complete (terminal count Interrupt) prior to masking or Not. */ |
781 | case (DMA_TCRS): /* Indicates if the DMA channel is requesting a transfer complete (terminal count Interrupt) prior to masking or Not. */ |
778 | DMAReg = DMA->TCRISR; |
782 | DMAReg = DMA->TCRISR; |
779 | break; |
783 | break; |
780 | 784 | ||
781 | case (DMA_ERS): /* Indicates if the DMA channel is requesting an Error Interrupt prior to masking or Not. */ |
785 | case (DMA_ERS): /* Indicates if the DMA channel is requesting an Error Interrupt prior to masking or Not. */ |
782 | DMAReg = DMA->ERISR; |
786 | DMAReg = DMA->ERISR; |
783 | break; |
787 | break; |
784 | 788 | ||
785 | 789 | ||
786 | } |
790 | } |
787 | 791 | ||
788 | if((DMAReg &(1 << ChannelIndx )) != RESET ) |
792 | if((DMAReg &(1 << ChannelIndx )) != RESET ) |
789 | 793 | ||
790 | { |
794 | { |
791 | return SET; |
795 | return SET; |
792 | } |
796 | } |
793 | 797 | ||
794 | else |
798 | else |
795 | 799 | ||
796 | { |
800 | { |
797 | 801 | ||
798 | return RESET; |
802 | return RESET; |
799 | 803 | ||
800 | 804 | ||
801 | } |
805 | } |
802 | 806 | ||
803 | } |
807 | } |
804 | 808 | ||
805 | 809 | ||
806 | /******************************************************************************** |
810 | /******************************************************************************** |
807 | * Function Name : DMA_ClearIT |
811 | * Function Name : DMA_ClearIT |
808 | * Description : Clears The Interrupt pending bits for termnal count or Error interrupts for a specified DMA Channel. |
812 | * Description : Clears The Interrupt pending bits for termnal count or Error interrupts for a specified DMA Channel. |
809 | * - ChannelIndx:specifies the DMA Channel to be checked. |
813 | * - ChannelIndx:specifies the DMA Channel to be checked. |
810 | * This parameter can be: |
814 | * This parameter can be: |
811 | * - Channel0 |
815 | * - Channel0 |
812 | * - Channel1 |
816 | * - Channel1 |
813 | * - Channel2 |
817 | * - Channel2 |
814 | * - Channel3 |
818 | * - Channel3 |
815 | * - Channel4 |
819 | * - Channel4 |
816 | * - Channel5 |
820 | * - Channel5 |
817 | * - Channel6 |
821 | * - Channel6 |
818 | * - Channel7 |
822 | * - Channel7 |
819 | * - DMA_ITClr : Specifies the DMA interrupt pending to be cleared. |
823 | * - DMA_ITClr : Specifies the DMA interrupt pending to be cleared. |
820 | *. This parameter can be: |
824 | *. This parameter can be: |
821 | * - DMA_TCC |
825 | * - DMA_TCC |
822 | * - DMA_EC. |
826 | * - DMA_EC. |
823 | * |
827 | * |
824 | * Output : None. |
828 | * Output : None. |
825 | 829 | ||
826 | * Return : SET or RESET. |
830 | * Return : SET or RESET. |
827 | *******************************************************************************/ |
831 | *******************************************************************************/ |
828 | 832 | ||
829 | 833 | ||
830 | void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr) |
834 | void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr) |
831 | 835 | ||
832 | { |
836 | { |
833 | 837 | ||
834 | 838 | ||
835 | switch(DMA_ITClr) |
839 | switch(DMA_ITClr) |
836 | 840 | ||
837 | { |
841 | { |
838 | 842 | ||
839 | case (DMA_TCC): /* Clear The status of the Terminal count interrupt on the corresponding channel.*/ |
843 | case (DMA_TCC): /* Clear The status of the Terminal count interrupt on the corresponding channel.*/ |
840 | DMA->TCICR |=(1 << ChannelIndx ); |
844 | DMA->TCICR |=(1 << ChannelIndx ); |
841 | break; |
845 | break; |
842 | 846 | ||
843 | 847 | ||
844 | 848 | ||
845 | case (DMA_EC): /* Clear The status of the error interrupt on the corresponding channel.*/ |
849 | case (DMA_EC): /* Clear The status of the error interrupt on the corresponding channel.*/ |
846 | DMA->EICR |=(1 << ChannelIndx ); |
850 | DMA->EICR |=(1 << ChannelIndx ); |
847 | break; |
851 | break; |
848 | 852 | ||
849 | 853 | ||
850 | 854 | ||
851 | } |
855 | } |
852 | 856 | ||
853 | 857 | ||
854 | 858 | ||
855 | } |
859 | } |
856 | 860 | ||
857 | 861 | ||
858 | /******************************************************************************* |
862 | /******************************************************************************* |
859 | * Function Name : DMA_Cmd(FunctionalState NewState) |
863 | * Function Name : DMA_Cmd(FunctionalState NewState) |
860 | * Description : Enables or disables the DMA peripheral. |
864 | * Description : Enables or disables the DMA peripheral. |
861 | * |
865 | * |
862 | * Input : |
866 | * Input : |
863 | * -NewState: new state of the DMA. |
867 | * -NewState: new state of the DMA. |
864 | * This parameter can be: ENABLE or DISABLE. |
868 | * This parameter can be: ENABLE or DISABLE. |
865 | * Output : None. |
869 | * Output : None. |
866 | * Return : None. |
870 | * Return : None. |
867 | *******************************************************************************/ |
871 | *******************************************************************************/ |
868 | 872 | ||
869 | 873 | ||
870 | void DMA_Cmd(FunctionalState NewState) |
874 | void DMA_Cmd(FunctionalState NewState) |
871 | 875 | ||
872 | { |
876 | { |
873 | if (NewState==ENABLE) /* ENABLE the DMA peripheral */ |
877 | if (NewState==ENABLE) /* ENABLE the DMA peripheral */ |
874 | 878 | ||
875 | { |
879 | { |
876 | DMA-> CNFR |= DMA_Enable ; |
880 | DMA-> CNFR |= DMA_Enable ; |
877 | } |
881 | } |
878 | 882 | ||
879 | else /* DISABLE the DMA peripheral */ |
883 | else /* DISABLE the DMA peripheral */ |
880 | { |
884 | { |
881 | DMA-> CNFR &= ~ DMA_Enable ; |
885 | DMA-> CNFR &= ~ DMA_Enable ; |
882 | } |
886 | } |
883 | } |
887 | } |
884 | 888 | ||
885 | 889 | ||
886 | 890 | ||
887 | /******************************************************************************* |
891 | /******************************************************************************* |
888 | * Function Name : DMA_ChannelCmd |
892 | * Function Name : DMA_ChannelCmd |
889 | * Description : Enables or disables the specified DMA_Channelx |
893 | * Description : Enables or disables the specified DMA_Channelx |
890 | * |
894 | * |
891 | * Input : |
895 | * Input : |
892 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
896 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
893 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
897 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
894 | * This parameter can be: ENABLE or DISABLE. |
898 | * This parameter can be: ENABLE or DISABLE. |
895 | * Output : None. |
899 | * Output : None. |
896 | * Return : None. |
900 | * Return : None. |
897 | *******************************************************************************/ |
901 | *******************************************************************************/ |
898 | 902 | ||
899 | 903 | ||
900 | void DMA_ChannelCmd (DMA_Channel_TypeDef *DMA_Channelx,FunctionalState NewState) |
904 | void DMA_ChannelCmd (DMA_Channel_TypeDef *DMA_Channelx,FunctionalState NewState) |
901 | 905 | ||
902 | { |
906 | { |
903 | if (NewState==ENABLE) /* Enable The Channelx */ |
907 | if (NewState==ENABLE) /* Enable The Channelx */ |
904 | 908 | ||
905 | { |
909 | { |
906 | DMA_Channelx->CCNF |= DMA_ChannelEnable ; |
910 | DMA_Channelx->CCNF |= DMA_ChannelEnable ; |
907 | } |
911 | } |
908 | 912 | ||
909 | else /* Disable The Channelx */ |
913 | else /* Disable The Channelx */ |
910 | { |
914 | { |
911 | DMA_Channelx-> CCNF &= ~ DMA_ChannelEnable ; |
915 | DMA_Channelx-> CCNF &= ~ DMA_ChannelEnable ; |
912 | } |
916 | } |
913 | } |
917 | } |
914 | 918 | ||
915 | 919 | ||
916 | 920 | ||
917 | /******************************************************************************** |
921 | /******************************************************************************** |
918 | * Function Name : DMA_GetChannelActiveStatus |
922 | * Function Name : DMA_GetChannelActiveStatus |
919 | * Description : Checks The DMA_Channelx FIFO if it has data or not. |
923 | * Description : Checks The DMA_Channelx FIFO if it has data or not. |
920 | * Input : |
924 | * Input : |
921 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
925 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
922 | * |
926 | * |
923 | * |
927 | * |
924 | * Output : None. |
928 | * Output : None. |
925 | * |
929 | * |
926 | * Return : SET or RESET. |
930 | * Return : SET or RESET. |
927 | *******************************************************************************/ |
931 | *******************************************************************************/ |
928 | 932 | ||
929 | 933 | ||
930 | FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx ) |
934 | FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx ) |
931 | 935 | ||
932 | { |
936 | { |
933 | 937 | ||
934 | if ( ( DMA_Channelx->CCNF & DMA_ChannelActive) != RESET ) |
938 | if ( ( DMA_Channelx->CCNF & DMA_ChannelActive) != RESET ) |
935 | { |
939 | { |
936 | return SET; /* The DMA_Channelx FIFO has data */ |
940 | return SET; /* The DMA_Channelx FIFO has data */ |
937 | } |
941 | } |
938 | 942 | ||
939 | else |
943 | else |
940 | 944 | ||
941 | { |
945 | { |
942 | 946 | ||
943 | return RESET; /* No data in the DMA_Channelx FIFO */ |
947 | return RESET; /* No data in the DMA_Channelx FIFO */ |
944 | 948 | ||
945 | 949 | ||
946 | } |
950 | } |
947 | 951 | ||
948 | } |
952 | } |
949 | 953 | ||
950 | 954 | ||
951 | /******************************************************************************** |
955 | /******************************************************************************** |
952 | * Function Name : DMA_DeInit |
956 | * Function Name : DMA_DeInit |
953 | * Description : Initializes the DMA peripheral registers to their default reset values. |
957 | * Description : Initializes the DMA peripheral registers to their default reset values. |
954 | * |
958 | * |
955 | * |
959 | * |
956 | * Input : None |
960 | * Input : None |
957 | * |
961 | * |
958 | * Output : None. |
962 | * Output : None. |
959 | * |
963 | * |
960 | * Called Functions: |
964 | * Called Functions: |
961 | * |
965 | * |
962 | * - SCU_AHBPeriphReset: Function defined in the System clock Unit "scu.c". |
966 | * - SCU_AHBPeriphReset: Function defined in the System clock Unit "scu.c". |
963 | * |
967 | * |
964 | * |
968 | * |
965 | * Return : None |
969 | * Return : None |
966 | *******************************************************************************/ |
970 | *******************************************************************************/ |
967 | 971 | ||
968 | 972 | ||
969 | void DMA_DeInit(void) |
973 | void DMA_DeInit(void) |
970 | 974 | ||
971 | { |
975 | { |
972 | 976 | ||
973 | SCU_AHBPeriphReset(__DMA, ENABLE); /*DMA peripheral is under Reset " Reset on"*/ |
977 | SCU_AHBPeriphReset(__DMA, ENABLE); /*DMA peripheral is under Reset " Reset on"*/ |
974 | SCU_AHBPeriphReset(__DMA, DISABLE); /*DMA peripheral Reset off*/ |
978 | SCU_AHBPeriphReset(__DMA, DISABLE); /*DMA peripheral Reset off*/ |
975 | } |
979 | } |
976 | 980 | ||
977 | 981 | ||
978 | 982 | ||
979 | /******************************************************************************** |
983 | /******************************************************************************** |
980 | * Function Name : DMA_StructInit |
984 | * Function Name : DMA_StructInit |
981 | * Description : Fills each DMA_InitStruct member with its reset value. |
985 | * Description : Fills each DMA_InitStruct member with its reset value. |
982 | * Input : |
986 | * Input : |
983 | * -DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will be initialized. |
987 | * -DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will be initialized. |
984 | * |
988 | * |
985 | * Output : None. |
989 | * Output : None. |
986 | * |
990 | * |
987 | * Return : None |
991 | * Return : None |
988 | *******************************************************************************/ |
992 | *******************************************************************************/ |
989 | 993 | ||
990 | 994 | ||
991 | void DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct) |
995 | void DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct) |
992 | 996 | ||
993 | { |
997 | { |
994 | 998 | ||
995 | /* Initialize The current source address */ |
999 | /* Initialize The current source address */ |
996 | DMA_InitStruct-> DMA_Channel_SrcAdd =0x0000000; |
1000 | DMA_InitStruct-> DMA_Channel_SrcAdd =0x0000000; |
997 | 1001 | ||
998 | 1002 | ||
999 | /* Initialize The current Destination address */ |
1003 | /* Initialize The current Destination address */ |
1000 | DMA_InitStruct->DMA_Channel_DesAdd=0x00000000; |
1004 | DMA_InitStruct->DMA_Channel_DesAdd=0x00000000; |
1001 | 1005 | ||
1002 | 1006 | ||
1003 | 1007 | ||
1004 | /* Initialize The Linked List Items */ |
1008 | /* Initialize The Linked List Items */ |
1005 | DMA_InitStruct->DMA_Channel_LLstItm=0x00000000 ; |
1009 | DMA_InitStruct->DMA_Channel_LLstItm=0x00000000 ; |
1006 | 1010 | ||
1007 | 1011 | ||
1008 | 1012 | ||
1009 | /* Initialize The Destination width */ |
1013 | /* Initialize The Destination width */ |
1010 | DMA_InitStruct->DMA_Channel_DesWidth= DMA_DesWidth_Byte; |
1014 | DMA_InitStruct->DMA_Channel_DesWidth= DMA_DesWidth_Byte; |
1011 | 1015 | ||
1012 | 1016 | ||
1013 | 1017 | ||
1014 | /* Initialize The source width */ |
1018 | /* Initialize The source width */ |
1015 | DMA_InitStruct->DMA_Channel_SrcWidth= DMA_SrcWidth_Byte; |
1019 | DMA_InitStruct->DMA_Channel_SrcWidth= DMA_SrcWidth_Byte; |
1016 | 1020 | ||
1017 | 1021 | ||
1018 | /* Initialize The Burst Size for the Destination */ |
1022 | /* Initialize The Burst Size for the Destination */ |
1019 | DMA_InitStruct->DMA_Channel_DesBstSize= DMA_DesBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the Destination width */ |
1023 | DMA_InitStruct->DMA_Channel_DesBstSize= DMA_DesBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the Destination width */ |
1020 | 1024 | ||
1021 | 1025 | ||
1022 | 1026 | ||
1023 | /* Initialize The Burst Size for the Source*/ |
1027 | /* Initialize The Burst Size for the Source*/ |
1024 | DMA_InitStruct->DMA_Channel_SrcBstSize= DMA_SrcBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the source width */ |
1028 | DMA_InitStruct->DMA_Channel_SrcBstSize= DMA_SrcBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the source width */ |
1025 | 1029 | ||
1026 | /* Initialize The Flow control and transfer type for the DMA transfer */ |
1030 | /* Initialize The Flow control and transfer type for the DMA transfer */ |
1027 | DMA_InitStruct->DMA_Channel_FlowCntrl=DMA_FlowCntrlt0_DMA; /* memory to memory transfer with DMA as flow controller */ |
1031 | DMA_InitStruct->DMA_Channel_FlowCntrl=DMA_FlowCntrlt0_DMA; /* memory to memory transfer with DMA as flow controller */ |
1028 | 1032 | ||
1029 | 1033 | ||
1030 | /* Initialize The Transfer Size */ |
1034 | /* Initialize The Transfer Size */ |
1031 | DMA_InitStruct->DMA_Channel_TrsfSize =0x00; |
1035 | DMA_InitStruct->DMA_Channel_TrsfSize =0x00; |
1032 | 1036 | ||
1033 | 1037 | ||
1034 | 1038 | ||
1035 | /* Initialize the DMA source request peripheral :"This field is ignored if the source of the transfer is from memory" */ |
1039 | /* Initialize the DMA source request peripheral :"This field is ignored if the source of the transfer is from memory" */ |
1036 | DMA_InitStruct->DMA_Channel_Src =0x00; |
1040 | DMA_InitStruct->DMA_Channel_Src =0x00; |
1037 | 1041 | ||
1038 | 1042 | ||
1039 | 1043 | ||
1040 | /* Initialize the DMA Destination request peripheral :"This field is ignored if the destination of the transfer is to memory.*/ |
1044 | /* Initialize the DMA Destination request peripheral :"This field is ignored if the destination of the transfer is to memory.*/ |
1041 | 1045 | ||
1042 | DMA_InitStruct->DMA_Channel_Des=0x00; |
1046 | DMA_InitStruct->DMA_Channel_Des=0x00; |
1043 | 1047 | ||
1044 | 1048 | ||
1045 | } |
1049 | } |
1046 | 1050 | ||
1047 | 1051 | ||
1048 | 1052 | ||
1049 | 1053 | ||
1050 | /******************************************************************************** |
1054 | /******************************************************************************** |
1051 | * Function Name : DMA_Init |
1055 | * Function Name : DMA_Init |
1052 | * Description : Initializes the DMA_Channelx according to the specified parameters |
1056 | * Description : Initializes the DMA_Channelx according to the specified parameters |
1053 | * in the DMA_InitStruct . |
1057 | * in the DMA_InitStruct . |
1054 | * |
1058 | * |
1055 | * Input : |
1059 | * Input : |
1056 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
1060 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
1057 | * -DMA_InitStruct: pointer to a DMA_InitTypeDef structure |
1061 | * -DMA_InitStruct: pointer to a DMA_InitTypeDef structure |
1058 | * ( Structure Config to be load in DMA Registers). . |
1062 | * ( Structure Config to be load in DMA Registers). . |
1059 | * |
1063 | * |
1060 | * Output : None. |
1064 | * Output : None. |
1061 | * |
1065 | * |
1062 | * Return : None |
1066 | * Return : None |
1063 | *******************************************************************************/ |
1067 | *******************************************************************************/ |
1064 | 1068 | ||
1065 | 1069 | ||
1066 | void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct) |
1070 | void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct) |
1067 | 1071 | ||
1068 | { |
1072 | { |
1069 | 1073 | ||
1070 | 1074 | ||
1071 | 1075 | ||
1072 | /* Select the DMA source peripheral request */ |
1076 | /* Select the DMA source peripheral request */ |
1073 | DMA_Channelx->CCNF &= SRC_Mask; |
1077 | DMA_Channelx->CCNF &= SRC_Mask; |
1074 | DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Src; |
1078 | DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Src; |
1075 | 1079 | ||
1076 | 1080 | ||
1077 | /* Select the flow controller and the transfer type */ |
1081 | /* Select the flow controller and the transfer type */ |
1078 | DMA_Channelx->CCNF &= DMA_FlowCntrl_Mask; |
1082 | DMA_Channelx->CCNF &= DMA_FlowCntrl_Mask; |
1079 | DMA_Channelx->CCNF |=DMA_InitStruct->DMA_Channel_FlowCntrl; |
1083 | DMA_Channelx->CCNF |=DMA_InitStruct->DMA_Channel_FlowCntrl; |
1080 | 1084 | ||
1081 | 1085 | ||
1082 | /* Select the DMA Destination peripheral request*/ |
1086 | /* Select the DMA Destination peripheral request*/ |
1083 | DMA_Channelx->CCNF &= DES_Mask; |
1087 | DMA_Channelx->CCNF &= DES_Mask; |
1084 | DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Des; |
1088 | DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Des; |
1085 | 1089 | ||
1086 | /* Set the source address */ |
1090 | /* Set the source address */ |
1087 | DMA_Channelx->SRC = DMA_InitStruct-> DMA_Channel_SrcAdd ; |
1091 | DMA_Channelx->SRC = DMA_InitStruct-> DMA_Channel_SrcAdd ; |
1088 | 1092 | ||
1089 | 1093 | ||
1090 | /* Set the destination address */ |
1094 | /* Set the destination address */ |
1091 | 1095 | ||
1092 | DMA_Channelx->DES = DMA_InitStruct->DMA_Channel_DesAdd ; |
1096 | DMA_Channelx->DES = DMA_InitStruct->DMA_Channel_DesAdd ; |
1093 | 1097 | ||
1094 | 1098 | ||
1095 | 1099 | ||
1096 | /* Set the linked list Items address */ |
1100 | /* Set the linked list Items address */ |
1097 | DMA_Channelx->LLI = DMA_InitStruct->DMA_Channel_LLstItm ; |
1101 | DMA_Channelx->LLI = DMA_InitStruct->DMA_Channel_LLstItm ; |
1098 | 1102 | ||
1099 | 1103 | ||
1100 | /* Set The Destination width */ |
1104 | /* Set The Destination width */ |
1101 | DMA_Channelx->CC &= DMA_Width_DES_MASK; |
1105 | DMA_Channelx->CC &= DMA_Width_DES_MASK; |
1102 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesWidth; |
1106 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesWidth; |
1103 | 1107 | ||
1104 | 1108 | ||
1105 | /* Set The Source width */ |
1109 | /* Set The Source width */ |
1106 | DMA_Channelx->CC &= DMA_Width_SRC_MASK; |
1110 | DMA_Channelx->CC &= DMA_Width_SRC_MASK; |
1107 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_SrcWidth; |
1111 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_SrcWidth; |
1108 | 1112 | ||
1109 | /* Set The Burst Size for the Destination */ |
1113 | /* Set The Burst Size for the Destination */ |
1110 | DMA_Channelx->CC &= DMA_Bst_DES_MASK; |
1114 | DMA_Channelx->CC &= DMA_Bst_DES_MASK; |
1111 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesBstSize; |
1115 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesBstSize; |
1112 | 1116 | ||
1113 | /* Set The Burst Size for the Source */ |
1117 | /* Set The Burst Size for the Source */ |
1114 | DMA_Channelx->CC &= DMA_Bst_SRC_MASK; |
1118 | DMA_Channelx->CC &= DMA_Bst_SRC_MASK; |
1115 | DMA_Channelx->CC |=DMA_InitStruct->DMA_Channel_SrcBstSize; |
1119 | DMA_Channelx->CC |=DMA_InitStruct->DMA_Channel_SrcBstSize; |
1116 | 1120 | ||
1117 | 1121 | ||
1118 | /* Initialize The Transfer Size for the Source */ |
1122 | /* Initialize The Transfer Size for the Source */ |
1119 | DMA_Channelx->CC &= DMA_TrsfSisze_Mask; |
1123 | DMA_Channelx->CC &= DMA_TrsfSisze_Mask; |
1120 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_TrsfSize; |
1124 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_TrsfSize; |
1121 | 1125 | ||
1122 | 1126 | ||
1123 | } |
1127 | } |
1124 | 1128 | ||
- | 1129 | ||
- | 1130 | /******************************************************************************** |
|
- | 1131 | * Function Name : DMA_LLI_CCR_Init |
|
- | 1132 | * Description : Return linked list's control word according to the specified |
|
- | 1133 | * parameters in the LLI_CCR_InitStruct . |
|
- | 1134 | * |
|
- | 1135 | * Input : -LLI_CCR_InitStruct: pointer to a LLI_CCR_InitTypeDef structure |
|
- | 1136 | * ( Structure Config to be load in DMA Registers). . |
|
- | 1137 | * |
|
- | 1138 | * Output : None. |
|
- | 1139 | * |
|
- | 1140 | * Return : Control word |
|
- | 1141 | *******************************************************************************/ |
|
- | 1142 | ||
- | 1143 | ||
- | 1144 | u32 DMA_LLI_CCR_Init(LLI_CCR_InitTypeDef * LLI_CCR_InitStruct) |
|
- | 1145 | ||
- | 1146 | { |
|
- | 1147 | u32 CC=0; |
|
- | 1148 | /* Set The Destination width */ |
|
- | 1149 | CC &= DMA_Width_DES_MASK; |
|
- | 1150 | CC |= LLI_CCR_InitStruct->LLI_DesWidth; |
|
- | 1151 | ||
- | 1152 | /* Set The Source width */ |
|
- | 1153 | CC &= DMA_Width_SRC_MASK; |
|
- | 1154 | CC |= LLI_CCR_InitStruct->LLI_SrcWidth; |
|
- | 1155 | ||
- | 1156 | /* Set The Burst Size for the Destination */ |
|
- | 1157 | CC &= DMA_Bst_DES_MASK; |
|
- | 1158 | CC |= LLI_CCR_InitStruct->LLI_DesBstSize; |
|
- | 1159 | ||
- | 1160 | /* Set The Burst Size for the Source */ |
|
- | 1161 | CC &= DMA_Bst_SRC_MASK; |
|
- | 1162 | CC |= LLI_CCR_InitStruct->LLI_SrcBstSize; |
|
- | 1163 | ||
- | 1164 | /* Initialize The Transfer Size for the Source */ |
|
- | 1165 | CC &= DMA_TrsfSisze_Mask; |
|
- | 1166 | CC |= LLI_CCR_InitStruct->LLI_TrsfSize; |
|
- | 1167 | ||
- | 1168 | /* Enable or disable source increment*/ |
|
- | 1169 | CC &= DMA_SrcIncrement_MASK ; |
|
- | 1170 | CC |= LLI_CCR_InitStruct->LLI_SrcIncrement; |
|
- | 1171 | ||
- | 1172 | /* Enable or disable destination increment*/ |
|
- | 1173 | CC &= DMA_DesIncrement_MASK ; |
|
- | 1174 | CC |= LLI_CCR_InitStruct->LLI_DesIncrement; |
|
- | 1175 | ||
- | 1176 | /* Enable or disable cacheable access*/ |
|
- | 1177 | CC &= DMA_CacheableAccess_MASK; |
|
- | 1178 | CC |= LLI_CCR_InitStruct->LLI_PROT0; |
|
- | 1179 | ||
- | 1180 | /* Enable or disable bufferable access*/ |
|
- | 1181 | CC &= DMA_BufferableAccess_MASK; |
|
- | 1182 | CC |= LLI_CCR_InitStruct->LLI_PROT1; |
|
- | 1183 | ||
- | 1184 | /* Enable or disablePrivileged mode*/ |
|
- | 1185 | CC &= DMA_PrivilegedAccess_MASK; |
|
- | 1186 | CC |= LLI_CCR_InitStruct->LLI_PROT2; |
|
- | 1187 | ||
- | 1188 | /* Enable or disable Terminal count interrupt*/ |
|
- | 1189 | CC &= DMA_TCInterrupt_MASK ; |
|
- | 1190 | CC |= LLI_CCR_InitStruct->LLI_TCInterrupt; |
|
- | 1191 | return CC; |
|
- | 1192 | } |
|
1125 | 1193 | ||
1126 | /******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ |
1194 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ |
1127 | 1195 |