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1 | /*############################################################################ |
1 | /*############################################################################ |
2 | ############################################################################*/ |
2 | ############################################################################*/ |
3 | 3 | ||
4 | #ifndef BLMC_H_ |
4 | #ifndef BLMC_H_ |
5 | #define BLMC_H_ |
5 | #define BLMC_H_ |
6 | 6 | ||
7 | extern volatile unsigned char Phase; |
7 | extern volatile unsigned char Phase; |
8 | extern volatile unsigned char ShadowTCCR1A; |
8 | extern volatile unsigned char ShadowTCCR1A; |
9 | extern volatile unsigned char CompInterruptFreigabe; |
9 | extern volatile unsigned char CompInterruptFreigabe; |
10 | 10 | ||
11 | void Blc(void); |
11 | void Blc(void); |
12 | void Manuell(void); |
12 | void Manuell(void); |
13 | 13 | ||
14 | #ifdef _32KHZ |
14 | #ifdef _32KHZ |
15 | #define PWM_C_ON {TCCR1A = 0xA1; TCCR2 = 0x49; DDRB = 0x0A;} |
15 | #define PWM_C_ON {TCCR1A = 0xA1; TCCR2 = 0x49; DDRB = 0x0A;} |
16 | #define PWM_B_ON {TCCR1A = 0xA1; TCCR2 = 0x49; DDRB = 0x0C;} |
16 | #define PWM_B_ON {TCCR1A = 0xA1; TCCR2 = 0x49; DDRB = 0x0C;} |
17 | #define PWM_A_ON {TCCR1A = 0xA1; TCCR2 = 0x69; DDRB = 0x08;} |
17 | #define PWM_A_ON {TCCR1A = 0xA1; TCCR2 = 0x69; DDRB = 0x08;} |
18 | #define PWM_OFF {TCCR1A = 0x01; TCCR2 = 0x49; PORTC &= ~0x0E;} |
18 | #define PWM_OFF {TCCR1A = 0x01; TCCR2 = 0x49; PORTC &= ~0x0E;} |
19 | #endif |
19 | #endif |
20 | 20 | ||
21 | #ifdef _16KHZ |
21 | #ifdef _16KHZ |
22 | #define PWM_C_ON {TCCR1A = 0xA1; TCCR2 = 0x41; DDRB = 0x0A;} |
22 | #define PWM_C_ON {TCCR1A = 0xA2; TCCR2 = 0x41; DDRB = 0x0A;} |
23 | #define PWM_B_ON {TCCR1A = 0xA1; TCCR2 = 0x41; DDRB = 0x0C;} |
23 | #define PWM_B_ON {TCCR1A = 0xA2; TCCR2 = 0x41; DDRB = 0x0C;} |
24 | #define PWM_A_ON {TCCR1A = 0xA1; TCCR2 = 0x61; DDRB = 0x08;} |
24 | #define PWM_A_ON {TCCR1A = 0xA2; TCCR2 = 0x61; DDRB = 0x08;} |
25 | #define PWM_OFF {TCCR1A = 0x01; TCCR2 = 0x41; PORTC &= ~0x0E;} |
25 | #define PWM_OFF {TCCR1A = 0x02; TCCR2 = 0x41; PORTC &= ~0x0E;} |
26 | #endif |
26 | #endif |
27 | 27 | ||
28 | 28 | ||
29 | #define STEUER_A_H {PWM_A_ON} |
29 | #define STEUER_A_H {PWM_A_ON} |
30 | #define STEUER_B_H {PWM_B_ON} |
30 | #define STEUER_B_H {PWM_B_ON} |
31 | #define STEUER_C_H {PWM_C_ON} |
31 | #define STEUER_C_H {PWM_C_ON} |
32 | 32 | ||
33 | #define STEUER_A_L {PORTD &= ~0x30; PORTD |= 0x08;} |
33 | #define STEUER_A_L {PORTD &= ~0x30; PORTD |= 0x08;} |
34 | #define STEUER_B_L {PORTD &= ~0x28; PORTD |= 0x10;} |
34 | #define STEUER_B_L {PORTD &= ~0x28; PORTD |= 0x10;} |
35 | #define STEUER_C_L {PORTD &= ~0x18; PORTD |= 0x20;} |
35 | #define STEUER_C_L {PORTD &= ~0x18; PORTD |= 0x20;} |
36 | #define STEUER_OFF {PORTD &= ~0x38; PWM_OFF;} |
36 | #define STEUER_OFF {PORTD &= ~0x38; PWM_OFF;} |
37 | 37 | ||
38 | #define SENSE_A ADMUX = 0; |
38 | #define SENSE_A ADMUX = 0; |
39 | #define SENSE_B ADMUX = 1; |
39 | #define SENSE_B ADMUX = 1; |
40 | #define SENSE_C ADMUX = 2; |
40 | #define SENSE_C ADMUX = 2; |
41 | 41 | ||
42 | #define ClrSENSE ACSR |= 0x10 |
42 | #define ClrSENSE ACSR |= 0x10 |
43 | #define SENSE ((ACSR & 0x10)) |
43 | #define SENSE ((ACSR & 0x10)) |
44 | #define SENSE_L (!(ACSR & 0x20)) |
44 | #define SENSE_L (!(ACSR & 0x20)) |
45 | #define SENSE_H ((ACSR & 0x20)) |
45 | #define SENSE_H ((ACSR & 0x20)) |
46 | #define ENABLE_SENSE_INT {CompInterruptFreigabe = 1;ACSR |= 0x0A; } |
46 | #define ENABLE_SENSE_INT {CompInterruptFreigabe = 1;ACSR |= 0x0A; } |
47 | #define DISABLE_SENSE_INT {CompInterruptFreigabe = 0; ACSR &= ~0x08; } |
47 | #define DISABLE_SENSE_INT {CompInterruptFreigabe = 0; ACSR &= ~0x08; } |
48 | 48 | ||
49 | 49 | ||
50 | #define SENSE_FALLING_INT ACSR &= ~0x01 |
50 | #define SENSE_FALLING_INT ACSR &= ~0x01 |
51 | #define SENSE_RISING_INT ACSR |= 0x03 |
51 | #define SENSE_RISING_INT ACSR |= 0x03 |
52 | #define SENSE_TOGGLE_INT ACSR &= ~0x03 |
52 | #define SENSE_TOGGLE_INT ACSR &= ~0x03 |
53 | 53 | ||
54 | #endif //BLMC_H_ |
54 | #endif //BLMC_H_ |
55 | 55 | ||
56 | 56 |