Rev 2039 | Only display areas with differences | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 2039 | Rev 2189 | ||
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1 | #include <avr/io.h> |
1 | #include <avr/io.h> |
2 | #include <avr/interrupt.h> |
2 | #include <avr/interrupt.h> |
3 | #include "uart1.h" |
3 | #include "uart1.h" |
4 | #include "ubx.h" |
4 | #include "ubx.h" |
5 | 5 | ||
6 | #define USART1_BAUD 57600 |
6 | #define USART1_BAUD 57600 |
7 | 7 | ||
8 | /****************************************************************/ |
8 | /****************************************************************/ |
9 | /* Initialization of the USART1 */ |
9 | /* Initialization of the USART1 */ |
10 | /****************************************************************/ |
10 | /****************************************************************/ |
11 | void usart1_init(void) { |
11 | void usart1_init(void) { |
12 | // USART1 Control and Status Register A, B, C and baud rate register |
12 | // USART1 Control and Status Register A, B, C and baud rate register |
13 | uint8_t sreg = SREG; |
13 | uint8_t sreg = SREG; |
14 | uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU / (8 * USART1_BAUD) - 1); |
14 | uint16_t ubrr = (uint16_t) (F_CPU / (8 * USART1_BAUD) - 1); |
15 | 15 | ||
16 | // disable all interrupts before reconfiguration |
16 | // disable all interrupts before reconfiguration |
17 | cli(); |
17 | cli(); |
18 | 18 | ||
19 | // disable RX-Interrupt, disable TX-Interrupt, disable DRE-Interrupt |
19 | // disable RX-Interrupt, disable TX-Interrupt, disable DRE-Interrupt |
20 | UCSR1B &= ~ ((1 << RXCIE1) | (1 << TXCIE1) | (1 << UDRIE1)); |
20 | UCSR1B &= ~ ((1 << RXCIE1) | (1 << TXCIE1) | (1 << UDRIE1)); |
21 | 21 | ||
22 | // set direction of RXD1 and TXD1 pins |
22 | // set direction of RXD1 and TXD1 pins |
23 | // set RXD1 (PD2) as an input pin, set TXD1 (PD3) as an output pin |
23 | // set RXD1 (PD2) as an input pin, set TXD1 (PD3) as an output pin |
24 | PORTD |= (1 << PORTD2) | (1 << PORTD3); |
24 | PORTD |= (1 << PORTD2) | (1 << PORTD3); |
25 | DDRD &= ~(1 << DDD2); |
25 | DDRD &= ~(1 << DDD2); |
26 | DDRD |= (1 << DDD3); |
26 | DDRD |= (1 << DDD3); |
27 | 27 | ||
28 | // USART0 Baud Rate Register |
28 | // USART0 Baud Rate Register |
29 | // set clock divider |
29 | // set clock divider |
30 | UBRR1H = (uint8_t) (ubrr >> 8); |
30 | UBRR1H = (uint8_t) (ubrr >> 8); |
31 | UBRR1L = (uint8_t) ubrr; |
31 | UBRR1L = (uint8_t) ubrr; |
32 | 32 | ||
33 | // enable double speed operation |
33 | // enable double speed operation |
34 | UCSR1A |= (1 << U2X1); |
34 | UCSR1A |= (1 << U2X1); |
35 | // enable receiver and transmitter |
35 | // enable receiver and transmitter |
36 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
36 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
37 | // set asynchronous mode, no parity, 1 stop bit |
37 | // set asynchronous mode, no parity, 1 stop bit |
38 | UCSR1C &= ~((1 << UMSEL11) | (1 << UMSEL10) | (1 << UPM11) | (1 << UPM10) | (1 << USBS1)); |
38 | UCSR1C &= ~((1 << UMSEL11) | (1 << UMSEL10) | (1 << UPM11) | (1 << UPM10) | (1 << USBS1)); |
39 | 39 | ||
40 | // 8-bit |
40 | // 8-bit |
41 | UCSR1B &= ~(1 << UCSZ12); |
41 | UCSR1B &= ~(1 << UCSZ12); |
42 | UCSR1C |= (1 << UCSZ11) | (1 << UCSZ10); |
42 | UCSR1C |= (1 << UCSZ11) | (1 << UCSZ10); |
43 | 43 | ||
44 | // flush receive buffer explicit |
44 | // flush receive buffer explicit |
45 | while (UCSR1A & (1 << RXC1)) |
45 | while (UCSR1A & (1 << RXC1)) |
46 | UDR1; |
46 | UDR1; |
47 | 47 | ||
48 | // enable interrupts at the end |
48 | // enable interrupts at the end |
49 | // enable RX-Interrupt |
49 | // enable RX-Interrupt |
50 | UCSR1B |= (1 << RXCIE1); |
50 | UCSR1B |= (1 << RXCIE1); |
51 | // enable TX-Interrupt |
51 | // enable TX-Interrupt |
52 | //UCSR1B |= (1 << TXCIE1); |
52 | //UCSR1B |= (1 << TXCIE1); |
53 | // enable DRE interrupt |
53 | // enable DRE interrupt |
54 | //UCSR1B |= (1 << UDRIE1); |
54 | //UCSR1B |= (1 << UDRIE1); |
55 | 55 | ||
56 | // restore global interrupt flags |
56 | // restore global interrupt flags |
57 | SREG = sreg; |
57 | SREG = sreg; |
58 | } |
58 | } |
59 | 59 | ||
60 | /****************************************************************/ |
60 | /****************************************************************/ |
61 | /* USART1 data register empty ISR */ |
61 | /* USART1 data register empty ISR */ |
62 | /****************************************************************/ |
62 | /****************************************************************/ |
63 | /*ISR(USART1_UDRE_vect) { |
63 | /*ISR(USART1_UDRE_vect) { |
64 | } |
64 | } |
65 | */ |
65 | */ |
66 | 66 | ||
67 | /****************************************************************/ |
67 | /****************************************************************/ |
68 | /* USART1 transmitter ISR */ |
68 | /* USART1 transmitter ISR */ |
69 | /****************************************************************/ |
69 | /****************************************************************/ |
70 | /*ISR(USART1_TX_vect) { |
70 | /*ISR(USART1_TX_vect) { |
71 | } |
71 | } |
72 | */ |
72 | */ |
73 | /****************************************************************/ |
73 | /****************************************************************/ |
74 | /* USART1 receiver ISR */ |
74 | /* USART1 receiver ISR */ |
75 | /****************************************************************/ |
75 | /****************************************************************/ |
76 | ISR(USART1_RX_vect) { |
76 | ISR(USART1_RX_vect) { |
77 | ubx_parser(UDR1); // get data byte and put it into the ubx protocol parser |
77 | ubx_parser(UDR1); // get data byte and put it into the ubx protocol parser |
78 | } |
78 | } |
79 | 79 |