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Rev 2039 Rev 2189
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#include <avr/io.h>
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include <avr/interrupt.h>
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#include "uart1.h"
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#include "uart1.h"
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#include "ubx.h"
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#include "ubx.h"
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#define USART1_BAUD 57600
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#define USART1_BAUD 57600
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/****************************************************************/
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/****************************************************************/
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/*              Initialization of the USART1                    */
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/*              Initialization of the USART1                    */
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/****************************************************************/
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/****************************************************************/
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void usart1_init(void) {
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void usart1_init(void) {
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        // USART1 Control and Status Register A, B, C and baud rate register
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        // USART1 Control and Status Register A, B, C and baud rate register
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        uint8_t sreg = SREG;
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        uint8_t sreg = SREG;
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        uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU / (8 * USART1_BAUD) - 1);
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        uint16_t ubrr = (uint16_t) (F_CPU / (8 * USART1_BAUD) - 1);
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        // disable all interrupts before reconfiguration
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        // disable all interrupts before reconfiguration
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        cli();
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        cli();
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        // disable RX-Interrupt, disable TX-Interrupt, disable DRE-Interrupt
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        // disable RX-Interrupt, disable TX-Interrupt, disable DRE-Interrupt
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        UCSR1B &= ~ ((1 << RXCIE1) | (1 << TXCIE1) | (1 << UDRIE1));
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        UCSR1B &= ~ ((1 << RXCIE1) | (1 << TXCIE1) | (1 << UDRIE1));
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        // set direction of RXD1 and TXD1 pins
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        // set direction of RXD1 and TXD1 pins
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        // set RXD1 (PD2) as an input pin,  set TXD1 (PD3) as an output pin
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        // set RXD1 (PD2) as an input pin,  set TXD1 (PD3) as an output pin
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        PORTD |= (1 << PORTD2) | (1 << PORTD3);
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        PORTD |= (1 << PORTD2) | (1 << PORTD3);
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        DDRD &= ~(1 << DDD2);
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        DDRD &= ~(1 << DDD2);
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        DDRD |= (1 << DDD3);
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        DDRD |= (1 << DDD3);
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        // USART0 Baud Rate Register
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        // USART0 Baud Rate Register
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        // set clock divider
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        // set clock divider
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        UBRR1H = (uint8_t) (ubrr >> 8);
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        UBRR1H = (uint8_t) (ubrr >> 8);
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        UBRR1L = (uint8_t) ubrr;
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        UBRR1L = (uint8_t) ubrr;
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        // enable double speed operation
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        // enable double speed operation
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        UCSR1A |= (1 << U2X1);
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        UCSR1A |= (1 << U2X1);
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        // enable receiver and transmitter
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        // enable receiver and transmitter
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        UCSR1B = (1 << TXEN1) | (1 << RXEN1);
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        UCSR1B = (1 << TXEN1) | (1 << RXEN1);
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        // set asynchronous mode,  no parity, 1 stop bit
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        // set asynchronous mode,  no parity, 1 stop bit
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        UCSR1C &= ~((1 << UMSEL11) | (1 << UMSEL10) | (1 << UPM11) | (1 << UPM10) | (1 << USBS1));
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        UCSR1C &= ~((1 << UMSEL11) | (1 << UMSEL10) | (1 << UPM11) | (1 << UPM10) | (1 << USBS1));
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        // 8-bit
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        // 8-bit
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        UCSR1B &= ~(1 << UCSZ12);
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        UCSR1B &= ~(1 << UCSZ12);
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        UCSR1C |= (1 << UCSZ11) | (1 << UCSZ10);
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        UCSR1C |= (1 << UCSZ11) | (1 << UCSZ10);
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        // flush receive buffer explicit
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        // flush receive buffer explicit
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        while (UCSR1A & (1 << RXC1))
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        while (UCSR1A & (1 << RXC1))
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                UDR1;
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                UDR1;
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        // enable interrupts at the end
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        // enable interrupts at the end
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        // enable RX-Interrupt
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        // enable RX-Interrupt
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        UCSR1B |= (1 << RXCIE1);
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        UCSR1B |= (1 << RXCIE1);
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        // enable TX-Interrupt
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        // enable TX-Interrupt
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        //UCSR1B |= (1 << TXCIE1);
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        //UCSR1B |= (1 << TXCIE1);
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        // enable DRE interrupt
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        // enable DRE interrupt
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        //UCSR1B |= (1 << UDRIE1);
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        //UCSR1B |= (1 << UDRIE1);
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        // restore global interrupt flags
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        // restore global interrupt flags
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        SREG = sreg;
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        SREG = sreg;
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}
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}
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/****************************************************************/
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/****************************************************************/
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/*               USART1 data register empty ISR                 */
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/*               USART1 data register empty ISR                 */
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/****************************************************************/
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/****************************************************************/
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/*ISR(USART1_UDRE_vect) {
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/*ISR(USART1_UDRE_vect) {
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 }
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 }
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 */
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 */
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/****************************************************************/
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/****************************************************************/
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/*               USART1 transmitter ISR                         */
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/*               USART1 transmitter ISR                         */
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/****************************************************************/
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/****************************************************************/
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/*ISR(USART1_TX_vect) {
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/*ISR(USART1_TX_vect) {
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 }
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 }
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 */
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 */
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/****************************************************************/
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/****************************************************************/
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/*               USART1 receiver ISR                            */
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/*               USART1 receiver ISR                            */
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/****************************************************************/
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/****************************************************************/
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ISR(USART1_RX_vect) {
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ISR(USART1_RX_vect) {
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    ubx_parser(UDR1);  // get data byte and put it into the ubx protocol parser
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    ubx_parser(UDR1);  // get data byte and put it into the ubx protocol parser
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}
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}
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