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1 | /*####################################################################################### |
1 | /*####################################################################################### |
2 | Decodes the sbus protocol |
2 | Decodes the sbus protocol |
3 | #######################################################################################*/ |
3 | #######################################################################################*/ |
4 | 4 | ||
5 | #include "sbus.h" |
5 | #include "sbus.h" |
6 | #include "main.h" |
6 | #include "main.h" |
7 | 7 | ||
8 | #if (defined(__AVR_ATmega1284__) || defined(__AVR_ATmega1284P__)) |
8 | #if (defined(__AVR_ATmega1284__) || defined(__AVR_ATmega1284P__)) |
9 | unsigned char NewSBusData = 0, sBusBuffer[25]; |
9 | unsigned char NewSBusData = 0, sBusBuffer[25]; |
10 | 10 | ||
11 | //############################################################################ |
11 | //############################################################################ |
12 | // USART1 initialisation from killagreg |
12 | // USART1 initialisation from killagreg |
13 | void SbusUartInit(void) |
13 | void SbusUartInit(void) |
14 | //############################################################################ |
14 | //############################################################################ |
15 | { |
15 | { |
16 | // -- Start of USART1 initialisation for Spekturm seriell-mode |
16 | // -- Start of USART1 initialisation for Spekturm seriell-mode |
17 | // USART1 Control and Status Register A, B, C and baud rate register |
17 | // USART1 Control and Status Register A, B, C and baud rate register |
18 | uint8_t sreg = SREG; |
18 | uint8_t sreg = SREG; |
19 | 19 | ||
20 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * 100000) - 1); |
20 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * 100000) - 1); |
21 | 21 | ||
22 | // disable all interrupts before reconfiguration |
22 | // disable all interrupts before reconfiguration |
23 | cli(); |
23 | cli(); |
24 | // disable RX-Interrupt |
24 | // disable RX-Interrupt |
25 | UCSR1B &= ~(1 << RXCIE1); |
25 | UCSR1B &= ~(1 << RXCIE1); |
26 | // disable TX-Interrupt |
26 | // disable TX-Interrupt |
27 | UCSR1B &= ~(1 << TXCIE1); |
27 | UCSR1B &= ~(1 << TXCIE1); |
28 | // disable DRE-Interrupt |
28 | // disable DRE-Interrupt |
29 | UCSR1B &= ~(1 << UDRIE1); |
29 | UCSR1B &= ~(1 << UDRIE1); |
30 | // set direction of RXD1 and TXD1 pins |
30 | // set direction of RXD1 and TXD1 pins |
31 | // set RXD1 (PD2) as an input pin |
31 | // set RXD1 (PD2) as an input pin |
32 | PORTD |= (1 << PORTD2); |
32 | PORTD |= (1 << PORTD2); |
33 | DDRD &= ~(1 << DDD2); |
33 | DDRD &= ~(1 << DDD2); |
34 | 34 | ||
35 | // set TXD1 (PD3) as an output pin |
35 | // set TXD1 (PD3) as an output pin |
36 | PORTD |= (1 << PORTD3); |
36 | PORTD |= (1 << PORTD3); |
37 | DDRD |= (1 << DDD3); |
37 | DDRD |= (1 << DDD3); |
38 | 38 | ||
39 | // USART0 Baud Rate Register |
39 | // USART0 Baud Rate Register |
40 | // set clock divider |
40 | // set clock divider |
41 | UBRR1H = (uint8_t)(ubrr>>8); |
41 | UBRR1H = (uint8_t)(ubrr>>8); |
42 | UBRR1L = (uint8_t)ubrr; |
42 | UBRR1L = (uint8_t)ubrr; |
43 | // enable double speed operation |
43 | // enable double speed operation |
44 | UCSR1A |= (1 << U2X1); |
44 | UCSR1A |= (1 << U2X1); |
45 | // enable receiver and transmitter |
45 | // enable receiver and transmitter |
46 | //UCSR1B = (1<<RXEN1)|(1<<TXEN1); |
46 | //UCSR1B = (1<<RXEN1)|(1<<TXEN1); |
47 | 47 | ||
48 | UCSR1B = (1<<RXEN1); |
48 | UCSR1B = (1<<RXEN1); |
49 | // set asynchronous mode |
49 | // set asynchronous mode |
50 | UCSR1C &= ~(1 << UMSEL11); |
50 | UCSR1C &= ~(1 << UMSEL11); |
51 | UCSR1C &= ~(1 << UMSEL10); |
51 | UCSR1C &= ~(1 << UMSEL10); |
52 | // parity |
52 | // parity |
53 | UCSR1C <= (1 << UPM11); // even |
53 | UCSR1C <= (1 << UPM11); // even |
54 | UCSR1C &= ~(1 << UPM10); |
54 | UCSR1C &= ~(1 << UPM10); |
55 | // stop bit |
55 | // stop bit |
56 | UCSR1C |= (1 << USBS1); // two |
56 | UCSR1C |= (1 << USBS1); // two |
57 | // 8-bit |
57 | // 8-bit |
58 | UCSR1B &= ~(1 << UCSZ12); |
58 | UCSR1B &= ~(1 << UCSZ12); |
59 | UCSR1C |= (1 << UCSZ11); |
59 | UCSR1C |= (1 << UCSZ11); |
60 | UCSR1C |= (1 << UCSZ10); |
60 | UCSR1C |= (1 << UCSZ10); |
61 | // flush receive buffer explicit |
61 | // flush receive buffer explicit |
62 | while(UCSR1A & (1<<RXC1)) UDR1; |
62 | while(UCSR1A & (1<<RXC1)) UDR1; |
63 | // enable RX-interrupts at the end |
63 | // enable RX-interrupts at the end |
64 | UCSR1B |= (1 << RXCIE1); |
64 | UCSR1B |= (1 << RXCIE1); |
65 | // -- End of USART1 initialisation |
65 | // -- End of USART1 initialisation |
66 | // restore global interrupt flags |
66 | // restore global interrupt flags |
67 | - | ||
- | 67 | sBusBuffer[23] |= 4; // This Bit contains the 'Signal loss' |
|
68 | SREG = sreg; |
68 | SREG = sreg; |
69 | return; |
69 | return; |
70 | } |
70 | } |
71 | 71 | ||
72 | // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
72 | // ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
73 | #define MIN_FRAMEGAP 68 // 7ms |
73 | #define MIN_FRAMEGAP 68 // 7ms |
74 | #define MAX_BYTEGAP 3 // 310us |
74 | #define MAX_BYTEGAP 3 // 310us |
75 | 75 | ||
76 | //############################################################################ |
76 | //############################################################################ |
77 | // Is called by the uart interrupt |
77 | // Is called by the uart interrupt |
78 | //############################################################################ |
78 | //############################################################################ |
79 | void SbusParser(unsigned char udr) |
79 | void SbusParser(unsigned char udr) |
80 | { |
80 | { |
81 | static unsigned char ptr = 0; |
81 | static unsigned char ptr = 0; |
82 | if(!SpektrumTimer && udr == 0x0f) // wait for the start |
82 | if(!SpektrumTimer && udr == 0x0f) // wait for the start |
83 | { |
83 | { |
84 | ptr = 0; |
84 | ptr = 0; |
85 | } |
85 | } |
86 | else |
86 | else |
87 | { |
87 | { |
88 | if(++ptr == 24) // last byte |
88 | if(++ptr == 24) // last byte |
89 | { |
89 | { |
90 | NewSBusData = 1; |
90 | NewSBusData = 1; |
91 | } |
91 | } |
92 | else |
92 | else |
93 | if(ptr > 24) ptr = 25; |
93 | if(ptr > 24) ptr = 25; |
94 | else |
94 | else |
95 | { |
95 | { |
96 | sBusBuffer[ptr] = udr; // collect all bytes |
96 | sBusBuffer[ptr] = udr; // collect all bytes |
97 | } |
97 | } |
98 | } |
98 | } |
99 | SpektrumTimer = 100; // 10ms gap |
99 | SpektrumTimer = 100; // 10ms gap |
100 | } |
100 | } |
101 | 101 | ||
102 | void ProcessSBus(void) |
102 | void ProcessSBus(void) |
103 | { |
103 | { |
104 | static unsigned char load = 0; |
104 | static unsigned char load = 0; |
105 | unsigned char bitmask8 = 1, sbyte = 2, i, index = 1, process; |
105 | unsigned char bitmask8 = 1, sbyte = 2, i, index = 1, process; |
106 | unsigned int bitmask11 = 256; |
106 | unsigned int bitmask11 = 256; |
107 | signed int signal = 0,tmp; |
107 | signed int signal = 0,tmp; |
108 | 108 | ||
109 | if(!(sBusBuffer[23] & 4)) // This Bit contains the 'Signal loss' |
109 | if(!(sBusBuffer[23] & 4)) // This Bit contains the 'Signal loss' |
110 | { |
110 | { |
111 | TIMSK1 &= ~_BV(ICIE1); // disable PPM-Input |
111 | TIMSK1 &= ~_BV(ICIE1); // disable PPM-Input |
112 | if(EE_Parameter.FailsafeChannel == 0 || PPM_in[EE_Parameter.FailsafeChannel] < 100) // forces Failsafe if the receiver doesn't have 'signal loss' on Failsafe |
112 | if(EE_Parameter.FailsafeChannel == 0 || PPM_in[EE_Parameter.FailsafeChannel] < 100) // forces Failsafe if the receiver doesn't have 'signal loss' on Failsafe |
113 | { |
113 | { |
114 | if(SenderOkay < 200) SenderOkay += 10; else SenderOkay = 200; |
114 | if(SenderOkay < 200) SenderOkay += 10; else SenderOkay = 200; |
115 | } |
115 | } |
116 | signal = sBusBuffer[1]; |
116 | signal = sBusBuffer[1]; |
117 | if(!load--) { process = (12*11 - 8); load = 2;} else process = (4*11 - 8); // lowers the processor load |
117 | if(!load--) { process = (12*11 - 8); load = 2;} else process = (4*11 - 8); // lowers the processor load |
118 | for(i = 0; i < process; i++) // collect the single bits |
118 | for(i = 0; i < process; i++) // collect the single bits |
119 | { |
119 | { |
120 | if(sBusBuffer[sbyte] & bitmask8) signal |= bitmask11; |
120 | if(sBusBuffer[sbyte] & bitmask8) signal |= bitmask11; |
121 | bitmask8 *= 2; |
121 | bitmask8 *= 2; |
122 | if(!bitmask8) |
122 | if(!bitmask8) |
123 | { |
123 | { |
124 | bitmask8 = 1; |
124 | bitmask8 = 1; |
125 | sbyte++; |
125 | sbyte++; |
126 | } |
126 | } |
127 | bitmask11 *= 2; |
127 | bitmask11 *= 2; |
128 | if(bitmask11 == 2048) |
128 | if(bitmask11 == 2048) |
129 | { |
129 | { |
130 | bitmask11 = 1; |
130 | bitmask11 = 1; |
131 | signal = (signal-1024) / 5; // the resolution is higher than required |
131 | signal = (signal-1024) / 5; // the resolution is higher than required |
132 | tmp = (3 * (PPM_in[index]) + signal) / 4; |
132 | tmp = (3 * (PPM_in[index]) + signal) / 4; |
133 | if(tmp > signal+1) tmp--; else |
133 | if(tmp > signal+1) tmp--; else |
134 | if(tmp < signal-1) tmp++; |
134 | if(tmp < signal-1) tmp++; |
135 | if(SenderOkay >= 195) PPM_diff[index] = ((tmp - PPM_in[index]) / 3) * 3; |
135 | if(SenderOkay >= 195) PPM_diff[index] = ((tmp - PPM_in[index]) / 3) * 3; |
136 | else PPM_diff[index] = 0; |
136 | else PPM_diff[index] = 0; |
137 | PPM_in[index] = tmp; |
137 | PPM_in[index] = tmp; |
138 | signal = 0; |
138 | signal = 0; |
139 | index++; // next channel |
139 | index++; // next channel |
140 | } |
140 | } |
141 | } |
141 | } |
142 | NewPpmData = 0; // Null bedeutet: Neue Daten |
142 | NewPpmData = 0; // Null bedeutet: Neue Daten |
143 | } |
143 | } |
144 | NewSBusData = 0; |
144 | NewSBusData = 0; |
145 | } |
145 | } |
146 | 146 | ||
147 | #endif |
147 | #endif |
148 | 148 |