WebSVN - FlightCtrl - Diff - Rev 903 and 909 - /branches/V0.69k CRK HexaLotte/uart1.c


#include <avr/io.h>
#include <avr/interrupt.h>
 
 
#include "main.h"
#include "uart1.h"
#include "fifo.h"
#ifdef USE_KILLAGREG
#include "ubx.h"
#endif
 
 
 
// FIFO-objects and buffers for input and output
 
//#define BUFSIZE_IN  0x96
//volatile uint8_t inbuf[BUFSIZE_IN];
//fifo_t infifo;
 
#define BUFSIZE_OUT 0x96
volatile uint8_t outbuf[BUFSIZE_OUT];
fifo_t outfifo;
 
/****************************************************************/
/*              Initialization of the USART1                    */
/****************************************************************/
void USART1_Init (void)
{
        // USART1 Control and Status Register A, B, C and baud rate register
        uint8_t sreg = SREG;
        uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1);
 
        // disable all interrupts before reconfiguration
        cli();
 
        // disable RX-Interrupt
        UCSR1B &= ~(1 << RXCIE1);
        // disable TX-Interrupt
        UCSR1B &= ~(1 << TXCIE1);
        // disable DRE-Interrupt
        UCSR1B &= ~(1 << UDRIE1);
 
        // set direction of RXD1 and TXD1 pins
        // set RXD1 (PD2) as an input pin
        PORTD |= (1 << PORTD2);
        DDRD &= ~(1 << DDD2);
 
        // set TXD1 (PD3) as an output pin
        PORTD |= (1 << PORTD3);
        DDRD  |= (1 << DDD3);
 
        // USART0 Baud Rate Register
        // set clock divider
        UBRR1H = (uint8_t)(ubrr>>8);
        UBRR1L = (uint8_t)ubrr;
 
        // enable double speed operation
        UCSR1A |= (1 << U2X1);
        // enable receiver and transmitter
        UCSR1B = (1 << TXEN1) | (1 << RXEN1);
        // set asynchronous mode
        UCSR1C &= ~(1 << UMSEL11);
        UCSR1C &= ~(1 << UMSEL10);
        // no parity
        UCSR1C &= ~(1 << UPM11);
        UCSR1C &= ~(1 << UPM10);
        // 1 stop bit
        UCSR1C &= ~(1 << USBS1);
        // 8-bit
        UCSR1B &= ~(1 << UCSZ12);
        UCSR1C |=  (1 << UCSZ11);
        UCSR1C |=  (1 << UCSZ10);
 
        // flush receive buffer explicit
        while ( UCSR1A & (1<<RXC1) ) UDR1;
 
        // enable interrupts at the end
        // enable RX-Interrupt
        UCSR1B |= (1 << RXCIE1);
        // enable TX-Interrupt
        UCSR1B |= (1 << TXCIE1);
        // enable DRE interrupt
        //UCSR1B |= (1 << UDRIE1);
 
 
        // restore global interrupt flags
    SREG = sreg;
 
    // inint FIFO buffer
        //fifo_init (&infifo,   inbuf, BUFSIZE_IN);
    //fifo_init (&outfifo, outbuf, BUFSIZE_OUT);
}
 
/*int16_t USART1_putc (const uint8_t c)
{
    int16_t ret = fifo_put (&outfifo, c);
    // create an data register empty interrupt
    UCSR1B |= (1 << UDRIE1);
 
    return ret;
}
*/
/*int16_t USART1_getc_nowait ()
{
    return fifo_get_nowait (&infifo);
}
 
 
uint8_t USART1_getc_wait ()
{
    return fifo_get_wait (&infifo);
}
*/
 
/****************************************************************/
/*               USART1 data register empty ISR                 */
/****************************************************************/
/*ISR(USART1_UDRE_vect)
{
// Move a character from the output buffer to the data register.
// When the character was processed the next interrupt is generated.
// If the output buffer is empty the DRE-interrupt is disabled.
    if (outfifo.count > 0)
       UDR1 = _inline_fifo_get (&outfifo);
    else
        UCSR1B &= ~(1 << UDRIE1);
}
*/
 
/****************************************************************/
/*               USART1 transmitter ISR                         */
/****************************************************************/
/*ISR(USART1_TX_vect)
{
 
}
*/
/****************************************************************/
/*               USART1 receiver ISR                            */
/****************************************************************/
ISR(USART1_RX_vect)
{
        uint8_t c;
        c = UDR1; // get data byte
        #if defined (USE_KILLAGREG) || defined (USE_MK3MAG)
        if (BoardRelease == 11) ubx_parser(c); // and put it into the ubx protocol parser
        #endif
}
 

Rev 903	Rev 909
1	#include <avr/io.h>	1	#include <avr/io.h>
2	#include <avr/interrupt.h>	2	#include <avr/interrupt.h>
3		3
4		4
5	#include "main.h"	5	#include "main.h"
6	#include "uart1.h"	6	#include "uart1.h"
7	#include "fifo.h"	7	#include "fifo.h"
8	#ifdef USE_KILLAGREG	8	#ifdef USE_KILLAGREG
9	#include "ubx.h"	9	#include "ubx.h"
10	#endif	10	#endif
11		11
12		12
13		13
14	// FIFO-objects and buffers for input and output	14	// FIFO-objects and buffers for input and output
15		15
16	//#define BUFSIZE_IN 0x96	16	//#define BUFSIZE_IN 0x96
17	//volatile uint8_t inbuf[BUFSIZE_IN];	17	//volatile uint8_t inbuf[BUFSIZE_IN];
18	//fifo_t infifo;	18	//fifo_t infifo;
19		19
20	#define BUFSIZE_OUT 0x96	20	#define BUFSIZE_OUT 0x96
21	volatile uint8_t outbuf[BUFSIZE_OUT];	21	volatile uint8_t outbuf[BUFSIZE_OUT];
22	fifo_t outfifo;	22	fifo_t outfifo;
23		23
24	/****************************************************************/	24	/****************************************************************/
25	/* Initialization of the USART1 */	25	/* Initialization of the USART1 */
26	/****************************************************************/	26	/****************************************************************/
27	void USART1_Init (void)	27	void USART1_Init (void)
28	{	28	{
29	// USART1 Control and Status Register A, B, C and baud rate register	29	// USART1 Control and Status Register A, B, C and baud rate register
30	uint8_t sreg = SREG;	30	uint8_t sreg = SREG;
31	uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1);	31	uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1);
32		32
33	// disable all interrupts before reconfiguration	33	// disable all interrupts before reconfiguration
34	cli();	34	cli();
35		35
36	// disable RX-Interrupt	36	// disable RX-Interrupt
37	UCSR1B &= ~(1 << RXCIE1);	37	UCSR1B &= ~(1 << RXCIE1);
38	// disable TX-Interrupt	38	// disable TX-Interrupt
39	UCSR1B &= ~(1 << TXCIE1);	39	UCSR1B &= ~(1 << TXCIE1);
40	// disable DRE-Interrupt	40	// disable DRE-Interrupt
41	UCSR1B &= ~(1 << UDRIE1);	41	UCSR1B &= ~(1 << UDRIE1);
42		42
43	// set direction of RXD1 and TXD1 pins	43	// set direction of RXD1 and TXD1 pins
44	// set RXD1 (PD2) as an input pin	44	// set RXD1 (PD2) as an input pin
45	PORTD \|= (1 << PORTD2);	45	PORTD \|= (1 << PORTD2);
46	DDRD &= ~(1 << DDD2);	46	DDRD &= ~(1 << DDD2);
47		47
48	// set TXD1 (PD3) as an output pin	48	// set TXD1 (PD3) as an output pin
49	PORTD \|= (1 << PORTD3);	49	PORTD \|= (1 << PORTD3);
50	DDRD \|= (1 << DDD3);	50	DDRD \|= (1 << DDD3);
51		51
52	// USART0 Baud Rate Register	52	// USART0 Baud Rate Register
53	// set clock divider	53	// set clock divider
54	UBRR1H = (uint8_t)(ubrr>>8);	54	UBRR1H = (uint8_t)(ubrr>>8);
55	UBRR1L = (uint8_t)ubrr;	55	UBRR1L = (uint8_t)ubrr;
56		56
57	// enable double speed operation	57	// enable double speed operation
58	UCSR1A \|= (1 << U2X1);	58	UCSR1A \|= (1 << U2X1);
59	// enable receiver and transmitter	59	// enable receiver and transmitter
60	UCSR1B = (1 << TXEN1) \| (1 << RXEN1);	60	UCSR1B = (1 << TXEN1) \| (1 << RXEN1);
61	// set asynchronous mode	61	// set asynchronous mode
62	UCSR1C &= ~(1 << UMSEL11);	62	UCSR1C &= ~(1 << UMSEL11);
63	UCSR1C &= ~(1 << UMSEL10);	63	UCSR1C &= ~(1 << UMSEL10);
64	// no parity	64	// no parity
65	UCSR1C &= ~(1 << UPM11);	65	UCSR1C &= ~(1 << UPM11);
66	UCSR1C &= ~(1 << UPM10);	66	UCSR1C &= ~(1 << UPM10);
67	// 1 stop bit	67	// 1 stop bit
68	UCSR1C &= ~(1 << USBS1);	68	UCSR1C &= ~(1 << USBS1);
69	// 8-bit	69	// 8-bit
70	UCSR1B &= ~(1 << UCSZ12);	70	UCSR1B &= ~(1 << UCSZ12);
71	UCSR1C \|= (1 << UCSZ11);	71	UCSR1C \|= (1 << UCSZ11);
72	UCSR1C \|= (1 << UCSZ10);	72	UCSR1C \|= (1 << UCSZ10);
73		73
74	// flush receive buffer explicit	74	// flush receive buffer explicit
75	while ( UCSR1A & (1<<RXC1) ) UDR1;	75	while ( UCSR1A & (1<<RXC1) ) UDR1;
76		76
77	// enable interrupts at the end	77	// enable interrupts at the end
78	// enable RX-Interrupt	78	// enable RX-Interrupt
79	UCSR1B \|= (1 << RXCIE1);	79	UCSR1B \|= (1 << RXCIE1);
80	// enable TX-Interrupt	80	// enable TX-Interrupt
81	UCSR1B \|= (1 << TXCIE1);	81	UCSR1B \|= (1 << TXCIE1);
82	// enable DRE interrupt	82	// enable DRE interrupt
83	//UCSR1B \|= (1 << UDRIE1);	83	//UCSR1B \|= (1 << UDRIE1);
84		84
85		85
86	// restore global interrupt flags	86	// restore global interrupt flags
87	SREG = sreg;	87	SREG = sreg;
88		88
89	// inint FIFO buffer	89	// inint FIFO buffer
90	//fifo_init (&infifo, inbuf, BUFSIZE_IN);	90	//fifo_init (&infifo, inbuf, BUFSIZE_IN);
91	//fifo_init (&outfifo, outbuf, BUFSIZE_OUT);	91	//fifo_init (&outfifo, outbuf, BUFSIZE_OUT);
92	}	92	}
93		93
94	/*int16_t USART1_putc (const uint8_t c)	94	/*int16_t USART1_putc (const uint8_t c)
95	{	95	{
96	int16_t ret = fifo_put (&outfifo, c);	96	int16_t ret = fifo_put (&outfifo, c);
97	// create an data register empty interrupt	97	// create an data register empty interrupt
98	UCSR1B \|= (1 << UDRIE1);	98	UCSR1B \|= (1 << UDRIE1);
99		99
100	return ret;	100	return ret;
101	}	101	}
102	*/	102	*/
103	/*int16_t USART1_getc_nowait ()	103	/*int16_t USART1_getc_nowait ()
104	{	104	{
105	return fifo_get_nowait (&infifo);	105	return fifo_get_nowait (&infifo);
106	}	106	}
107		107
108		108
109	uint8_t USART1_getc_wait ()	109	uint8_t USART1_getc_wait ()
110	{	110	{
111	return fifo_get_wait (&infifo);	111	return fifo_get_wait (&infifo);
112	}	112	}
113	*/	113	*/
114		114
115	/****************************************************************/	115	/****************************************************************/
116	/* USART1 data register empty ISR */	116	/* USART1 data register empty ISR */
117	/****************************************************************/	117	/****************************************************************/
118	/*ISR(USART1_UDRE_vect)	118	/*ISR(USART1_UDRE_vect)
119	{	119	{
120	// Move a character from the output buffer to the data register.	120	// Move a character from the output buffer to the data register.
121	// When the character was processed the next interrupt is generated.	121	// When the character was processed the next interrupt is generated.
122	// If the output buffer is empty the DRE-interrupt is disabled.	122	// If the output buffer is empty the DRE-interrupt is disabled.
123	if (outfifo.count > 0)	123	if (outfifo.count > 0)
124	UDR1 = _inline_fifo_get (&outfifo);	124	UDR1 = _inline_fifo_get (&outfifo);
125	else	125	else
126	UCSR1B &= ~(1 << UDRIE1);	126	UCSR1B &= ~(1 << UDRIE1);
127	}	127	}
128	*/	128	*/
129		129
130	/****************************************************************/	130	/****************************************************************/
131	/* USART1 transmitter ISR */	131	/* USART1 transmitter ISR */
132	/****************************************************************/	132	/****************************************************************/
133	/*ISR(USART1_TX_vect)	133	/*ISR(USART1_TX_vect)
134	{	134	{
135		135
136	}	136	}
137	*/	137	*/
138	/****************************************************************/	138	/****************************************************************/
139	/* USART1 receiver ISR */	139	/* USART1 receiver ISR */
140	/****************************************************************/	140	/****************************************************************/
141	ISR(USART1_RX_vect)	141	ISR(USART1_RX_vect)
142	{	142	{
143	uint8_t c;	143	uint8_t c;
144	c = UDR1; // get data byte	144	c = UDR1; // get data byte
145	#ifdef USE_KILLAGREG	145	#if defined (USE_KILLAGREG) \|\| defined (USE_MK3MAG)
146	if (BoardRelease == 11) ubx_parser(c); // and put it into the ubx protocol parser	146	if (BoardRelease == 11) ubx_parser(c); // and put it into the ubx protocol parser
147	#endif	147	#endif
148	}	148	}
149		149

Subversion Repositories FlightCtrl

(root)/branches/V0.69k CRK HexaLotte/uart1.c - Rev 903 → 909