WebSVN - FlightCtrl - Diff - Rev 702 and 757 - /branches/V0.68d Code Redesign killagreg/uart1.c


#include <avr/io.h>
#include <avr/interrupt.h>
 
 
#include "main.h"
#include "uart1.h"
#include "fifo.h"
#include "ubx.h"
 
 
 
// FIFO-objects and buffers for input and output
 
//#define BUFSIZE_IN  0x96
//volatile uint8_t inbuf[BUFSIZE_IN];
//fifo_t infifo;
 
#define BUFSIZE_OUT 0x96
volatile uint8_t outbuf[BUFSIZE_OUT];
fifo_t outfifo;
 
/****************************************************************/
/*              Initialization of the USART1                    */
/****************************************************************/
void USART1_Init (void)
{
        // USART1 Control and Status Register A, B, C and baud rate register
        uint8_t sreg = SREG;
        uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1);
 
        // disable all interrupts before reconfiguration
        cli();
 
        // disable RX-Interrupt
        UCSR1B &= ~(1 << RXCIE1);
        // disable TX-Interrupt
        UCSR1B &= ~(1 << TXCIE1);
        // disable DRE-Interrupt
        UCSR1B &= ~(1 << UDRIE1);
 
        // set direction of RXD1 and TXD1 pins
        // set RXD1 (PD2) as an input pin
        PORTD |= (1 << PORTD2);
        DDRD &= ~(1 << DDD2);
 
        // set TXD1 (PD3) as an output pin
        PORTD |= (1 << PORTD3);
        DDRD  |= (1 << DDD3);
 
        // USART0 Baud Rate Register
        // set clock divider
        UBRR1H = (uint8_t)(ubrr>>8);
        UBRR1L = (uint8_t)ubrr;
 
        // enable double speed operation
        UCSR1A |= (1 << U2X1);
        // enable receiver and transmitter
        UCSR1B = (1 << TXEN1) | (1 << RXEN1);
        // set asynchronous mode
        UCSR1C &= ~(1 << UMSEL11);
        UCSR1C &= ~(1 << UMSEL10);
        // no parity
        UCSR1C &= ~(1 << UPM11);
        UCSR1C &= ~(1 << UPM10);
        // 1 stop bit
        UCSR1C &= ~(1 << USBS1);
        // 8-bit
        UCSR1B &= ~(1 << UCSZ12);
        UCSR1C |=  (1 << UCSZ11);
        UCSR1C |=  (1 << UCSZ10);
 
        // flush receive buffer explicit
        while ( UCSR1A & (1<<RXC1) ) UDR1;
 
        // enable interrupts at the end
        // enable RX-Interrupt
        UCSR1B |= (1 << RXCIE1);
        // enable TX-Interrupt
        UCSR1B |= (1 << TXCIE1);
        // enable DRE interrupt
        //UCSR1B |= (1 << UDRIE1);
 
 
        // restore global interrupt flags
    SREG = sreg;
 
    // inint FIFO buffer
        //fifo_init (&infifo,   inbuf, BUFSIZE_IN);
    //fifo_init (&outfifo, outbuf, BUFSIZE_OUT);
}
 
/*int16_t USART1_putc (const uint8_t c)
{
    int16_t ret = fifo_put (&outfifo, c);
    // create an data register empty interrupt
    UCSR1B |= (1 << UDRIE1);
 
    return ret;
}
*/
/*int16_t USART1_getc_nowait ()
{
    return fifo_get_nowait (&infifo);
}
 
 
uint8_t USART1_getc_wait ()
{
    return fifo_get_wait (&infifo);
}
*/
 
/****************************************************************/
/*               USART1 data register empty ISR                 */
/****************************************************************/
/*ISR(USART1_UDRE_vect)
{
// Move a character from the output buffer to the data register.
// When the character was processed the next interrupt is generated.
// If the output buffer is empty the DRE-interrupt is disabled.
    if (outfifo.count > 0)
       UDR1 = _inline_fifo_get (&outfifo);
    else
        UCSR1B &= ~(1 << UDRIE1);
}
*/
 
/****************************************************************/
/*               USART1 transmitter ISR                         */
/****************************************************************/
/*ISR(USART1_TX_vect)
{
 
}
*/
/****************************************************************/
/*               USART1 receiver ISR                            */
/****************************************************************/
ISR(USART1_RX_vect)
{
        uint8_t c;
        c = UDR1; // get data byte
        if (BoardRelease == 11) ubx_parser(c); // and put it into the ubx protocol parser
}
 

Rev 702	Rev 757
1	#include <avr/io.h>	1	#include <avr/io.h>
2	#include <avr/interrupt.h>	2	#include <avr/interrupt.h>
3		3
4		4
5	#include "main.h"	5	#include "main.h"
6	#include "uart1.h"	6	#include "uart1.h"
7	#include "fifo.h"	7	#include "fifo.h"
8	#include "ubx.h"	8	#include "ubx.h"
9		9
10		10
11		11
12	// FIFO-objects and buffers for input and output	12	// FIFO-objects and buffers for input and output
13		13
14	//#define BUFSIZE_IN 0x96	14	//#define BUFSIZE_IN 0x96
15	//volatile uint8_t inbuf[BUFSIZE_IN];	15	//volatile uint8_t inbuf[BUFSIZE_IN];
16	//fifo_t infifo;	16	//fifo_t infifo;
17		17
18	#define BUFSIZE_OUT 0x96	18	#define BUFSIZE_OUT 0x96
19	volatile uint8_t outbuf[BUFSIZE_OUT];	19	volatile uint8_t outbuf[BUFSIZE_OUT];
20	fifo_t outfifo;	20	fifo_t outfifo;
21		21
22	/****************************************************************/	22	/****************************************************************/
23	/* Initialization of the USART1 */	23	/* Initialization of the USART1 */
24	/****************************************************************/	24	/****************************************************************/
25	void USART1_Init (void)	25	void USART1_Init (void)
26	{	26	{
27	// USART1 Control and Status Register A, B, C and baud rate register	27	// USART1 Control and Status Register A, B, C and baud rate register
28	uint8_t sreg = SREG;	28	uint8_t sreg = SREG;
29	uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1);	29	uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1);
30		30
31	// disable all interrupts before reconfiguration	31	// disable all interrupts before reconfiguration
32	cli();	32	cli();
33		33
34	// disable RX-Interrupt	34	// disable RX-Interrupt
35	UCSR1B &= ~(1 << RXCIE1);	35	UCSR1B &= ~(1 << RXCIE1);
36	// disable TX-Interrupt	36	// disable TX-Interrupt
37	UCSR1B &= ~(1 << TXCIE1);	37	UCSR1B &= ~(1 << TXCIE1);
38	// disable DRE-Interrupt	38	// disable DRE-Interrupt
39	UCSR1B &= ~(1 << UDRIE1);	39	UCSR1B &= ~(1 << UDRIE1);
40		40
41	// set direction of RXD1 and TXD1 pins	41	// set direction of RXD1 and TXD1 pins
42	// set RXD1 (PD2) as an input pin	42	// set RXD1 (PD2) as an input pin
43	PORTD \|= (1 << PORTD2);	43	PORTD \|= (1 << PORTD2);
44	DDRD &= ~(1 << DDD2);	44	DDRD &= ~(1 << DDD2);
45		45
46	// set TXD1 (PD3) as an output pin	46	// set TXD1 (PD3) as an output pin
47	PORTD \|= (1 << PORTD3);	47	PORTD \|= (1 << PORTD3);
48	DDRD \|= (1 << DDD3);	48	DDRD \|= (1 << DDD3);
49		49
50	// USART0 Baud Rate Register	50	// USART0 Baud Rate Register
51	// set clock divider	51	// set clock divider
52	UBRR1H = (uint8_t)(ubrr>>8);	52	UBRR1H = (uint8_t)(ubrr>>8);
53	UBRR1L = (uint8_t)ubrr;	53	UBRR1L = (uint8_t)ubrr;
54		54
55	// enable double speed operation	55	// enable double speed operation
56	UCSR1A \|= (1 << U2X1);	56	UCSR1A \|= (1 << U2X1);
57	// enable receiver and transmitter	57	// enable receiver and transmitter
58	UCSR1B = (1 << TXEN1) \| (1 << RXEN1);	58	UCSR1B = (1 << TXEN1) \| (1 << RXEN1);
59	// set asynchronous mode	59	// set asynchronous mode
60	UCSR1C &= ~(1 << UMSEL11);	60	UCSR1C &= ~(1 << UMSEL11);
61	UCSR1C &= ~(1 << UMSEL10);	61	UCSR1C &= ~(1 << UMSEL10);
62	// no parity	62	// no parity
63	UCSR1C &= ~(1 << UPM11);	63	UCSR1C &= ~(1 << UPM11);
64	UCSR1C &= ~(1 << UPM10);	64	UCSR1C &= ~(1 << UPM10);
65	// 1 stop bit	65	// 1 stop bit
66	UCSR1C &= ~(1 << USBS1);	66	UCSR1C &= ~(1 << USBS1);
67	// 8-bit	67	// 8-bit
68	UCSR1B &= ~(1 << UCSZ12);	68	UCSR1B &= ~(1 << UCSZ12);
69	UCSR1C \|= (1 << UCSZ11);	69	UCSR1C \|= (1 << UCSZ11);
70	UCSR1C \|= (1 << UCSZ10);	70	UCSR1C \|= (1 << UCSZ10);
71		71
72	// flush receive buffer explicit	72	// flush receive buffer explicit
73	while ( UCSR1A & (1<<RXC1) ) UDR1;	73	while ( UCSR1A & (1<<RXC1) ) UDR1;
74		74
75	// enable interrupts at the end	75	// enable interrupts at the end
76	// enable RX-Interrupt	76	// enable RX-Interrupt
77	UCSR1B \|= (1 << RXCIE1);	77	UCSR1B \|= (1 << RXCIE1);
78	// enable TX-Interrupt	78	// enable TX-Interrupt
79	UCSR1B \|= (1 << TXCIE1);	79	UCSR1B \|= (1 << TXCIE1);
80	// enable DRE interrupt	80	// enable DRE interrupt
81	//UCSR1B \|= (1 << UDRIE1);	81	//UCSR1B \|= (1 << UDRIE1);
82		82
83		83
84	// restore global interrupt flags	84	// restore global interrupt flags
85	SREG = sreg;	85	SREG = sreg;
86		86
87	// inint FIFO buffer	87	// inint FIFO buffer
88	//fifo_init (&infifo, inbuf, BUFSIZE_IN);	88	//fifo_init (&infifo, inbuf, BUFSIZE_IN);
89	//fifo_init (&outfifo, outbuf, BUFSIZE_OUT);	89	//fifo_init (&outfifo, outbuf, BUFSIZE_OUT);
90	}	90	}
91		91
92	/*int16_t USART1_putc (const uint8_t c)	92	/*int16_t USART1_putc (const uint8_t c)
93	{	93	{
94	int16_t ret = fifo_put (&outfifo, c);	94	int16_t ret = fifo_put (&outfifo, c);
95	// create an data register empty interrupt	95	// create an data register empty interrupt
96	UCSR1B \|= (1 << UDRIE1);	96	UCSR1B \|= (1 << UDRIE1);
97		97
98	return ret;	98	return ret;
99	}	99	}
100	*/	100	*/
101	/*int16_t USART1_getc_nowait ()	101	/*int16_t USART1_getc_nowait ()
102	{	102	{
103	return fifo_get_nowait (&infifo);	103	return fifo_get_nowait (&infifo);
104	}	104	}
105		105
106		106
107	uint8_t USART1_getc_wait ()	107	uint8_t USART1_getc_wait ()
108	{	108	{
109	return fifo_get_wait (&infifo);	109	return fifo_get_wait (&infifo);
110	}	110	}
111	*/	111	*/
112		112
113	/****************************************************************/	113	/****************************************************************/
114	/* USART1 data register empty ISR */	114	/* USART1 data register empty ISR */
115	/****************************************************************/	115	/****************************************************************/
116	/*ISR(USART1_UDRE_vect)	116	/*ISR(USART1_UDRE_vect)
117	{	117	{
118	// Move a character from the output buffer to the data register.	118	// Move a character from the output buffer to the data register.
119	// When the character was processed the next interrupt is generated.	119	// When the character was processed the next interrupt is generated.
120	// If the output buffer is empty the DRE-interrupt is disabled.	120	// If the output buffer is empty the DRE-interrupt is disabled.
121	if (outfifo.count > 0)	121	if (outfifo.count > 0)
122	UDR1 = _inline_fifo_get (&outfifo);	122	UDR1 = _inline_fifo_get (&outfifo);
123	else	123	else
124	UCSR1B &= ~(1 << UDRIE1);	124	UCSR1B &= ~(1 << UDRIE1);
125	}	125	}
126	*/	126	*/
127		127
128	/****************************************************************/	128	/****************************************************************/
129	/* USART1 transmitter ISR */	129	/* USART1 transmitter ISR */
130	/****************************************************************/	130	/****************************************************************/
131	/*ISR(USART1_TX_vect)	131	/*ISR(USART1_TX_vect)
132	{	132	{
133		133
134	}	134	}
135	*/	135	*/
136	/****************************************************************/	136	/****************************************************************/
137	/* USART1 receiver ISR */	137	/* USART1 receiver ISR */
138	/****************************************************************/	138	/****************************************************************/
139	ISR(USART1_RX_vect)	139	ISR(USART1_RX_vect)
140	{	140	{
141	uint8_t c;	141	uint8_t c;
142	c = UDR1; // get data byte	142	c = UDR1; // get data byte
143	ubx_parser(c); // and put it into the ubx protocol parser	143	if (BoardRelease == 11) ubx_parser(c); // and put it into the ubx protocol parser
144	}	144	}
145		145

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(root)/branches/V0.68d Code Redesign killagreg/uart1.c @ 894 - Rev 702 → 757