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1 | #include <avr/io.h> |
1 | #include <avr/io.h> |
2 | #include <avr/interrupt.h> |
2 | #include <avr/interrupt.h> |
3 | 3 | ||
4 | 4 | ||
5 | #include "main.h" |
5 | #include "main.h" |
6 | #include "uart1.h" |
6 | #include "uart1.h" |
7 | #include "fifo.h" |
7 | #include "fifo.h" |
8 | #include "ubx.h" |
8 | #include "ubx.h" |
9 | 9 | ||
10 | 10 | ||
11 | 11 | ||
12 | // FIFO-objects and buffers for input and output |
12 | // FIFO-objects and buffers for input and output |
13 | 13 | ||
14 | //#define BUFSIZE_IN 0x96 |
14 | //#define BUFSIZE_IN 0x96 |
15 | //volatile uint8_t inbuf[BUFSIZE_IN]; |
15 | //volatile uint8_t inbuf[BUFSIZE_IN]; |
16 | //fifo_t infifo; |
16 | //fifo_t infifo; |
17 | 17 | ||
18 | #define BUFSIZE_OUT 0x96 |
18 | #define BUFSIZE_OUT 0x96 |
19 | volatile uint8_t outbuf[BUFSIZE_OUT]; |
19 | volatile uint8_t outbuf[BUFSIZE_OUT]; |
20 | fifo_t outfifo; |
20 | fifo_t outfifo; |
21 | 21 | ||
22 | /****************************************************************/ |
22 | /****************************************************************/ |
23 | /* Initialization of the USART1 */ |
23 | /* Initialization of the USART1 */ |
24 | /****************************************************************/ |
24 | /****************************************************************/ |
25 | void USART1_Init (void) |
25 | void USART1_Init (void) |
26 | { |
26 | { |
27 | // USART1 Control and Status Register A, B, C and baud rate register |
27 | // USART1 Control and Status Register A, B, C and baud rate register |
28 | uint8_t sreg = SREG; |
28 | uint8_t sreg = SREG; |
29 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
29 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
30 | 30 | ||
31 | // disable all interrupts before reconfiguration |
31 | // disable all interrupts before reconfiguration |
32 | cli(); |
32 | cli(); |
33 | 33 | ||
34 | // disable RX-Interrupt |
34 | // disable RX-Interrupt |
35 | UCSR1B &= ~(1 << RXCIE1); |
35 | UCSR1B &= ~(1 << RXCIE1); |
36 | // disable TX-Interrupt |
36 | // disable TX-Interrupt |
37 | UCSR1B &= ~(1 << TXCIE1); |
37 | UCSR1B &= ~(1 << TXCIE1); |
38 | // disable DRE-Interrupt |
38 | // disable DRE-Interrupt |
39 | UCSR1B |= (1 << UDRIE1); |
39 | UCSR1B |= (1 << UDRIE1); |
40 | 40 | ||
41 | // disable receiver and transmitter (will flush the buffers) |
41 | // disable receiver and transmitter (will flush the buffers) |
42 | UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1)); |
42 | UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1)); |
43 | 43 | ||
44 | // set direction of RXD1 and TXD1 pins |
44 | // set direction of RXD1 and TXD1 pins |
45 | // set RXD1 (PD2) as an input pin |
45 | // set RXD1 (PD2) as an input pin |
46 | PORTD |= (1 << PORTD2); |
- | |
47 | DDRD &= ~(1 << DDD2); |
46 | DDRD &= ~(1 << DDD2); |
- | 47 | PORTD |= (1 << PORTD2); |
|
- | 48 | ||
48 | // set TXD1 (PD3) as an output pin |
49 | // set TXD1 (PD3) as an output pin |
- | 50 | DDRD |= (1 << DDD3); |
|
49 | PORTD |= (1 << PORTD3); |
51 | PORTD |= (1 << PORTD3); |
50 | DDRD |= (1 << DDD3); |
- | |
51 | 52 | ||
52 | // USART0 Baud Rate Register |
53 | // USART0 Baud Rate Register |
53 | // set clock divider |
54 | // set clock divider |
54 | UBRR1H = (uint8_t)(ubrr>>8); |
55 | UBRR1H = (uint8_t)(ubrr>>8); |
55 | UBRR1L = (uint8_t)ubrr; |
56 | UBRR1L = (uint8_t)ubrr; |
56 | 57 | ||
57 | // enable double speed operation |
58 | // enable double speed operation |
58 | UCSR1A |= (1 << U2X1); |
59 | UCSR1A |= (1 << U2X1); |
59 | // enable receiver and transmitter |
60 | // enable receiver and transmitter |
60 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
61 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
61 | // set asynchronous mode |
62 | // set asynchronous mode |
62 | UCSR1C &= ~(1 << UMSEL11); |
63 | UCSR1C &= ~(1 << UMSEL11); |
63 | UCSR1C &= ~(1 << UMSEL10); |
64 | UCSR1C &= ~(1 << UMSEL10); |
64 | // no parity |
65 | // no parity |
65 | UCSR1C &= ~(1 << UPM11); |
66 | UCSR1C &= ~(1 << UPM11); |
66 | UCSR1C &= ~(1 << UPM10); |
67 | UCSR1C &= ~(1 << UPM10); |
67 | // 1 stop bit |
68 | // 1 stop bit |
68 | UCSR1C &= ~(1 << USBS1); |
69 | UCSR1C &= ~(1 << USBS1); |
69 | // 8-bit |
70 | // 8-bit |
70 | UCSR1B &= ~(1 << UCSZ12); |
71 | UCSR1B &= ~(1 << UCSZ12); |
71 | UCSR1C |= (1 << UCSZ11); |
72 | UCSR1C |= (1 << UCSZ11); |
72 | UCSR1C |= (1 << UCSZ10); |
73 | UCSR1C |= (1 << UCSZ10); |
73 | 74 | ||
74 | // flush receive buffer explicit |
75 | // flush receive buffer explicit |
75 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
76 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
76 | 77 | ||
77 | // enable interrupts at the end |
78 | // enable interrupts at the end |
78 | // enable RX-Interrupt |
79 | // enable RX-Interrupt |
79 | UCSR1B |= (1 << RXCIE1); |
80 | UCSR1B |= (1 << RXCIE1); |
80 | // enable TX-Interrupt |
81 | // enable TX-Interrupt |
81 | //UCSR1B |= (1 << TXCIE1); |
82 | //UCSR1B |= (1 << TXCIE1); |
82 | // enable DRE interrupt |
83 | // enable DRE interrupt |
83 | //UCSR1B |= (1 << UDRIE1); |
84 | //UCSR1B |= (1 << UDRIE1); |
84 | 85 | ||
85 | 86 | ||
86 | // restore global interrupt flags |
87 | // restore global interrupt flags |
87 | SREG = sreg; |
88 | SREG = sreg; |
88 | 89 | ||
89 | // inint FIFO buffer |
90 | // inint FIFO buffer |
90 | //fifo_init (&infifo, inbuf, BUFSIZE_IN); |
91 | //fifo_init (&infifo, inbuf, BUFSIZE_IN); |
91 | fifo_init (&outfifo, outbuf, BUFSIZE_OUT); |
92 | fifo_init (&outfifo, outbuf, BUFSIZE_OUT); |
92 | } |
93 | } |
93 | 94 | ||
94 | int16_t USART1_putc (const uint8_t c) |
95 | int16_t USART1_putc (const uint8_t c) |
95 | { |
96 | { |
96 | int16_t ret = fifo_put (&outfifo, c); |
97 | int16_t ret = fifo_put (&outfifo, c); |
97 | // create an data register empty interrupt |
98 | // create an data register empty interrupt |
98 | UCSR1B |= (1 << UDRIE1); |
99 | UCSR1B |= (1 << UDRIE1); |
99 | 100 | ||
100 | return ret; |
101 | return ret; |
101 | } |
102 | } |
102 | 103 | ||
103 | /*int16_t USART1_getc_nowait () |
104 | /*int16_t USART1_getc_nowait () |
104 | { |
105 | { |
105 | return fifo_get_nowait (&infifo); |
106 | return fifo_get_nowait (&infifo); |
106 | } |
107 | } |
107 | 108 | ||
108 | 109 | ||
109 | uint8_t USART1_getc_wait () |
110 | uint8_t USART1_getc_wait () |
110 | { |
111 | { |
111 | return fifo_get_wait (&infifo); |
112 | return fifo_get_wait (&infifo); |
112 | } |
113 | } |
113 | */ |
114 | */ |
114 | 115 | ||
115 | /****************************************************************/ |
116 | /****************************************************************/ |
116 | /* USART1 data register empty ISR */ |
117 | /* USART1 data register empty ISR */ |
117 | /****************************************************************/ |
118 | /****************************************************************/ |
118 | ISR(USART1_UDRE_vect) |
119 | ISR(USART1_UDRE_vect) |
119 | { |
120 | { |
120 | // Move a character from the output buffer to the data register. |
121 | // Move a character from the output buffer to the data register. |
121 | // When the character was processed the next interrupt is generated. |
122 | // When the character was processed the next interrupt is generated. |
122 | // If the output buffer is empty the DRE-interrupt is disabled. |
123 | // If the output buffer is empty the DRE-interrupt is disabled. |
123 | if (outfifo.count > 0) |
124 | if (outfifo.count > 0) |
124 | UDR1 = _inline_fifo_get (&outfifo); |
125 | UDR1 = _inline_fifo_get (&outfifo); |
125 | else |
126 | else |
126 | UCSR1B &= ~(1 << UDRIE1); |
127 | UCSR1B &= ~(1 << UDRIE1); |
127 | } |
128 | } |
128 | 129 | ||
129 | /****************************************************************/ |
130 | /****************************************************************/ |
130 | /* USART1 transmitter ISR */ |
131 | /* USART1 transmitter ISR */ |
131 | /****************************************************************/ |
132 | /****************************************************************/ |
132 | ISR(USART1_TX_vect) |
133 | ISR(USART1_TX_vect) |
133 | { |
134 | { |
134 | 135 | ||
135 | } |
136 | } |
136 | 137 | ||
137 | /****************************************************************/ |
138 | /****************************************************************/ |
138 | /* USART1 receiver ISR */ |
139 | /* USART1 receiver ISR */ |
139 | /****************************************************************/ |
140 | /****************************************************************/ |
140 | ISR(USART1_RX_vect) |
141 | ISR(USART1_RX_vect) |
141 | { |
142 | { |
142 | uint8_t c; |
143 | uint8_t c; |
143 | c = UDR0; // get data byte |
144 | c = UDR0; // get data byte |
144 | ubx_parser(c); // and put it into the ubx protocol parser |
145 | ubx_parser(c); // and put it into the ubx protocol parser |
145 | } |
146 | } |
146 | 147 |