WebSVN - FlightCtrl - Diff - Rev 684 and 687 - /branches/V0.68d Code Redesign killagreg/uart1.c


#include <avr/io.h>
#include <avr/interrupt.h>
 
 
#include "main.h"
#include "uart1.h"
#include "fifo.h"
#include "ubx.h"
 
 
 
// FIFO-objects and buffers for input and output
 
//#define BUFSIZE_IN  0x96
//volatile uint8_t inbuf[BUFSIZE_IN];
//fifo_t infifo;
 
#define BUFSIZE_OUT 0x96
volatile uint8_t outbuf[BUFSIZE_OUT];
fifo_t outfifo;
 
/****************************************************************/
/*              Initialization of the USART1                    */
/****************************************************************/
void USART1_Init (void)
{
        // USART1 Control and Status Register A, B, C and baud rate register
        uint8_t sreg = SREG;
        uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1);
 
        // disable all interrupts before reconfiguration
        cli();
 
        // disable RX-Interrupt
        UCSR1B &= ~(1 << RXCIE1);
        // disable TX-Interrupt
        UCSR1B &= ~(1 << TXCIE1);
        // disable DRE-Interrupt
        UCSR1B |= (1 << UDRIE1);
 
        // disable receiver and transmitter (will flush the buffers)
        UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1));
 
        // set direction of RXD1 and TXD1 pins
        // set RXD1 (PD2) as an input pin
        PORTD |= (1 << PORTD2);
        DDRD &= ~(1 << DDD2);
        // set TXD1 (PD3) as an output pin
        PORTD |= (1 << PORTD3);
        DDRD |=  (1 << DDD3);
 
        // USART0 Baud Rate Register
        // set clock divider
        UBRR1H = (uint8_t)(ubrr>>8);
        UBRR1L = (uint8_t)ubrr;
 
        // enable double speed operation
        UCSR1A |= (1 << U2X1);
        // enable receiver and transmitter
        UCSR1B = (1 << TXEN1) | (1 << RXEN1);
        // set asynchronous mode
        UCSR1C &= ~(1 << UMSEL11);
        UCSR1C &= ~(1 << UMSEL10);
        // no parity
        UCSR1C &= ~(1 << UPM11);
        UCSR1C &= ~(1 << UPM10);
        // 1 stop bit
        UCSR1C &= ~(1 << USBS1);
        // 8-bit
        UCSR1B &= ~(1 << UCSZ12);
        UCSR1C |=  (1 << UCSZ11);
        UCSR1C |=  (1 << UCSZ10);
 
        // flush receive buffer explicit
        while ( UCSR1A & (1<<RXC1) ) UDR1;
 
        // enable interrupts at the end
        // enable RX-Interrupt
        UCSR1B |= (1 << RXCIE1);
        // enable TX-Interrupt
        //UCSR1B |= (1 << TXCIE1);
        // enable DRE interrupt
        //UCSR1B |= (1 << UDRIE1);
 
 
        // restore global interrupt flags
    SREG = sreg;
 
    // inint FIFO buffer
        //fifo_init (&infifo,   inbuf, BUFSIZE_IN);
    fifo_init (&outfifo, outbuf, BUFSIZE_OUT);
}
 
int16_t USART1_putc (const uint8_t c)
{
    int16_t ret = fifo_put (&outfifo, c);
    // create an data register empty interrupt
    UCSR1B |= (1 << UDRIE1);
 
    return ret;
}
 
/*int16_t USART1_getc_nowait ()
{
    return fifo_get_nowait (&infifo);
}
 
 
uint8_t USART1_getc_wait ()
{
    return fifo_get_wait (&infifo);
}
*/
 
/****************************************************************/
/*               USART1 data register empty ISR                 */
/****************************************************************/
ISR(USART1_UDRE_vect)
{
// Move a character from the output buffer to the data register.
// When the character was processed the next interrupt is generated.
// If the output buffer is empty the DRE-interrupt is disabled.
    if (outfifo.count > 0)
       UDR1 = _inline_fifo_get (&outfifo);
    else
        UCSR1B &= ~(1 << UDRIE1);
}
 
/****************************************************************/
/*               USART1 transmitter ISR                         */
/****************************************************************/
ISR(USART1_TX_vect)
{
 
}
 
/****************************************************************/
/*               USART1 receiver ISR                            */
/****************************************************************/
ISR(USART1_RX_vect)
{
        uint8_t c;
        c = UDR0; // get data byte
        ubx_parser(c); // and put it into the ubx protocol parser
}
 

Rev 684	Rev 687
-		1	#include <avr/io.h>
-		2	#include <avr/interrupt.h>
-		3
-		4
1	#include "main.h"	5	#include "main.h"
2	#include "uart1.h"	6	#include "uart1.h"
3	#include "fifo.h"	7	#include "fifo.h"
4	#include "ubx.h"	8	#include "ubx.h"
5		9
6		10
7		11
8	// FIFO-objects and buffers for input and output	12	// FIFO-objects and buffers for input and output
9		13
10	//#define BUFSIZE_IN 0x96	14	//#define BUFSIZE_IN 0x96
11	//volatile uint8_t inbuf[BUFSIZE_IN];	15	//volatile uint8_t inbuf[BUFSIZE_IN];
12	//fifo_t infifo;	16	//fifo_t infifo;
13		17
14	#define BUFSIZE_OUT 0x96	18	#define BUFSIZE_OUT 0x96
15	volatile uint8_t outbuf[BUFSIZE_OUT];	19	volatile uint8_t outbuf[BUFSIZE_OUT];
16	fifo_t outfifo;	20	fifo_t outfifo;
17		21
18	/****************************************************************/	22	/****************************************************************/
19	/* Initialization of the USART1 */	23	/* Initialization of the USART1 */
20	/****************************************************************/	24	/****************************************************************/
21	void USART1_Init (void)	25	void USART1_Init (void)
22	{	26	{
23	// USART1 Control and Status Register A, B, C and baud rate register	27	// USART1 Control and Status Register A, B, C and baud rate register
24	uint8_t sreg = SREG;	28	uint8_t sreg = SREG;
25	uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1);	29	uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1);
26		30
27	// disable all interrupts before reconfiguration	31	// disable all interrupts before reconfiguration
28	cli();	32	cli();
29		33
30	// disable RX-Interrupt	34	// disable RX-Interrupt
31	UCSR1B &= ~(1 << RXCIE1);	35	UCSR1B &= ~(1 << RXCIE1);
32	// disable TX-Interrupt	36	// disable TX-Interrupt
33	UCSR1B &= ~(1 << TXCIE1);	37	UCSR1B &= ~(1 << TXCIE1);
34	// disable DRE-Interrupt	38	// disable DRE-Interrupt
35	UCSR1B \|= (1 << UDRIE1);	39	UCSR1B \|= (1 << UDRIE1);
36		40
37	// disable receiver and transmitter (will flush the buffers)	41	// disable receiver and transmitter (will flush the buffers)
38	UCSR1B &= ~((1 << TXEN1) \| (1 << RXEN1));	42	UCSR1B &= ~((1 << TXEN1) \| (1 << RXEN1));
39		43
40	// set direction of RXD1 and TXD1 pins	44	// set direction of RXD1 and TXD1 pins
41	// set RXD1 (PD2) as an input pin	45	// set RXD1 (PD2) as an input pin
42	PORTD \|= (1 << PORTD2);	46	PORTD \|= (1 << PORTD2);
43	DDRD &= ~(1 << DDD2);	47	DDRD &= ~(1 << DDD2);
44	// set TXD1 (PD3) as an output pin	48	// set TXD1 (PD3) as an output pin
45	PORTD \|= (1 << PORTD3);	49	PORTD \|= (1 << PORTD3);
46	DDRD \|= (1 << DDD3);	50	DDRD \|= (1 << DDD3);
47		51
48	// USART0 Baud Rate Register	52	// USART0 Baud Rate Register
49	// set clock divider	53	// set clock divider
50	UBRR1H = (uint8_t)(ubrr>>8);	54	UBRR1H = (uint8_t)(ubrr>>8);
51	UBRR1L = (uint8_t)ubrr;	55	UBRR1L = (uint8_t)ubrr;
52		56
53	// enable double speed operation	57	// enable double speed operation
54	UCSR1A \|= (1 << U2X1);	58	UCSR1A \|= (1 << U2X1);
55	// enable receiver and transmitter	59	// enable receiver and transmitter
56	UCSR1B = (1 << TXEN1) \| (1 << RXEN1);	60	UCSR1B = (1 << TXEN1) \| (1 << RXEN1);
57	// set asynchronous mode	61	// set asynchronous mode
58	UCSR1C &= ~(1 << UMSEL11);	62	UCSR1C &= ~(1 << UMSEL11);
59	UCSR1C &= ~(1 << UMSEL10);	63	UCSR1C &= ~(1 << UMSEL10);
60	// no parity	64	// no parity
61	UCSR1C &= ~(1 << UPM11);	65	UCSR1C &= ~(1 << UPM11);
62	UCSR1C &= ~(1 << UPM10);	66	UCSR1C &= ~(1 << UPM10);
63	// 1 stop bit	67	// 1 stop bit
64	UCSR1C &= ~(1 << USBS1);	68	UCSR1C &= ~(1 << USBS1);
65	// 8-bit	69	// 8-bit
66	UCSR1B &= ~(1 << UCSZ12);	70	UCSR1B &= ~(1 << UCSZ12);
67	UCSR1C \|= (1 << UCSZ11);	71	UCSR1C \|= (1 << UCSZ11);
68	UCSR1C \|= (1 << UCSZ10);	72	UCSR1C \|= (1 << UCSZ10);
69		73
70	// flush receive buffer explicit	74	// flush receive buffer explicit
71	while ( UCSR1A & (1<<RXC1) ) UDR1;	75	while ( UCSR1A & (1<<RXC1) ) UDR1;
72		76
73	// enable interrupts at the end	77	// enable interrupts at the end
74	// enable RX-Interrupt	78	// enable RX-Interrupt
75	UCSR1B \|= (1 << RXCIE1);	79	UCSR1B \|= (1 << RXCIE1);
76	// enable TX-Interrupt	80	// enable TX-Interrupt
77	//UCSR1B \|= (1 << TXCIE1);	81	//UCSR1B \|= (1 << TXCIE1);
78	// enable DRE interrupt	82	// enable DRE interrupt
79	//UCSR1B \|= (1 << UDRIE1);	83	//UCSR1B \|= (1 << UDRIE1);
80		84
81		85
82	// restore global interrupt flags	86	// restore global interrupt flags
83	SREG = sreg;	87	SREG = sreg;
84		88
85	// inint FIFO buffer	89	// inint FIFO buffer
86	//fifo_init (&infifo, inbuf, BUFSIZE_IN);	90	//fifo_init (&infifo, inbuf, BUFSIZE_IN);
87	fifo_init (&outfifo, outbuf, BUFSIZE_OUT);	91	fifo_init (&outfifo, outbuf, BUFSIZE_OUT);
88	}	92	}
89		93
90	int16_t USART1_putc (const uint8_t c)	94	int16_t USART1_putc (const uint8_t c)
91	{	95	{
92	int16_t ret = fifo_put (&outfifo, c);	96	int16_t ret = fifo_put (&outfifo, c);
93	// create an data register empty interrupt	97	// create an data register empty interrupt
94	UCSR1B \|= (1 << UDRIE1);	98	UCSR1B \|= (1 << UDRIE1);
95		99
96	return ret;	100	return ret;
97	}	101	}
98		102
99	/*int16_t USART1_getc_nowait ()	103	/*int16_t USART1_getc_nowait ()
100	{	104	{
101	return fifo_get_nowait (&infifo);	105	return fifo_get_nowait (&infifo);
102	}	106	}
103		107
104		108
105	uint8_t USART1_getc_wait ()	109	uint8_t USART1_getc_wait ()
106	{	110	{
107	return fifo_get_wait (&infifo);	111	return fifo_get_wait (&infifo);
108	}	112	}
109	*/	113	*/
110		114
111	/****************************************************************/	115	/****************************************************************/
112	/* USART1 data register empty ISR */	116	/* USART1 data register empty ISR */
113	/****************************************************************/	117	/****************************************************************/
114	ISR(USART1_UDRE_vect)	118	ISR(USART1_UDRE_vect)
115	{	119	{
116	// Move a character from the output buffer to the data register.	120	// Move a character from the output buffer to the data register.
117	// When the character was processed the next interrupt is generated.	121	// When the character was processed the next interrupt is generated.
118	// If the output buffer is empty the DRE-interrupt is disabled.	122	// If the output buffer is empty the DRE-interrupt is disabled.
119	if (outfifo.count > 0)	123	if (outfifo.count > 0)
120	UDR1 = _inline_fifo_get (&outfifo);	124	UDR1 = _inline_fifo_get (&outfifo);
121	else	125	else
122	UCSR1B &= ~(1 << UDRIE1);	126	UCSR1B &= ~(1 << UDRIE1);
123	}	127	}
124		128
125	/****************************************************************/	129	/****************************************************************/
126	/* USART1 transmitter ISR */	130	/* USART1 transmitter ISR */
127	/****************************************************************/	131	/****************************************************************/
128	ISR(USART1_TX_vect)	132	ISR(USART1_TX_vect)
129	{	133	{
130		134
131	}	135	}
132		136
133	/****************************************************************/	137	/****************************************************************/
134	/* USART1 receiver ISR */	138	/* USART1 receiver ISR */
135	/****************************************************************/	139	/****************************************************************/
136	ISR(USART1_RX_vect)	140	ISR(USART1_RX_vect)
137	{	141	{
138	uint8_t c;	142	uint8_t c;
139	c = UDR0; // get data byte	143	c = UDR0; // get data byte
140	ubx_parser(c); // and put it into the ubx protocol parser	144	ubx_parser(c); // and put it into the ubx protocol parser
141	}	145	}
142		146

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(root)/branches/V0.68d Code Redesign killagreg/uart1.c - Rev 684 → 687