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1 | #include <avr/io.h> |
1 | #include <avr/io.h> |
2 | #include <avr/interrupt.h> |
2 | #include <avr/interrupt.h> |
3 | 3 | ||
4 | #include "main.h" |
4 | #include "main.h" |
5 | #include "uart1.h" |
5 | #include "uart1.h" |
6 | #include "ubx.h" |
6 | #include "ubx.h" |
7 | 7 | ||
8 | 8 | ||
9 | /****************************************************************/ |
9 | /****************************************************************/ |
10 | /* Initialization of the USART1 */ |
10 | /* Initialization of the USART1 */ |
11 | /****************************************************************/ |
11 | /****************************************************************/ |
12 | void USART1_Init (void) |
12 | void USART1_Init (void) |
13 | { |
13 | { |
14 | // USART1 Control and Status Register A, B, C and baud rate register |
14 | // USART1 Control and Status Register A, B, C and baud rate register |
15 | uint8_t sreg = SREG; |
15 | uint8_t sreg = SREG; |
16 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
16 | uint16_t ubrr = (uint16_t) ((uint32_t) SYSCLK/(8 * USART1_BAUD) - 1); |
17 | 17 | ||
18 | // disable all interrupts before reconfiguration |
18 | // disable all interrupts before reconfiguration |
19 | cli(); |
19 | cli(); |
20 | 20 | ||
21 | // disable RX-Interrupt |
21 | // disable RX-Interrupt |
22 | UCSR1B &= ~(1 << RXCIE1); |
22 | UCSR1B &= ~(1 << RXCIE1); |
23 | // disable TX-Interrupt |
23 | // disable TX-Interrupt |
24 | UCSR1B &= ~(1 << TXCIE1); |
24 | UCSR1B &= ~(1 << TXCIE1); |
25 | // disable DRE-Interrupt |
25 | // disable DRE-Interrupt |
26 | UCSR1B &= ~(1 << UDRIE1); |
26 | UCSR1B &= ~(1 << UDRIE1); |
27 | 27 | ||
28 | // set direction of RXD1 and TXD1 pins |
28 | // set direction of RXD1 and TXD1 pins |
29 | // set RXD1 (PD2) as an input pin |
29 | // set RXD1 (PD2) as an input pin |
30 | PORTD |= (1 << PORTD2); |
30 | PORTD |= (1 << PORTD2); |
31 | DDRD &= ~(1 << DDD2); |
31 | DDRD &= ~(1 << DDD2); |
32 | 32 | ||
33 | // set TXD1 (PD3) as an output pin |
33 | // set TXD1 (PD3) as an output pin |
34 | PORTD |= (1 << PORTD3); |
34 | PORTD |= (1 << PORTD3); |
35 | DDRD |= (1 << DDD3); |
35 | DDRD |= (1 << DDD3); |
36 | 36 | ||
37 | // USART0 Baud Rate Register |
37 | // USART0 Baud Rate Register |
38 | // set clock divider |
38 | // set clock divider |
39 | UBRR1H = (uint8_t)(ubrr>>8); |
39 | UBRR1H = (uint8_t)(ubrr>>8); |
40 | UBRR1L = (uint8_t)ubrr; |
40 | UBRR1L = (uint8_t)ubrr; |
41 | 41 | ||
42 | // enable double speed operation |
42 | // enable double speed operation |
43 | UCSR1A |= (1 << U2X1); |
43 | UCSR1A |= (1 << U2X1); |
44 | // enable receiver and transmitter |
44 | // enable receiver and transmitter |
45 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
45 | UCSR1B = (1 << TXEN1) | (1 << RXEN1); |
46 | // set asynchronous mode |
46 | // set asynchronous mode |
47 | UCSR1C &= ~(1 << UMSEL11); |
47 | UCSR1C &= ~(1 << UMSEL11); |
48 | UCSR1C &= ~(1 << UMSEL10); |
48 | UCSR1C &= ~(1 << UMSEL10); |
49 | // no parity |
49 | // no parity |
50 | UCSR1C &= ~(1 << UPM11); |
50 | UCSR1C &= ~(1 << UPM11); |
51 | UCSR1C &= ~(1 << UPM10); |
51 | UCSR1C &= ~(1 << UPM10); |
52 | // 1 stop bit |
52 | // 1 stop bit |
53 | UCSR1C &= ~(1 << USBS1); |
53 | UCSR1C &= ~(1 << USBS1); |
54 | // 8-bit |
54 | // 8-bit |
55 | UCSR1B &= ~(1 << UCSZ12); |
55 | UCSR1B &= ~(1 << UCSZ12); |
56 | UCSR1C |= (1 << UCSZ11); |
56 | UCSR1C |= (1 << UCSZ11); |
57 | UCSR1C |= (1 << UCSZ10); |
57 | UCSR1C |= (1 << UCSZ10); |
58 | 58 | ||
59 | // flush receive buffer explicit |
59 | // flush receive buffer explicit |
60 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
60 | while ( UCSR1A & (1<<RXC1) ) UDR1; |
61 | 61 | ||
62 | // enable interrupts at the end |
62 | // enable interrupts at the end |
63 | // enable RX-Interrupt |
63 | // enable RX-Interrupt |
64 | UCSR1B |= (1 << RXCIE1); |
64 | UCSR1B |= (1 << RXCIE1); |
65 | // enable TX-Interrupt |
65 | // enable TX-Interrupt |
66 | UCSR1B |= (1 << TXCIE1); |
66 | UCSR1B |= (1 << TXCIE1); |
67 | // enable DRE interrupt |
67 | // enable DRE interrupt |
68 | //UCSR1B |= (1 << UDRIE1); |
68 | //UCSR1B |= (1 << UDRIE1); |
69 | 69 | ||
70 | 70 | ||
71 | // restore global interrupt flags |
71 | // restore global interrupt flags |
72 | SREG = sreg; |
72 | SREG = sreg; |
73 | 73 | ||
74 | } |
74 | } |
75 | 75 | ||
76 | /****************************************************************/ |
76 | /****************************************************************/ |
77 | /* USART1 transmitter ISR */ |
77 | /* USART1 transmitter ISR */ |
78 | /****************************************************************/ |
78 | /****************************************************************/ |
79 | /*ISR(USART1_TX_vect) |
79 | /*ISR(USART1_TX_vect) |
80 | { |
80 | { |
81 | 81 | ||
82 | } |
82 | } |
83 | */ |
83 | */ |
84 | /****************************************************************/ |
84 | /****************************************************************/ |
85 | /* USART1 receiver ISR */ |
85 | /* USART1 receiver ISR */ |
86 | /****************************************************************/ |
86 | /****************************************************************/ |
87 | ISR(USART1_RX_vect) |
87 | ISR(USART1_RX_vect) |
88 | { |
88 | { |
89 | uint8_t c; |
89 | uint8_t c; |
90 | c = UDR1; // get data byte |
90 | c = UDR1; // get data byte |
91 | 91 | ||
92 | ubx_parser(c); // and put it into the ubx protocol parser |
92 | UBX_Parser(c); // and put it into the ubx protocol parser |
93 | 93 | ||
94 | } |
94 | } |
95 | 95 |