WebSVN - Projects - Diff - Rev 426 and 434


 
#include <stdlib.h>
#include <avr/io.h>
#include <avr/interrupt.h>
 
#include "analog.h"
#include "printf_P.h"
 
volatile uint16_t Adc0, Adc1, Adc2, Adc3, Adc4, Adc5, Adc6, Adc7;
volatile uint8_t ADReady = 1;
 
/*****************************************************/
/*     Initialize Analog Digital Converter           */
/*****************************************************/
void ADC_Init(void)
{
        uint8_t sreg = SREG;
        printf("\r\n ADC init...");
        // disable all interrupts before reconfiguration
        cli();
        //ADC0 ... ADC7 is connected to PortA pin 0 ... 7
        DDRA = 0x00;
        PORTA = 0x00;
        // Digital Input Disable Register 0
        // Disable digital input buffer for analog adc_channel pins
        DIDR0 = 0xFF;
        // external reference AREF, adjust data to the right
    ADMUX &= ~((1 << REFS1)|(1 << REFS0)|(1 << ADLAR));
    // set muxer to ADC adc_channel 0 (0 to 7 is a valid choice)
    ADMUX = (ADMUX & 0xE0) | 0x00;
    //Set ADC Control and Status Register A
    //Auto Trigger Enable, Prescaler Select Bits to Division Factor 128, i.e. ADC clock = SYSCKL/128 = 156.25 kHz
        ADCSRA = (0<<ADEN)|(0<<ADSC)|(0<<ADATE)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0)|(0<<ADIE);
        //Set ADC Control and Status Register B
        //Trigger Source to Free Running Mode
        ADCSRB &= ~((1 << ADTS2)|(1 << ADTS1)|(1 << ADTS0));
        // Start AD conversion
        ADC_Enable();
    // restore global interrupt flags
    SREG = sreg;
        sei();
    printf("ok");
}
 
/*****************************************************/
/*     Interrupt Service Routine for ADC             */
/*****************************************************/
// runs at 312.5 kHz or 3.2 µs
// if after (60.8µs) all 19 states are processed the interrupt is disabled
// and the update of further ads is stopped
 
 
#define ADC0    0
#define ADC1    1
#define ADC2    2
#define ADC3    3
#define ADC4    4
#define ADC5    5
#define ADC6    6
#define ADC7    7
 
ISR(ADC_vect)
{
    static uint8_t ad_channel = ADC0, state = 0;
 
    // state machine
        switch(state++)
        {
                case 0:
                        Adc0 = ADC;
                        ad_channel = ADC1;
                        break;
                case 1:
                        Adc1 = ADC;
                        ad_channel = ADC2;
                        break;
                case 2:
                        Adc2 = ADC;
                        ad_channel = ADC3;
                        break;
                case 3:
                        Adc3 = ADC;
                        ad_channel = ADC4;
            break;
                case 4:
                        Adc4 = ADC;
                        ad_channel = ADC5;
                        break;
                case 5:
                        Adc5 = ADC;
                        ad_channel = ADC6;
                        break;
                case 6:
                        Adc6 = ADC;
                        ad_channel = ADC7;
                        break;
                case 7:
                        Adc7 = ADC;
                        ad_channel = ADC0;
                        state = 0;
                        ADReady = 1;
            break;
                default:
                        ad_channel = ADC0;
                        state = 0;
                        ADReady = 1;
                        break;
        }
    // set adc muxer to next ad_channel
    ADMUX = (ADMUX & 0xE0) | ad_channel;
    // after full cycle stop further interrupts
    if(state != 0) ADC_Enable();
}
 

Rev 426	Rev 434
1		1
2	#include <stdlib.h>	2	#include <stdlib.h>
3	#include <avr/io.h>	3	#include <avr/io.h>
4	#include <avr/interrupt.h>	4	#include <avr/interrupt.h>
5		-
6	#include "analog.h"	5	#include "analog.h"
-		6	#include "printf_P.h"
7		7
8	volatile uint16_t Adc0, Adc1, Adc2, Adc3, Adc4, Adc5, Adc6, Adc7;	8	volatile uint16_t Adc0, Adc1, Adc2, Adc3, Adc4, Adc5, Adc6, Adc7;
9	volatile uint8_t ADReady = 1;	9	volatile uint8_t ADReady = 1;
10		10
11	/*****************************************************/	11	/*****************************************************/
12	/* Initialize Analog Digital Converter */	12	/* Initialize Analog Digital Converter */
13	/*****************************************************/	13	/*****************************************************/
14	void ADC_Init(void)	14	void ADC_Init(void)
15	{	15	{
16	uint8_t sreg = SREG;	16	uint8_t sreg = SREG;
-		17	printf("\r\n ADC init...");
17	// disable all interrupts before reconfiguration	18	// disable all interrupts before reconfiguration
18	cli();	19	cli();
19	//ADC0 ... ADC7 is connected to PortA pin 0 ... 7	20	//ADC0 ... ADC7 is connected to PortA pin 0 ... 7
20	DDRA = 0x00;	21	DDRA = 0x00;
21	PORTA = 0x00;	22	PORTA = 0x00;
22	// Digital Input Disable Register 0	23	// Digital Input Disable Register 0
23	// Disable digital input buffer for analog adc_channel pins	24	// Disable digital input buffer for analog adc_channel pins
24	DIDR0 = 0xFF;	25	DIDR0 = 0xFF;
25	// external reference AREF, adjust data to the right	26	// external reference AREF, adjust data to the right
26	ADMUX &= ~((1 << REFS1)\|(1 << REFS0)\|(1 << ADLAR));	27	ADMUX &= ~((1 << REFS1)\|(1 << REFS0)\|(1 << ADLAR));
27	// set muxer to ADC adc_channel 0 (0 to 7 is a valid choice)	28	// set muxer to ADC adc_channel 0 (0 to 7 is a valid choice)
28	ADMUX = (ADMUX & 0xE0) \| 0x00;	29	ADMUX = (ADMUX & 0xE0) \| 0x00;
29	//Set ADC Control and Status Register A	30	//Set ADC Control and Status Register A
30	//Auto Trigger Enable, Prescaler Select Bits to Division Factor 128, i.e. ADC clock = SYSCKL/128 = 156.25 kHz	31	//Auto Trigger Enable, Prescaler Select Bits to Division Factor 128, i.e. ADC clock = SYSCKL/128 = 156.25 kHz
31	ADCSRA = (0<<ADEN)\|(0<<ADSC)\|(0<<ADATE)\|(1<<ADPS2)\|(1<<ADPS1)\|(1<<ADPS0)\|(0<<ADIE);	32	ADCSRA = (0<<ADEN)\|(0<<ADSC)\|(0<<ADATE)\|(1<<ADPS2)\|(1<<ADPS1)\|(1<<ADPS0)\|(0<<ADIE);
32	//Set ADC Control and Status Register B	33	//Set ADC Control and Status Register B
33	//Trigger Source to Free Running Mode	34	//Trigger Source to Free Running Mode
34	ADCSRB &= ~((1 << ADTS2)\|(1 << ADTS1)\|(1 << ADTS0));	35	ADCSRB &= ~((1 << ADTS2)\|(1 << ADTS1)\|(1 << ADTS0));
35	// Start AD conversion	36	// Start AD conversion
36	ADC_Enable();	37	ADC_Enable();
37	// restore global interrupt flags	38	// restore global interrupt flags
38	SREG = sreg;	39	SREG = sreg;
-		40	sei();
-		41	printf("ok");
39	}	42	}
40		43
41	/*****************************************************/	44	/*****************************************************/
42	/* Interrupt Service Routine for ADC */	45	/* Interrupt Service Routine for ADC */
43	/*****************************************************/	46	/*****************************************************/
44	// runs at 312.5 kHz or 3.2 µs	47	// runs at 312.5 kHz or 3.2 µs
45	// if after (60.8µs) all 19 states are processed the interrupt is disabled	48	// if after (60.8µs) all 19 states are processed the interrupt is disabled
46	// and the update of further ads is stopped	49	// and the update of further ads is stopped
47		50
48		51
49	#define ADC0 0	52	#define ADC0 0
50	#define ADC1 1	53	#define ADC1 1
51	#define ADC2 2	54	#define ADC2 2
52	#define ADC3 3	55	#define ADC3 3
53	#define ADC4 4	56	#define ADC4 4
54	#define ADC5 5	57	#define ADC5 5
55	#define ADC6 6	58	#define ADC6 6
56	#define ADC7 7	59	#define ADC7 7
57		60
58	ISR(ADC_vect)	61	ISR(ADC_vect)
59	{	62	{
60	static uint8_t ad_channel = ADC0, state = 0;	63	static uint8_t ad_channel = ADC0, state = 0;
61		64
62	// state machine	65	// state machine
63	switch(state++)	66	switch(state++)
64	{	67	{
65	case 0:	68	case 0:
66	Adc0 = ADC;	69	Adc0 = ADC;
67	ad_channel = ADC1;	70	ad_channel = ADC1;
68	break;	71	break;
69	case 1:	72	case 1:
70	Adc1 = ADC;	73	Adc1 = ADC;
71	ad_channel = ADC2;	74	ad_channel = ADC2;
72	break;	75	break;
73	case 2:	76	case 2:
74	Adc2 = ADC;	77	Adc2 = ADC;
75	ad_channel = ADC3;	78	ad_channel = ADC3;
76	break;	79	break;
77	case 3:	80	case 3:
78	Adc3 = ADC;	81	Adc3 = ADC;
79	ad_channel = ADC4;	82	ad_channel = ADC4;
80	break;	83	break;
81	case 4:	84	case 4:
82	Adc4 = ADC;	85	Adc4 = ADC;
83	ad_channel = ADC5;	86	ad_channel = ADC5;
84	break;	87	break;
85	case 5:	88	case 5:
86	Adc5 = ADC;	89	Adc5 = ADC;
87	ad_channel = ADC6;	90	ad_channel = ADC6;
88	break;	91	break;
89	case 6:	92	case 6:
90	Adc6 = ADC;	93	Adc6 = ADC;
91	ad_channel = ADC7;	94	ad_channel = ADC7;
92	break;	95	break;
93	case 7:	96	case 7:
94	Adc7 = ADC;	97	Adc7 = ADC;
95	ad_channel = ADC0;	98	ad_channel = ADC0;
96	state = 0;	99	state = 0;
97	ADReady = 1;	100	ADReady = 1;
98	break;	101	break;
99	default:	102	default:
100	ad_channel = ADC0;	103	ad_channel = ADC0;
101	state = 0;	104	state = 0;
102	ADReady = 1;	105	ADReady = 1;
103	break;	106	break;
104	}	107	}
105	// set adc muxer to next ad_channel	108	// set adc muxer to next ad_channel
106	ADMUX = (ADMUX & 0xE0) \| ad_channel;	109	ADMUX = (ADMUX & 0xE0) \| ad_channel;
107	// after full cycle stop further interrupts	110	// after full cycle stop further interrupts
108	if(state != 0) ADC_Enable();	111	if(state != 0) ADC_Enable();
109	}	112	}
110		113

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