| 0,0 → 1,777 |
|---|
| |
| main.elf: file format elf32-avr |
| |
| Sections: |
| Idx Name Size VMA LMA File off Algn |
| 0 .text 0000047e 00000000 00000000 00000094 2**1 |
| CONTENTS, ALLOC, LOAD, READONLY, CODE |
| 1 .data 00000002 00800060 0000047e 00000512 2**0 |
| CONTENTS, ALLOC, LOAD, DATA |
| 2 .bss 000000ea 00800062 00800062 00000514 2**0 |
| ALLOC |
| 3 .stab 00000378 00000000 00000000 00000514 2**2 |
| CONTENTS, READONLY, DEBUGGING |
| 4 .stabstr 00000071 00000000 00000000 0000088c 2**0 |
| CONTENTS, READONLY, DEBUGGING |
| 5 .debug_aranges 00000020 00000000 00000000 000008fd 2**0 |
| CONTENTS, READONLY, DEBUGGING |
| 6 .debug_pubnames 0000011d 00000000 00000000 0000091d 2**0 |
| CONTENTS, READONLY, DEBUGGING |
| 7 .debug_info 000003bf 00000000 00000000 00000a3a 2**0 |
| CONTENTS, READONLY, DEBUGGING |
| 8 .debug_abbrev 0000011c 00000000 00000000 00000df9 2**0 |
| CONTENTS, READONLY, DEBUGGING |
| 9 .debug_line 00000367 00000000 00000000 00000f15 2**0 |
| CONTENTS, READONLY, DEBUGGING |
| 10 .debug_frame 00000070 00000000 00000000 0000127c 2**2 |
| CONTENTS, READONLY, DEBUGGING |
| 11 .debug_str 000001dc 00000000 00000000 000012ec 2**0 |
| CONTENTS, READONLY, DEBUGGING |
| 12 .debug_loc 00000220 00000000 00000000 000014c8 2**0 |
| CONTENTS, READONLY, DEBUGGING |
| Disassembly of section .text: |
| |
| 00000000 <__vectors>: |
| 0: 12 c0 rjmp .+36 ; 0x26 <__ctors_end> |
| 2: 2c c0 rjmp .+88 ; 0x5c <__bad_interrupt> |
| 4: 2b c0 rjmp .+86 ; 0x5c <__bad_interrupt> |
| 6: 2a c0 rjmp .+84 ; 0x5c <__bad_interrupt> |
| 8: 29 c0 rjmp .+82 ; 0x5c <__bad_interrupt> |
| a: 28 c0 rjmp .+80 ; 0x5c <__bad_interrupt> |
| c: 27 c0 rjmp .+78 ; 0x5c <__bad_interrupt> |
| e: 26 c0 rjmp .+76 ; 0x5c <__bad_interrupt> |
| 10: 25 c0 rjmp .+74 ; 0x5c <__bad_interrupt> |
| 12: 24 c0 rjmp .+72 ; 0x5c <__bad_interrupt> |
| 14: 23 c0 rjmp .+70 ; 0x5c <__bad_interrupt> |
| 16: 5c c0 rjmp .+184 ; 0xd0 <__vector_11> |
| 18: 21 c0 rjmp .+66 ; 0x5c <__bad_interrupt> |
| 1a: 25 c0 rjmp .+74 ; 0x66 <__vector_13> |
| 1c: 1f c0 rjmp .+62 ; 0x5c <__bad_interrupt> |
| 1e: 1e c0 rjmp .+60 ; 0x5c <__bad_interrupt> |
| 20: 1d c0 rjmp .+58 ; 0x5c <__bad_interrupt> |
| 22: 1c c0 rjmp .+56 ; 0x5c <__bad_interrupt> |
| 24: 1b c0 rjmp .+54 ; 0x5c <__bad_interrupt> |
| |
| 00000026 <__ctors_end>: |
| 26: 11 24 eor r1, r1 |
| 28: 1f be out 0x3f, r1 ; 63 |
| 2a: cf e5 ldi r28, 0x5F ; 95 |
| 2c: d4 e0 ldi r29, 0x04 ; 4 |
| 2e: de bf out 0x3e, r29 ; 62 |
| 30: cd bf out 0x3d, r28 ; 61 |
| |
| 00000032 <__do_copy_data>: |
| 32: 10 e0 ldi r17, 0x00 ; 0 |
| 34: a0 e6 ldi r26, 0x60 ; 96 |
| 36: b0 e0 ldi r27, 0x00 ; 0 |
| 38: ee e7 ldi r30, 0x7E ; 126 |
| 3a: f4 e0 ldi r31, 0x04 ; 4 |
| 3c: 02 c0 rjmp .+4 ; 0x42 <.do_copy_data_start> |
| |
| 0000003e <.do_copy_data_loop>: |
| 3e: 05 90 lpm r0, Z+ |
| 40: 0d 92 st X+, r0 |
| |
| 00000042 <.do_copy_data_start>: |
| 42: a2 36 cpi r26, 0x62 ; 98 |
| 44: b1 07 cpc r27, r17 |
| 46: d9 f7 brne .-10 ; 0x3e <__SP_H__> |
| |
| 00000048 <__do_clear_bss>: |
| 48: 11 e0 ldi r17, 0x01 ; 1 |
| 4a: a2 e6 ldi r26, 0x62 ; 98 |
| 4c: b0 e0 ldi r27, 0x00 ; 0 |
| 4e: 01 c0 rjmp .+2 ; 0x52 <.do_clear_bss_start> |
| |
| 00000050 <.do_clear_bss_loop>: |
| 50: 1d 92 st X+, r1 |
| |
| 00000052 <.do_clear_bss_start>: |
| 52: ac 34 cpi r26, 0x4C ; 76 |
| 54: b1 07 cpc r27, r17 |
| 56: e1 f7 brne .-8 ; 0x50 <.do_clear_bss_loop> |
| 58: d4 d1 rcall .+936 ; 0x402 <main> |
| 5a: 10 c2 rjmp .+1056 ; 0x47c <_exit> |
| |
| 0000005c <__bad_interrupt>: |
| 5c: d1 cf rjmp .-94 ; 0x0 <__heap_end> |
| |
| 0000005e <uart_putchar>: |
| struct str_Exception Exception; |
| |
| // -------------------------------------------------------------------------- |
| int uart_putchar (char c) |
| { |
| 5e: 8c b9 out 0x0c, r24 ; 12 |
| UDR = c; |
| return (0); |
| } |
| 60: 80 e0 ldi r24, 0x00 ; 0 |
| 62: 90 e0 ldi r25, 0x00 ; 0 |
| 64: 08 95 ret |
| |
| 00000066 <__vector_13>: |
| |
| // -------------------------------------------------------------------------- |
| SIGNAL(SIG_UART_TRANS) |
| { |
| 66: 1f 92 push r1 |
| 68: 0f 92 push r0 |
| 6a: 0f b6 in r0, 0x3f ; 63 |
| 6c: 0f 92 push r0 |
| 6e: 11 24 eor r1, r1 |
| 70: 8f 93 push r24 |
| 72: 9f 93 push r25 |
| 74: ef 93 push r30 |
| 76: ff 93 push r31 |
| static unsigned int ptr = 0; |
| unsigned char tmp_tx; |
| if(!UebertragungAbgeschlossen) |
| 78: 80 91 60 00 lds r24, 0x0060 |
| 7c: 88 23 and r24, r24 |
| 7e: d9 f4 brne .+54 ; 0xb6 <__vector_13+0x50> |
| { |
| ptr++; // die [0] wurde schon gesendet |
| 80: 80 91 6c 00 lds r24, 0x006C |
| 84: 90 91 6d 00 lds r25, 0x006D |
| 88: 01 96 adiw r24, 0x01 ; 1 |
| 8a: 90 93 6d 00 sts 0x006D, r25 |
| 8e: 80 93 6c 00 sts 0x006C, r24 |
| tmp_tx = TxdBuffer[ptr]; |
| 92: fc 01 movw r30, r24 |
| 94: e9 52 subi r30, 0x29 ; 41 |
| 96: ff 4f sbci r31, 0xFF ; 255 |
| 98: e0 81 ld r30, Z |
| if((tmp_tx == '\r') || (ptr == MAX_TX_BUF)) |
| 9a: ed 30 cpi r30, 0x0D ; 13 |
| 9c: 19 f0 breq .+6 ; 0xa4 <__vector_13+0x3e> |
| 9e: 84 36 cpi r24, 0x64 ; 100 |
| a0: 91 05 cpc r25, r1 |
| a2: 39 f4 brne .+14 ; 0xb2 <__vector_13+0x4c> |
| { |
| ptr = 0; |
| a4: 10 92 6d 00 sts 0x006D, r1 |
| a8: 10 92 6c 00 sts 0x006C, r1 |
| UebertragungAbgeschlossen = 1; |
| ac: 81 e0 ldi r24, 0x01 ; 1 |
| ae: 80 93 60 00 sts 0x0060, r24 |
| } |
| UDR = tmp_tx; |
| b2: ec b9 out 0x0c, r30 ; 12 |
| b4: 04 c0 rjmp .+8 ; 0xbe <__vector_13+0x58> |
| } |
| else ptr = 0; |
| b6: 10 92 6d 00 sts 0x006D, r1 |
| ba: 10 92 6c 00 sts 0x006C, r1 |
| be: ff 91 pop r31 |
| c0: ef 91 pop r30 |
| c2: 9f 91 pop r25 |
| c4: 8f 91 pop r24 |
| c6: 0f 90 pop r0 |
| c8: 0f be out 0x3f, r0 ; 63 |
| ca: 0f 90 pop r0 |
| cc: 1f 90 pop r1 |
| ce: 18 95 reti |
| |
| 000000d0 <__vector_11>: |
| } |
| |
| // -------------------------------------------------------------------------- |
| SIGNAL(SIG_UART_RECV) |
| { |
| d0: 1f 92 push r1 |
| d2: 0f 92 push r0 |
| d4: 0f b6 in r0, 0x3f ; 63 |
| d6: 0f 92 push r0 |
| d8: 11 24 eor r1, r1 |
| da: 2f 93 push r18 |
| dc: 3f 93 push r19 |
| de: 4f 93 push r20 |
| e0: 5f 93 push r21 |
| e2: 6f 93 push r22 |
| e4: 7f 93 push r23 |
| e6: 8f 93 push r24 |
| e8: 9f 93 push r25 |
| ea: af 93 push r26 |
| ec: bf 93 push r27 |
| ee: ef 93 push r30 |
| f0: ff 93 push r31 |
| static unsigned int crc; |
| static unsigned char crc1,crc2,buf_ptr; |
| static unsigned char UartState = 0; |
| unsigned char CrcOkay = 0; |
| |
| SioTmp = UDR; |
| f2: 8c b1 in r24, 0x0c ; 12 |
| f4: 80 93 62 00 sts 0x0062, r24 |
| |
| if(buf_ptr >= MAX_RX_BUF) |
| f8: 50 91 67 00 lds r21, 0x0067 |
| fc: 54 36 cpi r21, 0x64 ; 100 |
| fe: 10 f0 brcs .+4 ; 0x104 <__vector_11+0x34> |
| UartState = 0; |
| 100: 10 92 66 00 sts 0x0066, r1 |
| if(SioTmp == '\r' && UartState == 2) |
| 104: 80 91 62 00 lds r24, 0x0062 |
| 108: 8d 30 cpi r24, 0x0D ; 13 |
| 10a: 09 f0 breq .+2 ; 0x10e <__vector_11+0x3e> |
| 10c: 56 c0 rjmp .+172 ; 0x1ba <__vector_11+0xea> |
| 10e: 80 91 66 00 lds r24, 0x0066 |
| 112: 82 30 cpi r24, 0x02 ; 2 |
| 114: 09 f0 breq .+2 ; 0x118 <__vector_11+0x48> |
| 116: 51 c0 rjmp .+162 ; 0x1ba <__vector_11+0xea> |
| { |
| UartState = 0; |
| 118: 10 92 66 00 sts 0x0066, r1 |
| crc -= RxdBuffer[buf_ptr-2]; |
| 11c: 65 2f mov r22, r21 |
| 11e: 77 27 eor r23, r23 |
| 120: fb 01 movw r30, r22 |
| 122: 32 97 sbiw r30, 0x02 ; 2 |
| 124: 23 e7 ldi r18, 0x73 ; 115 |
| 126: 30 e0 ldi r19, 0x00 ; 0 |
| 128: e2 0f add r30, r18 |
| 12a: f3 1f adc r31, r19 |
| 12c: 40 81 ld r20, Z |
| crc -= RxdBuffer[buf_ptr-1]; |
| 12e: cb 01 movw r24, r22 |
| 130: 01 97 sbiw r24, 0x01 ; 1 |
| 132: dc 01 movw r26, r24 |
| 134: a2 0f add r26, r18 |
| 136: b3 1f adc r27, r19 |
| 138: 2c 91 ld r18, X |
| crc %= 4096; |
| 13a: 80 91 6a 00 lds r24, 0x006A |
| 13e: 90 91 6b 00 lds r25, 0x006B |
| 142: 84 1b sub r24, r20 |
| 144: 91 09 sbc r25, r1 |
| 146: 82 1b sub r24, r18 |
| 148: 91 09 sbc r25, r1 |
| 14a: 9f 70 andi r25, 0x0F ; 15 |
| 14c: 90 93 6b 00 sts 0x006B, r25 |
| 150: 80 93 6a 00 sts 0x006A, r24 |
| crc1 = '=' + crc / 64; |
| 154: 9c 01 movw r18, r24 |
| 156: 00 24 eor r0, r0 |
| 158: 22 0f add r18, r18 |
| 15a: 33 1f adc r19, r19 |
| 15c: 00 1c adc r0, r0 |
| 15e: 22 0f add r18, r18 |
| 160: 33 1f adc r19, r19 |
| 162: 00 1c adc r0, r0 |
| 164: 23 2f mov r18, r19 |
| 166: 30 2d mov r19, r0 |
| 168: 23 5c subi r18, 0xC3 ; 195 |
| 16a: 20 93 69 00 sts 0x0069, r18 |
| crc2 = '=' + crc % 64; |
| 16e: 8f 73 andi r24, 0x3F ; 63 |
| 170: 38 2f mov r19, r24 |
| 172: 33 5c subi r19, 0xC3 ; 195 |
| 174: 30 93 68 00 sts 0x0068, r19 |
| CrcOkay = 0; |
| if((crc1 == RxdBuffer[buf_ptr-2]) && (crc2 == RxdBuffer[buf_ptr-1])) |
| 178: 80 81 ld r24, Z |
| 17a: 28 17 cp r18, r24 |
| 17c: 29 f4 brne .+10 ; 0x188 <__vector_11+0xb8> |
| 17e: 8c 91 ld r24, X |
| 180: 38 17 cp r19, r24 |
| 182: 11 f4 brne .+4 ; 0x188 <__vector_11+0xb8> |
| 184: 91 e0 ldi r25, 0x01 ; 1 |
| 186: 06 c0 rjmp .+12 ; 0x194 <__vector_11+0xc4> |
| { |
| CrcOkay = 1; |
| } |
| else |
| { |
| CrcOkay = 0; |
| CntCrcError++; |
| 188: 80 91 64 00 lds r24, 0x0064 |
| 18c: 8f 5f subi r24, 0xFF ; 255 |
| 18e: 80 93 64 00 sts 0x0064, r24 |
| 192: 90 e0 ldi r25, 0x00 ; 0 |
| } |
| if(!NeuerDatensatzEmpfangen && CrcOkay) // Datensatz schon verarbeitet |
| 194: 80 91 63 00 lds r24, 0x0063 |
| 198: 88 23 and r24, r24 |
| 19a: 09 f0 breq .+2 ; 0x19e <__vector_11+0xce> |
| 19c: 6c c0 rjmp .+216 ; 0x276 <__vector_11+0x1a6> |
| 19e: 99 23 and r25, r25 |
| 1a0: 09 f4 brne .+2 ; 0x1a4 <__vector_11+0xd4> |
| 1a2: 69 c0 rjmp .+210 ; 0x276 <__vector_11+0x1a6> |
| { |
| NeuerDatensatzEmpfangen = 1; |
| 1a4: 81 e0 ldi r24, 0x01 ; 1 |
| 1a6: 80 93 63 00 sts 0x0063, r24 |
| AnzahlEmpfangsBytes = buf_ptr; |
| 1aa: 50 93 65 00 sts 0x0065, r21 |
| RxdBuffer[buf_ptr] = '\r'; |
| 1ae: fb 01 movw r30, r22 |
| 1b0: ed 58 subi r30, 0x8D ; 141 |
| 1b2: ff 4f sbci r31, 0xFF ; 255 |
| 1b4: 8d e0 ldi r24, 0x0D ; 13 |
| 1b6: 80 83 st Z, r24 |
| 1b8: 5e c0 rjmp .+188 ; 0x276 <__vector_11+0x1a6> |
| } |
| } |
| else |
| switch(UartState) |
| 1ba: 80 91 66 00 lds r24, 0x0066 |
| 1be: 81 30 cpi r24, 0x01 ; 1 |
| 1c0: 01 f1 breq .+64 ; 0x202 <__vector_11+0x132> |
| 1c2: 81 30 cpi r24, 0x01 ; 1 |
| 1c4: 20 f0 brcs .+8 ; 0x1ce <__vector_11+0xfe> |
| 1c6: 82 30 cpi r24, 0x02 ; 2 |
| 1c8: 09 f0 breq .+2 ; 0x1cc <__vector_11+0xfc> |
| 1ca: 53 c0 rjmp .+166 ; 0x272 <__vector_11+0x1a2> |
| 1cc: 35 c0 rjmp .+106 ; 0x238 <__vector_11+0x168> |
| { |
| case 0: |
| if(SioTmp == '#' && !NeuerDatensatzEmpfangen) UartState = 1; // Startzeichen und Daten schon verarbeitet |
| 1ce: 80 91 62 00 lds r24, 0x0062 |
| 1d2: 83 32 cpi r24, 0x23 ; 35 |
| 1d4: 39 f4 brne .+14 ; 0x1e4 <__vector_11+0x114> |
| 1d6: 80 91 63 00 lds r24, 0x0063 |
| 1da: 88 23 and r24, r24 |
| 1dc: 19 f4 brne .+6 ; 0x1e4 <__vector_11+0x114> |
| 1de: 81 e0 ldi r24, 0x01 ; 1 |
| 1e0: 80 93 66 00 sts 0x0066, r24 |
| buf_ptr = 0; |
| RxdBuffer[buf_ptr++] = SioTmp; |
| 1e4: 80 91 62 00 lds r24, 0x0062 |
| 1e8: 80 93 73 00 sts 0x0073, r24 |
| 1ec: 81 e0 ldi r24, 0x01 ; 1 |
| 1ee: 80 93 67 00 sts 0x0067, r24 |
| crc = SioTmp; |
| 1f2: 80 91 62 00 lds r24, 0x0062 |
| 1f6: 99 27 eor r25, r25 |
| 1f8: 90 93 6b 00 sts 0x006B, r25 |
| 1fc: 80 93 6a 00 sts 0x006A, r24 |
| 200: 3a c0 rjmp .+116 ; 0x276 <__vector_11+0x1a6> |
| |
| break; |
| case 1: // Adresse auswerten |
| UartState++; |
| 202: 82 e0 ldi r24, 0x02 ; 2 |
| 204: 80 93 66 00 sts 0x0066, r24 |
| RxdBuffer[buf_ptr++] = SioTmp; |
| 208: 80 91 62 00 lds r24, 0x0062 |
| 20c: e3 e7 ldi r30, 0x73 ; 115 |
| 20e: f0 e0 ldi r31, 0x00 ; 0 |
| 210: e5 0f add r30, r21 |
| 212: f1 1d adc r31, r1 |
| 214: 80 83 st Z, r24 |
| 216: 85 2f mov r24, r21 |
| 218: 8f 5f subi r24, 0xFF ; 255 |
| 21a: 80 93 67 00 sts 0x0067, r24 |
| crc += SioTmp; |
| 21e: 20 91 62 00 lds r18, 0x0062 |
| 222: 80 91 6a 00 lds r24, 0x006A |
| 226: 90 91 6b 00 lds r25, 0x006B |
| 22a: 82 0f add r24, r18 |
| 22c: 91 1d adc r25, r1 |
| 22e: 90 93 6b 00 sts 0x006B, r25 |
| 232: 80 93 6a 00 sts 0x006A, r24 |
| 236: 1f c0 rjmp .+62 ; 0x276 <__vector_11+0x1a6> |
| |
| break; |
| case 2: // Eingangsdaten sammeln |
| RxdBuffer[buf_ptr] = SioTmp; |
| 238: 80 91 62 00 lds r24, 0x0062 |
| 23c: e3 e7 ldi r30, 0x73 ; 115 |
| 23e: f0 e0 ldi r31, 0x00 ; 0 |
| 240: e5 0f add r30, r21 |
| 242: f1 1d adc r31, r1 |
| 244: 80 83 st Z, r24 |
| if(buf_ptr < MAX_RX_BUF) buf_ptr++; |
| 246: 54 36 cpi r21, 0x64 ; 100 |
| 248: 28 f4 brcc .+10 ; 0x254 <__vector_11+0x184> |
| 24a: 85 2f mov r24, r21 |
| 24c: 8f 5f subi r24, 0xFF ; 255 |
| 24e: 80 93 67 00 sts 0x0067, r24 |
| 252: 02 c0 rjmp .+4 ; 0x258 <__vector_11+0x188> |
| else UartState = 0; |
| 254: 10 92 66 00 sts 0x0066, r1 |
| crc += SioTmp; |
| 258: 20 91 62 00 lds r18, 0x0062 |
| 25c: 80 91 6a 00 lds r24, 0x006A |
| 260: 90 91 6b 00 lds r25, 0x006B |
| 264: 82 0f add r24, r18 |
| 266: 91 1d adc r25, r1 |
| 268: 90 93 6b 00 sts 0x006B, r25 |
| 26c: 80 93 6a 00 sts 0x006A, r24 |
| 270: 02 c0 rjmp .+4 ; 0x276 <__vector_11+0x1a6> |
| |
| break; |
| default: |
| UartState = 0; |
| 272: 10 92 66 00 sts 0x0066, r1 |
| 276: ff 91 pop r31 |
| 278: ef 91 pop r30 |
| 27a: bf 91 pop r27 |
| 27c: af 91 pop r26 |
| 27e: 9f 91 pop r25 |
| 280: 8f 91 pop r24 |
| 282: 7f 91 pop r23 |
| 284: 6f 91 pop r22 |
| 286: 5f 91 pop r21 |
| 288: 4f 91 pop r20 |
| 28a: 3f 91 pop r19 |
| 28c: 2f 91 pop r18 |
| 28e: 0f 90 pop r0 |
| 290: 0f be out 0x3f, r0 ; 63 |
| 292: 0f 90 pop r0 |
| 294: 1f 90 pop r1 |
| 296: 18 95 reti |
| |
| 00000298 <AddCRC>: |
| break; |
| } |
| } |
| |
| // -------------------------------------------------------------------------- |
| void AddCRC(unsigned int wieviele) |
| { |
| 298: dc 01 movw r26, r24 |
| unsigned int tmpCRC = 0,i; |
| for(i = 0; i < wieviele;i++) |
| 29a: 89 2b or r24, r25 |
| 29c: 29 f4 brne .+10 ; 0x2a8 <AddCRC+0x10> |
| 29e: 20 e0 ldi r18, 0x00 ; 0 |
| 2a0: 30 e0 ldi r19, 0x00 ; 0 |
| 2a2: a0 e0 ldi r26, 0x00 ; 0 |
| 2a4: b0 e0 ldi r27, 0x00 ; 0 |
| 2a6: 11 c0 rjmp .+34 ; 0x2ca <AddCRC+0x32> |
| 2a8: 20 e0 ldi r18, 0x00 ; 0 |
| 2aa: 30 e0 ldi r19, 0x00 ; 0 |
| 2ac: 40 e0 ldi r20, 0x00 ; 0 |
| 2ae: 50 e0 ldi r21, 0x00 ; 0 |
| 2b0: 67 ed ldi r22, 0xD7 ; 215 |
| 2b2: 70 e0 ldi r23, 0x00 ; 0 |
| { |
| tmpCRC += TxdBuffer[i]; |
| 2b4: fa 01 movw r30, r20 |
| 2b6: e6 0f add r30, r22 |
| 2b8: f7 1f adc r31, r23 |
| 2ba: 80 81 ld r24, Z |
| 2bc: 28 0f add r18, r24 |
| 2be: 31 1d adc r19, r1 |
| 2c0: 4f 5f subi r20, 0xFF ; 255 |
| 2c2: 5f 4f sbci r21, 0xFF ; 255 |
| 2c4: a4 17 cp r26, r20 |
| 2c6: b5 07 cpc r27, r21 |
| 2c8: a9 f7 brne .-22 ; 0x2b4 <AddCRC+0x1c> |
| } |
| tmpCRC %= 4096; |
| 2ca: 3f 70 andi r19, 0x0F ; 15 |
| TxdBuffer[i++] = '=' + tmpCRC / 64; |
| 2cc: c9 01 movw r24, r18 |
| 2ce: 00 24 eor r0, r0 |
| 2d0: 88 0f add r24, r24 |
| 2d2: 99 1f adc r25, r25 |
| 2d4: 00 1c adc r0, r0 |
| 2d6: 88 0f add r24, r24 |
| 2d8: 99 1f adc r25, r25 |
| 2da: 00 1c adc r0, r0 |
| 2dc: 89 2f mov r24, r25 |
| 2de: 90 2d mov r25, r0 |
| 2e0: 83 5c subi r24, 0xC3 ; 195 |
| 2e2: 47 ed ldi r20, 0xD7 ; 215 |
| 2e4: 50 e0 ldi r21, 0x00 ; 0 |
| 2e6: fd 01 movw r30, r26 |
| 2e8: e4 0f add r30, r20 |
| 2ea: f5 1f adc r31, r21 |
| 2ec: 80 83 st Z, r24 |
| 2ee: 11 96 adiw r26, 0x01 ; 1 |
| TxdBuffer[i++] = '=' + tmpCRC % 64; |
| 2f0: 2f 73 andi r18, 0x3F ; 63 |
| 2f2: 23 5c subi r18, 0xC3 ; 195 |
| 2f4: fd 01 movw r30, r26 |
| 2f6: e4 0f add r30, r20 |
| 2f8: f5 1f adc r31, r21 |
| 2fa: 20 83 st Z, r18 |
| 2fc: 11 96 adiw r26, 0x01 ; 1 |
| TxdBuffer[i++] = '\r'; |
| 2fe: a4 0f add r26, r20 |
| 300: b5 1f adc r27, r21 |
| 302: 8d e0 ldi r24, 0x0D ; 13 |
| 304: 8c 93 st X, r24 |
| UebertragungAbgeschlossen = 0; |
| 306: 10 92 60 00 sts 0x0060, r1 |
| UDR = TxdBuffer[0]; |
| 30a: 80 91 d7 00 lds r24, 0x00D7 |
| 30e: 8c b9 out 0x0c, r24 ; 12 |
| 310: 08 95 ret |
| |
| 00000312 <SendOutData>: |
| } |
| |
| |
| // -------------------------------------------------------------------------- |
| void SendOutData(unsigned char cmd,unsigned char modul, unsigned char *snd, unsigned char len) |
| { |
| 312: ff 92 push r15 |
| 314: 0f 93 push r16 |
| 316: 1f 93 push r17 |
| 318: cf 93 push r28 |
| 31a: df 93 push r29 |
| 31c: 8a 01 movw r16, r20 |
| 31e: 72 2f mov r23, r18 |
| unsigned int pt = 0; |
| unsigned char a,b,c; |
| unsigned char ptr = 0; |
| |
| TxdBuffer[pt++] = '#'; // Startzeichen |
| 320: 93 e2 ldi r25, 0x23 ; 35 |
| 322: 90 93 d7 00 sts 0x00D7, r25 |
| TxdBuffer[pt++] = modul; // Adresse (a=0; b=1,...) |
| 326: 60 93 d8 00 sts 0x00D8, r22 |
| TxdBuffer[pt++] = cmd; // Commando |
| 32a: 80 93 d9 00 sts 0x00D9, r24 |
| |
| while(len) |
| 32e: 22 23 and r18, r18 |
| 330: 19 f4 brne .+6 ; 0x338 <SendOutData+0x26> |
| 332: a3 e0 ldi r26, 0x03 ; 3 |
| 334: b0 e0 ldi r27, 0x00 ; 0 |
| 336: 5d c0 rjmp .+186 ; 0x3f2 <SendOutData+0xe0> |
| 338: a3 e0 ldi r26, 0x03 ; 3 |
| 33a: b0 e0 ldi r27, 0x00 ; 0 |
| 33c: 60 e0 ldi r22, 0x00 ; 0 |
| 33e: c7 ed ldi r28, 0xD7 ; 215 |
| 340: d0 e0 ldi r29, 0x00 ; 0 |
| { |
| if(len) { a = snd[ptr++]; len--;} else a = 0; |
| 342: f8 01 movw r30, r16 |
| 344: e6 0f add r30, r22 |
| 346: f1 1d adc r31, r1 |
| 348: 90 81 ld r25, Z |
| 34a: 6f 5f subi r22, 0xFF ; 255 |
| 34c: 71 50 subi r23, 0x01 ; 1 |
| if(len) { b = snd[ptr++]; len--;} else b = 0; |
| 34e: 19 f4 brne .+6 ; 0x356 <SendOutData+0x44> |
| 350: ff 24 eor r15, r15 |
| 352: 40 e0 ldi r20, 0x00 ; 0 |
| 354: 0f c0 rjmp .+30 ; 0x374 <SendOutData+0x62> |
| 356: f8 01 movw r30, r16 |
| 358: e6 0f add r30, r22 |
| 35a: f1 1d adc r31, r1 |
| 35c: 40 81 ld r20, Z |
| 35e: 6f 5f subi r22, 0xFF ; 255 |
| 360: 71 50 subi r23, 0x01 ; 1 |
| if(len) { c = snd[ptr++]; len--;} else c = 0; |
| 362: 11 f4 brne .+4 ; 0x368 <SendOutData+0x56> |
| 364: ff 24 eor r15, r15 |
| 366: 06 c0 rjmp .+12 ; 0x374 <SendOutData+0x62> |
| 368: f8 01 movw r30, r16 |
| 36a: e6 0f add r30, r22 |
| 36c: f1 1d adc r31, r1 |
| 36e: f0 80 ld r15, Z |
| 370: 6f 5f subi r22, 0xFF ; 255 |
| 372: 71 50 subi r23, 0x01 ; 1 |
| TxdBuffer[pt++] = '=' + (a >> 2); |
| 374: 89 2f mov r24, r25 |
| 376: 86 95 lsr r24 |
| 378: 86 95 lsr r24 |
| 37a: 83 5c subi r24, 0xC3 ; 195 |
| 37c: fd 01 movw r30, r26 |
| 37e: ec 0f add r30, r28 |
| 380: fd 1f adc r31, r29 |
| 382: 80 83 st Z, r24 |
| 384: fd 01 movw r30, r26 |
| 386: 31 96 adiw r30, 0x01 ; 1 |
| TxdBuffer[pt++] = '=' + (((a & 0x03) << 4) | ((b & 0xf0) >> 4)); |
| 388: 55 27 eor r21, r21 |
| 38a: 89 2f mov r24, r25 |
| 38c: 99 27 eor r25, r25 |
| 38e: 83 70 andi r24, 0x03 ; 3 |
| 390: 90 70 andi r25, 0x00 ; 0 |
| 392: 82 95 swap r24 |
| 394: 92 95 swap r25 |
| 396: 90 7f andi r25, 0xF0 ; 240 |
| 398: 98 27 eor r25, r24 |
| 39a: 80 7f andi r24, 0xF0 ; 240 |
| 39c: 98 27 eor r25, r24 |
| 39e: 9a 01 movw r18, r20 |
| 3a0: 32 95 swap r19 |
| 3a2: 22 95 swap r18 |
| 3a4: 2f 70 andi r18, 0x0F ; 15 |
| 3a6: 23 27 eor r18, r19 |
| 3a8: 3f 70 andi r19, 0x0F ; 15 |
| 3aa: 23 27 eor r18, r19 |
| 3ac: 82 2b or r24, r18 |
| 3ae: 83 5c subi r24, 0xC3 ; 195 |
| 3b0: ec 0f add r30, r28 |
| 3b2: fd 1f adc r31, r29 |
| 3b4: 80 83 st Z, r24 |
| 3b6: fd 01 movw r30, r26 |
| 3b8: 32 96 adiw r30, 0x02 ; 2 |
| TxdBuffer[pt++] = '=' + (((b & 0x0f) << 2) | ((c & 0xc0) >> 6)); |
| 3ba: 4f 70 andi r20, 0x0F ; 15 |
| 3bc: 50 70 andi r21, 0x00 ; 0 |
| 3be: 44 0f add r20, r20 |
| 3c0: 55 1f adc r21, r21 |
| 3c2: 44 0f add r20, r20 |
| 3c4: 55 1f adc r21, r21 |
| 3c6: 8f 2d mov r24, r15 |
| 3c8: 82 95 swap r24 |
| 3ca: 86 95 lsr r24 |
| 3cc: 86 95 lsr r24 |
| 3ce: 83 70 andi r24, 0x03 ; 3 |
| 3d0: 84 2b or r24, r20 |
| 3d2: 83 5c subi r24, 0xC3 ; 195 |
| 3d4: ec 0f add r30, r28 |
| 3d6: fd 1f adc r31, r29 |
| 3d8: 80 83 st Z, r24 |
| 3da: fd 01 movw r30, r26 |
| 3dc: 33 96 adiw r30, 0x03 ; 3 |
| TxdBuffer[pt++] = '=' + ( c & 0x3f); |
| 3de: 8f 2d mov r24, r15 |
| 3e0: 8f 73 andi r24, 0x3F ; 63 |
| 3e2: 83 5c subi r24, 0xC3 ; 195 |
| 3e4: ec 0f add r30, r28 |
| 3e6: fd 1f adc r31, r29 |
| 3e8: 80 83 st Z, r24 |
| 3ea: 14 96 adiw r26, 0x04 ; 4 |
| 3ec: 77 23 and r23, r23 |
| 3ee: 09 f0 breq .+2 ; 0x3f2 <SendOutData+0xe0> |
| 3f0: a8 cf rjmp .-176 ; 0x342 <SendOutData+0x30> |
| } |
| AddCRC(pt); |
| 3f2: cd 01 movw r24, r26 |
| 3f4: 51 df rcall .-350 ; 0x298 <AddCRC> |
| 3f6: df 91 pop r29 |
| 3f8: cf 91 pop r28 |
| 3fa: 1f 91 pop r17 |
| 3fc: 0f 91 pop r16 |
| 3fe: ff 90 pop r15 |
| 400: 08 95 ret |
| |
| 00000402 <main>: |
| } |
| |
| |
| //----------------------------------------------------------------------------- |
| //main |
| //main execution loop |
| //----------------------------------------------------------------------------- |
| int main(void) |
| { |
| 402: 0f 93 push r16 |
| 404: 1f 93 push r17 |
| 406: cf 93 push r28 |
| 408: df 93 push r29 |
| |
| // int message structures; |
| VersionInfo.identifier = XIDENTIFIER_VERSION; |
| 40a: 81 e0 ldi r24, 0x01 ; 1 |
| 40c: 80 93 6e 00 sts 0x006E, r24 |
| VersionInfo.majorversion = MAJORVERSION; |
| 410: 10 92 6f 00 sts 0x006F, r1 |
| VersionInfo.minorversion = MINORVERSION; |
| 414: 80 93 70 00 sts 0x0070, r24 |
| AnalogData.identifier = XIDENTIFIER_ANALOG; |
| 418: 82 e0 ldi r24, 0x02 ; 2 |
| 41a: 80 93 3b 01 sts 0x013B, r24 |
| Exception.identifier = XIDENTIFIER_EXCEPTION; |
| 41e: 10 92 71 00 sts 0x0071, r1 |
| |
| // PORT D - unused right now |
| PORTD = 0x10; |
| 422: 80 e1 ldi r24, 0x10 ; 16 |
| 424: 82 bb out 0x12, r24 ; 18 |
| DDRD = 0x00; |
| 426: 11 ba out 0x11, r1 ; 17 |
| |
| //Enable TXEN im Register UCR TX-Data Enable & RX Enable |
| |
| // USART initialization |
| // Communication Parameters: 8 Data, 1 Stop, No Parity |
| // USART Receiver: On |
| // USART Transmitter: On |
| // USART RX/TX interrupt enable |
| // USART Mode: Asynchronous |
| // USART Baud rate: 57600 |
| UCSRA=0x00; |
| 428: 1b b8 out 0x0b, r1 ; 11 |
| UCSRB=0xD8; |
| 42a: 88 ed ldi r24, 0xD8 ; 216 |
| 42c: 8a b9 out 0x0a, r24 ; 10 |
| UCSRC=0x86; |
| 42e: 86 e8 ldi r24, 0x86 ; 134 |
| 430: 80 bd out 0x20, r24 ; 32 |
| #ifdef CPUSPEED_20 //20.000MHz |
| UBRRH=0x00; |
| UBRRL=0x15; |
| #endif |
| |
| #ifdef CPUSPEED_16 //16.000MHz |
| UBRRH=0x00; |
| UBRRL=0x10; |
| #endif |
| |
| #ifdef CPUSPEED_11059 //11.059MHz |
| UBRRH=0x00; |
| 432: 10 bc out 0x20, r1 ; 32 |
| UBRRL=0x0B; |
| 434: 8b e0 ldi r24, 0x0B ; 11 |
| 436: 89 b9 out 0x09, r24 ; 9 |
| #endif |
| |
| |
| // Enable interrupts |
| sei(); |
| 438: 78 94 sei |
| |
| NeuerDatensatzEmpfangen = 0; |
| 43a: 10 92 63 00 sts 0x0063, r1 |
| 43e: 0e e6 ldi r16, 0x6E ; 110 |
| 440: 10 e0 ldi r17, 0x00 ; 0 |
| 442: c1 e7 ldi r28, 0x71 ; 113 |
| 444: d0 e0 ldi r29, 0x00 ; 0 |
| |
| // main loop |
| while (1) |
| { |
| if(NeuerDatensatzEmpfangen==1) { |
| 446: 80 91 63 00 lds r24, 0x0063 |
| 44a: 81 30 cpi r24, 0x01 ; 1 |
| 44c: e1 f7 brne .-8 ; 0x446 <main+0x44> |
| switch(RxdBuffer[3]) |
| 44e: 80 91 76 00 lds r24, 0x0076 |
| 452: 81 30 cpi r24, 0x01 ; 1 |
| 454: 19 f0 breq .+6 ; 0x45c <main+0x5a> |
| 456: 82 30 cpi r24, 0x02 ; 2 |
| 458: 39 f4 brne .+14 ; 0x468 <__stack+0x9> |
| 45a: 0d c0 rjmp .+26 ; 0x476 <__stack+0x17> |
| { |
| // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| // version request |
| case XIDENTIFIER_VERSION: |
| SendOutData('X',0x00,(unsigned char *) &VersionInfo,sizeof(VersionInfo)); |
| 45c: 23 e0 ldi r18, 0x03 ; 3 |
| 45e: a8 01 movw r20, r16 |
| 460: 60 e0 ldi r22, 0x00 ; 0 |
| 462: 88 e5 ldi r24, 0x58 ; 88 |
| 464: 56 df rcall .-340 ; 0x312 <SendOutData> |
| 466: 07 c0 rjmp .+14 ; 0x476 <__stack+0x17> |
| break; |
| // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| case XIDENTIFIER_ANALOG: |
| break; |
| // - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - |
| default: |
| Exception.errorcode = ERRORCODE_NOTIMPLEMENTED; |
| 468: 10 92 72 00 sts 0x0072, r1 |
| SendOutData('X',0x00,(unsigned char *) &Exception,sizeof(VersionInfo)); |
| 46c: 23 e0 ldi r18, 0x03 ; 3 |
| 46e: ae 01 movw r20, r28 |
| 470: 60 e0 ldi r22, 0x00 ; 0 |
| 472: 88 e5 ldi r24, 0x58 ; 88 |
| 474: 4e df rcall .-356 ; 0x312 <SendOutData> |
| } |
| NeuerDatensatzEmpfangen=0; |
| 476: 10 92 63 00 sts 0x0063, r1 |
| 47a: e5 cf rjmp .-54 ; 0x446 <main+0x44> |
| |
| 0000047c <_exit>: |
| 47c: ff cf rjmp .-2 ; 0x47c <_exit> |