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Compare Revisions

• This comparison shows the changes necessary to convert path

  → / @ 59

  → / @ 60

  ↔ Reverse comparison

• Compare Path:	Rev

  With Path:	Rev

Ignore whitespace Rev 59 → Rev 60

/trunk/spi_slave.c
140,7 → 140,7
}
}
// while RxFIFO not empty
while (SSP_GetFlagStatus(SSP0, SSP_FLAG_RxFifoNotEmpty)==SET)
while (SSP_GetFlagStatus(SSP0, SSP_FLAG_RxFifoNotEmpty) == SET)
{
rxdata = SSP0->DR; // catch the received byte
// Fill TxFIFO while its not full or end of packet is reached

/trunk/timer.c
64,12 → 64,13
//----------------------------------------------------------------------------------------------------
void TIM1_IRQHandler(void)
{
TIM_ClearFlag(TIM1, TIM_FLAG_OC1); // clear irq pending bit
TIM1->OC1R += 200; // Timerfreq is 200kHz, generate an interrupt every 1ms
CountMilliseconds++;
//if (GPIO_ReadBit(GPIO6, GPIO_Pin_3)) GPIO_WriteBit(GPIO6, GPIO_Pin_3, Bit_RESET); else GPIO_WriteBit(GPIO6, GPIO_Pin_3, Bit_SET);
if(TIM_GetFlagStatus(TIM1, TIM_FLAG_OC1) == SET)
{
TIM1->OC1R += 200; // Timerfreq is 200kHz, generate an interrupt every 1ms
CountMilliseconds++;
//if (GPIO_ReadBit(GPIO6, GPIO_Pin_3)) GPIO_WriteBit(GPIO6, GPIO_Pin_3, Bit_RESET); else GPIO_WriteBit(GPIO6, GPIO_Pin_3, Bit_SET);
TIM_ClearFlag(TIM1, TIM_FLAG_OC1); // clear irq pending bit
}
// write any value to VIC0 Vector address register
VIC0->VAR = 0xFF;
}
100,7 → 101,7
VIC_Config(TIM1_ITLine, VIC_IRQ, 5);
VIC_ITCmd(TIM1_ITLine, ENABLE);
SystemTime.Year = 0;
SystemTime.Month = 0;
SystemTime.Day = 0;