| 122,8 → 122,8 |
|---|
| { |
| static unsigned int ptr = 0; |
| unsigned char tmp_tx; |
| |
| if(!UebertragungAbgeschlossen) |
| |
| if(!UebertragungAbgeschlossen) |
| { |
| ptr++; // die [0] wurde schon gesendet |
| tmp_tx = TxdBuffer[ptr]; |
| 149,9 → 149,9 |
|---|
| |
| if (JetiUpdateModeActive == 1) { UDR1 = UDR0; return; } |
| if (JetiUpdateModeActive == 2) { RxdBuffer[0] = UDR0; return; } |
| |
| |
| SioTmp = UDR0; |
| |
| |
| if(buf_ptr >= MAX_SENDE_BUFF) UartState = 0; |
| if(SioTmp == '\r' && UartState == 2) |
| { |
| 174,7 → 174,7 |
|---|
| wdt_enable(WDTO_250MS); // Reset-Commando |
| ServoActive = 0; |
| } |
| |
| |
| } |
| } |
| else |
| 466,73 → 466,63 |
|---|
| SendOutData('W', FC_ADDRESS,2, &tempchar1, sizeof(tempchar1), &tempchar2, sizeof(tempchar2)); |
| } |
| break; |
| case 'j': |
| { uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU/ (8 * 38400L) - 1); |
| |
| |
| |
| cli(); |
| |
| // disable receiver and transmitter |
| UCSR0B &= ~(1 << TXEN0); |
| UCSR0B &= ~(1 << RXEN0); |
| UCSR1B &= ~(1 << TXEN1); |
| UCSR1B &= ~(1 << RXEN1); |
| |
| // disable RX-Interrupt |
| UCSR0B &= ~(1 << RXCIE0); |
| UCSR1B &= ~(1 << RXCIE1); |
| // disable TX-Interrupt |
| UCSR0B &= ~(1 << TXCIE0); |
| UCSR1B &= ~(1 << TXCIE1); |
| |
| // flush receive buffer explicit |
| while ( UCSR1A & (1<<RXC1) ) UDR1; |
| while ( UCSR0A & (1<<RXC0) ) UDR0; |
| |
| |
| if (pRxData[0] == 0) |
| case 'j': |
| tempchar1 = LIBFC_GetCPUType(); |
| if((tempchar1 == CPU_ATMEGA644P) || (tempchar1 == CPU_ATMEGA1284P)) |
| { |
| UBRR1H = (uint8_t)(ubrr>>8); |
| UBRR1L = (uint8_t)ubrr; |
| |
| UBRR0H = UBRR1H; |
| UBRR0L = UBRR1L; |
| // 8-bit |
| UCSR1B &= ~(1 << UCSZ12); |
| UCSR1C |= (1 << UCSZ11); |
| UCSR1C |= (1 << UCSZ10); |
| |
| UCSR1C &= ~(1 << UPM11); // 0 = parity disabled |
| UCSR1C &= ~(1 << UPM10); |
| JetiUpdateModeActive = 1; |
| uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU/ (8 * 38400L) - 1); |
| |
| |
| } |
| else JetiUpdateModeActive = 2; |
| cli(); |
| |
| // 1 stop bit |
| UCSR1C &= ~(1 << USBS1); |
| UCSR0C &= ~(1 << USBS0); |
| |
| UCSR1B &= ~(1<<TXB81); |
| |
| UCSR1B |= (1 << RXEN1); // enable RX |
| UCSR0B |= (1 << RXEN0); // enable RX |
| UCSR1B |= (1 << TXEN1); // enable TX |
| UCSR0B |= (1 << TXEN0); // enable TX |
| |
| // ensable RX-Interrupt |
| UCSR0B |= (1 << RXCIE0); |
| UCSR1B |= (1 << RXCIE1); |
| |
| |
| TIMSK1 &= ~_BV(ICIE1); // disable other Interrupts |
| TIMSK2 &= ~(1<<OCIE2A); |
| TIMSK0 &= ~_BV(TOIE0); |
| |
| sei(); |
| |
| // UART0 & UART1 disable RX and TX-Interrupt |
| UCSR0B &= ~((1 << RXCIE0)|(1 << TXCIE0)); |
| UCSR1B &= ~((1 << RXCIE1)|(1 << TXCIE1)); |
| |
| // UART0 & UART1 disable receiver and transmitter |
| UCSR0B &= ~((1 << TXEN0) | (1 << RXEN0)); |
| UCSR1B &= ~((1 << TXEN1) | (1 << RXEN1)); |
| |
| // UART0 & UART1 flush receive buffer explicit |
| while ( UCSR1A & (1<<RXC1) ) UDR1; |
| while ( UCSR0A & (1<<RXC0) ) UDR0; |
| |
| |
| if (pRxData[0] == 0) |
| { |
| JetiUpdateModeActive = 1; |
| |
| // UART0 & UART1 set baudrate |
| UBRR1H = (uint8_t)(ubrr>>8); |
| UBRR1L = (uint8_t)ubrr; |
| UBRR0H = UBRR1H; |
| UBRR0L = UBRR1L; |
| // UART1 no parity |
| UCSR1C &= ~(1 << UPM11); |
| UCSR1C &= ~(1 << UPM10); |
| // UART1 8-bit |
| UCSR1B &= ~(1 << UCSZ12); |
| UCSR1C |= (1 << UCSZ11); |
| UCSR1C |= (1 << UCSZ10); |
| } |
| else JetiUpdateModeActive = 2; |
| |
| // UART0 & UART1 1 stop bit |
| UCSR1C &= ~(1 << USBS1); |
| UCSR0C &= ~(1 << USBS0); |
| // UART1 clear 9th bit |
| UCSR1B &= ~(1<<TXB81); |
| // enable receiver and transmitter for UART0 and UART1 |
| UCSR0B |= (1 << TXEN0) | (1 << RXEN0); |
| UCSR1B |= (1 << TXEN1) | (1 << RXEN1); |
| // enable RX-Interrupt for UART0 and UART1 |
| UCSR0B |= (1 << RXCIE0); |
| UCSR1B |= (1 << RXCIE1); |
| // disable other Interrupts |
| TIMSK0 = 0; |
| TIMSK1 = 0; |
| TIMSK2 = 0; |
| |
| sei(); |
| } |
| break; |
| |