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/tags/V0.22a/libstr91x/include/91x_adc.h
0,0 → 1,135
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_adc.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
 
/* Define to prevent recursive inclusion ------------------------------------ */
 
#ifndef __91x_ADC_H
#define __91x_ADC_H
 
/* Includes ------------------------------------------------------------------*/
 
#include "91x_map.h"
 
/* Exported types ------------------------------------------------------------*/
 
/* ADC Init structure define */
typedef struct
{
u16 ADC_WDG_High_Threshold;
u16 ADC_WDG_Low_Threshold;
u16 ADC_Channel_0_Mode;
u16 ADC_Channel_1_Mode;
u16 ADC_Channel_2_Mode;
u16 ADC_Channel_3_Mode;
u16 ADC_Channel_4_Mode;
u16 ADC_Channel_5_Mode;
u16 ADC_Channel_6_Mode;
u16 ADC_Channel_7_Mode;
u16 ADC_Select_Channel;
FunctionalState ADC_Scan_Mode;
u16 ADC_Conversion_Mode;
}ADC_InitTypeDef;
 
/* ADC watchdog thresholds */
typedef enum
{
ADC_HighThreshold,
ADC_LowThreshold
}ADC_ThresholdType;
 
/* Exported constants --------------------------------------------------------*/
 
/* ADC channels */
#define ADC_Channel_0 0x00 /* Channel 0 */
#define ADC_Channel_1 0x01 /* Channel 1 */
#define ADC_Channel_2 0x02 /* Channel 2 */
#define ADC_Channel_3 0x03 /* Channel 3 */
#define ADC_Channel_4 0x04 /* Channel 4 */
#define ADC_Channel_5 0x05 /* Channel 5 */
#define ADC_Channel_6 0x06 /* Channel 6 */
#define ADC_Channel_7 0x07 /* Channel 7 */
 
/* ADC modes */
#define ADC_Continuous_Mode 0x0010 /* Continuous mode conversion */
#define ADC_Single_Mode 0xFFEF /* Single mode conversion */
 
/* ADC Flags */
#define ADC_FLAG_ECV 0x002F /* End of Conversion Flag */
#define ADC_FLAG_AWD 0x002E /* Analog WatchDog Flag */
#define ADC_FLAG_ORD 0x0 /* DMA overrun Flag */
#define ADC_FLAG_OV_CH_0 0x00CF /* Overflow Flag for channel 0 */
#define ADC_FLAG_OV_CH_1 0x00EF /* Overflow Flag for channel 1 */
#define ADC_FLAG_OV_CH_2 0x010F /* Overflow Flag for channel 2 */
#define ADC_FLAG_OV_CH_3 0x012F /* Overflow Flag for channel 3 */
#define ADC_FLAG_OV_CH_4 0x014F /* Overflow Flag for channel 4 */
#define ADC_FLAG_OV_CH_5 0x016F /* Overflow Flag for channel 5 */
#define ADC_FLAG_OV_CH_6 0x018F /* Overflow Flag for channel 6 */
#define ADC_FLAG_OV_CH_7 0x01AF /* Overflow Flag for channel 7 */
 
/* ADC conversion modes */
#define ADC_NoThreshold_Conversion 0x0003 /* Conversion w/o thresholds */
#define ADC_LowThreshold_Conversion 0x0002 /* Low threshold conversion */
#define ADC_HighThreshold_Conversion 0x0001 /* High threshold conversion */
#define ADC_No_Conversion 0x0000 /* No ADC conversion */
 
/* ADC interrupts */
#define ADC_IT_ECV 0x0400 /* End of Conversion Interrupt */
#define ADC_IT_AWD 0x0200 /* Analog Watchdog Interrupt */
#define ADC_IT_ORD 0x0010 /* Overun DMA Interrupt */
 
/* ADC Start/Stop conversion */
#define ADC_Conversion_Start 0x0001 /* ADC start conversion */
#define ADC_Conversion_Stop 0xFFFE /* ADC stop conversion */
 
/* ADC Trigger source */
#define ADC_PWM_Trig 0x01 /* PWM Trigger */
#define ADC_TIM_Trig 0x02 /* Timer Trigger */
#define ADC_PIN_Trig 0x03 /* External Trigger Pin */
 
/* ADC Trigger Edge */
#define Falling_ETE 0x00 /*Falling edge*/
#define Rising_ETE 0x01 /*Rising edge*/
 
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
 
void ADC_DeInit(void);
void ADC_Init(ADC_InitTypeDef* ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
void ADC_PrescalerConfig(u8 ADC_Prescaler);
u8 ADC_GetPrescalerValue(void);
FlagStatus ADC_GetFlagStatus(u16 ADC_Flag);
void ADC_ClearFlag(u16 ADC_Flag);
u16 ADC_GetConversionValue(u16 ADC_Channel);
FlagStatus ADC_GetAnalogWatchdogResult(u16 ADC_Channel);
void ADC_ClearAnalogWatchdogResult(u16 ADC_Channel);
u16 ADC_GetWatchdogThreshold(ADC_ThresholdType ADC_Threshold);
void ADC_ITConfig(u16 ADC_IT, FunctionalState ADC_NewState);
void ADC_StandbyModeCmd(FunctionalState ADC_NewState);
void ADC_Cmd(FunctionalState ADC_NewState);
void ADC_ConversionCmd(u16 ADC_Conversion);
void ADC_ExternalTrigConfig(u16 ADC_ExtTrig_Src , u16 ADC_ExtTrig_Edge);
void ADC_ExternalTrigCmd(FunctionalState ADC_NewState);
void ADC_DMACmd(FunctionalState ADC_NewState);
void ADC_AutomaticClockGatedCmd(FunctionalState ADC_NewState);
#endif /* __91x_ADC_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
 
/tags/V0.22a/libstr91x/include/91x_ahbapb.h
0,0 → 1,57
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_ahbapb.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* AHBAPB firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _91x_AHBAPB_H
#define _91x_AHBAPB_H
 
#include "91x_map.h"
 
#define AHBAPB_Split_Enable 0x01000000
#define AHBAPB_Split_Disable 0xFEFFFFFF
#define AHBAPB_Error_Enable 0x0000100
#define AHBAPB_Error_Disable 0xFFFFEFF
 
/*FLAG*/
#define AHBAPB_FLAG_ERROR 0x01 /* error flag*/
#define AHBAPB_FLAG_OUTM 0x10 /* Out of Memory flag */
#define AHBAPB_FLAG_APBT 0x20 /* APB Time-out flag */
#define AHBAPB_FLAG_RW 0x40 /*Access type flag*/
 
/* Includes ------------------------------------------------------------------*/
 
 
/* AHBAPB Init structure definition */
typedef struct
{
u32 AHBAPB_SetTimeOut;
u32 AHBAPB_Error;
u32 AHBAPB_Split;
u8 AHBAPB_SplitCounter;
}AHBAPB_InitTypeDef;
 
/* Exported constants --------------------------------------------------------*/
void AHBAPB_DeInit(AHBAPB_TypeDef* AHBAPBx);
void AHBAPB_Init(AHBAPB_TypeDef* AHBAPBx, AHBAPB_InitTypeDef* AHBAPB_InitStruct);
void AHBAPB_StructInit(AHBAPB_InitTypeDef* AHBAPB_InitStruct);
FlagStatus AHBAPB_GetFlagStatus(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG);
void AHBAPB_ClearFlag(AHBAPB_TypeDef* AHBAPBx, u8 AHBAPB_FLAG);
u32 AHBAPB_GetPeriphAddrError(AHBAPB_TypeDef* AHBAPBx);
 
 
#endif /* _91x_AHBAPB_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_can.h
0,0 → 1,166
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_can.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* CAN bus firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_CAN_H
#define __91x_CAN_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
 
/* Exported types ------------------------------------------------------------*/
 
/* CAN Init structure define */
typedef struct
{
u8 CAN_ConfigParameters;
u32 CAN_Bitrate;
}CAN_InitTypeDef;
 
/* Exported constants --------------------------------------------------------*/
/* Standard bitrates available*/
enum
{
CAN_BITRATE_100K,
CAN_BITRATE_125K,
CAN_BITRATE_250K,
CAN_BITRATE_500K,
CAN_BITRATE_1M
};
 
/* Control register*/
#define CAN_CR_TEST 0x0080
#define CAN_CR_CCE 0x0040
#define CAN_CR_DAR 0x0020
#define CAN_CR_EIE 0x0008
#define CAN_CR_SIE 0x0004
#define CAN_CR_IE 0x0002
#define CAN_CR_INIT 0x0001
 
/* Status register */
#define CAN_SR_BOFF 0x0080
#define CAN_SR_EWARN 0x0040
#define CAN_SR_EPASS 0x0020
#define CAN_SR_RXOK 0x0010
#define CAN_SR_TXOK 0x0008
#define CAN_SR_LEC 0x0007
 
/* Test register*/
#define CAN_TESTR_RX 0x0080
#define CAN_TESTR_TX1 0x0040
#define CAN_TESTR_TX0 0x0020
#define CAN_TESTR_LBACK 0x0010
#define CAN_TESTR_SILENT 0x0008
#define CAN_TESTR_BASIC 0x0004
 
/* IFn / Command Request register*/
#define CAN_CRR_BUSY 0x8000
 
/* IFn / Command Mask register*/
#define CAN_CMR_WRRD 0x0080
#define CAN_CMR_MASK 0x0040
#define CAN_CMR_ARB 0x0020
#define CAN_CMR_CONTROL 0x0010
#define CAN_CMR_CLRINTPND 0x0008
#define CAN_CMR_TXRQSTNEWDAT 0x0004
#define CAN_CMR_DATAA 0x0002
#define CAN_CMR_DATAB 0x0001
 
/* IFn / Mask 2 register*/
#define CAN_M2R_MXTD 0x8000
#define CAN_M2R_MDIR 0x4000
 
/* IFn / Arbitration 2 register*/
#define CAN_A2R_MSGVAL 0x8000
#define CAN_A2R_XTD 0x4000
#define CAN_A2R_DIR 0x2000
 
/* IFn / Message Control register*/
#define CAN_MCR_NEWDAT 0x8000
#define CAN_MCR_MSGLST 0x4000
#define CAN_MCR_INTPND 0x2000
#define CAN_MCR_UMASK 0x1000
#define CAN_MCR_TXIE 0x0800
#define CAN_MCR_RXIE 0x0400
#define CAN_MCR_RMTEN 0x0200
#define CAN_MCR_TXRQST 0x0100
#define CAN_MCR_EOB 0x0080
 
 
/* Wake-up modes*/
enum
{
CAN_WAKEUP_ON_EXT,
CAN_WAKEUP_ON_CAN
};
 
 
/* CAN message structure*/
typedef struct
{
u32 IdType;
u32 Id;
u8 Dlc;
u8 Data[8];
} canmsg;
 
/* Message ID types*/
enum
{
CAN_STD_ID,
CAN_EXT_ID
};
 
/* Message ID limits*/
 
#define CAN_LAST_STD_ID ((1<<11) - 1)
#define CAN_LAST_EXT_ID ((1L<<29) - 1)
 
/* Exported functions ------------------------------------------------------- */
void CAN_DeInit (void);
void CAN_Init(CAN_InitTypeDef* CAN_InitStruct);
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
void CAN_SetBitrate(u32 bitrate);
void CAN_SetTiming(u32 tseg1, u32 tseg2, u32 sjw, u32 brp);
ErrorStatus CAN_SetUnusedMsgObj(u32 msgobj);
ErrorStatus CAN_SetTxMsgObj(u32 msgobj, u32 idType, FunctionalState RemoteEN);
ErrorStatus CAN_SetRxMsgObj(u32 msgobj, u32 idType, u32 idLow, u32 idHigh, bool singleOrFifoLast);
ErrorStatus CAN_SetUnusedAllMsgObj(void);
ErrorStatus CAN_ReleaseMessage(u32 msgobj);
ErrorStatus CAN_UpdateMsgObj(u32 msgobj, canmsg* pCanMsg);
ErrorStatus CAN_SendMessage(u32 msgobj, canmsg* pCanMsg);
ErrorStatus CAN_TransmitRequest( u32 msgobj );
ErrorStatus CAN_ReceiveMessage(u32 msgobj, bool release, canmsg* pCanMsg);
void CAN_WaitEndOfTx(void);
ErrorStatus CAN_BasicSendMessage(canmsg* pCanMsg);
ErrorStatus CAN_BasicReceiveMessage(canmsg* pCanMsg);
void CAN_EnterInitMode(u8 InitMask);
void CAN_LeaveInitMode(void);
void CAN_EnterTestMode(u8 TestMask);
void CAN_LeaveTestMode(void);
void CAN_ReleaseTxMessage(u32 msgobj);
void CAN_ReleaseRxMessage(u32 msgobj);
FlagStatus CAN_GetMsgReceiveStatus(u32 msgobj);
FlagStatus CAN_GetMsgTransmitRequestStatus(u32 msgobj);
FlagStatus CAN_GetMsgInterruptStatus(u32 msgobj);
FlagStatus CAN_GetMsgValidStatus(u32 msgobj);
FlagStatus CAN_GetFlagStatus ( u32 CAN_Flag );
u32 CAN_GetTransmitErrorCounter ( void );
u32 CAN_GetReceiveErrorCounter ( void );
 
#endif /* __91x_CAN_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_conf.h
0,0 → 1,126
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_conf.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : Library configuration
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
 
#ifndef __91x_CONF_H
#define __91x_CONF_H
 
/* To work in buffered mode just Uncomment the following line */
//#define Buffered
 
/*Uncomment the line below to compile the library in DEBUG mode */
//#define DEBUG 1
 
/*Uncomment the following line to boot from Bank0*/
//#define Boot_Bank_0
 
/*Uncomment the following line to boot from Bank1*/
#define Boot_Bank_1
 
/*Uncomment the following line if the Flash size is 256KB or 512KB*/
#define Flash_512KB_256KB
 
/*Uncomment the following line if the Flash size is 1MB or 2MB */
//#define Flash_2MB_1MB
 
 
/************************* AHBAPB *************************/
//#define _AHBAPB
//#define _AHBAPB0
//#define _AHBAPB1
/************************* VIC *************************/
#define _VIC
#define _VIC0
#define _VIC1
/************************* DMA *************************/
//#define _DMA
//#define _DMA_Channel0
//#define _DMA_Channel1
//#define _DMA_Channel2
//#define _DMA_Channel3
//#define _DMA_Channel4
//#define _DMA_Channel5
//#define _DMA_Channel6
//#define _DMA_Channel7
 
/************************* EMI *************************/
//#define _EMI
//#define _EMI_Bank0
//#define _EMI_Bank1
//#define _EMI_Bank2
//#define _EMI_Bank3
/************************* FMI *************************/
#define _FMI
/************************* WIU *************************/
#define _WIU
/************************* TIM *************************/
#define _TIM
#define _TIM0
#define _TIM1
#define _TIM2
#define _TIM3
/************************* GPIO ************************/
#define _GPIO
#define _GPIO0
#define _GPIO1
#define _GPIO2
#define _GPIO3
#define _GPIO4
#define _GPIO5
#define _GPIO6
#define _GPIO7
#define _GPIO8
#define _GPIO9
/************************* RTC *************************/
//#define _RTC
/************************* SCU *************************/
#define _SCU
/************************* MC **************************/
//#define _MC
/************************* UART ************************/
#define _UART
#define _UART0
#define _UART1
#define _UART2
/************************* SSP *************************/
#define _SSP
#define _SSP0
#define _SSP1
/************************* CAN *************************/
//#define _CAN
/************************* ADC *************************/
#define _ADC
/************************* WDG *************************/
//#define _WDG
/************************* I2C *************************/
#define _I2C
//#define _I2C0
#define _I2C1
/************************ ENET *************************/
//#define _ENET
/************************ USB *************************/
#define _USB
 
/*---------------------------- _Main_Crystal frequency value (KHz)------------*/
 
#ifndef _Main_Crystal
#define _Main_Crystal 25000
#endif
/*------------------------------------------------------------------------------*/
 
 
#endif /* __91x_CONF_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_dma.h
0,0 → 1,290
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_dma.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : provide a short description of the source file indicating
* its purpose.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_DMA_H
#define __91x_DMA_H
 
/* Includes ------------------------------------------------------------------*/
#include"91x_map.h"
 
 
/* Exported types ------------------------------------------------------------*/
 
typedef struct
{
u32 DMA_Channel_SrcAdd; /* The current source address (byte-aligned) of the data to be transferred.*/
 
u32 DMA_Channel_DesAdd; /* The current destination address (byte-aligned) of the data to be transferred.*/
 
u32 DMA_Channel_LLstItm; /* The word- aligned address for the next Linked List Item. */
 
u32 DMA_Channel_DesWidth; /* Destination transfer width. */
 
u32 DMA_Channel_SrcWidth; /* Source transfer width. */
 
u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/
 
u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */
 
u32 DMA_Channel_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/
 
u32 DMA_Channel_FlowCntrl; /* Flow control and transfer type. */
 
u32 DMA_Channel_Src; /* Source peripheral: selects the DMA source request peripheral. */
 
u32 DMA_Channel_Des; /* Destination peripheral:selects the DMA destination request peripheral. */
 
} DMA_InitTypeDef;
 
typedef struct
{
u32 LLI_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/
u32 LLI_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */
u32 LLI_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/
u32 LLI_SrcWidth; /* Source transfer width. */
u32 LLI_DesWidth; /* Destination transfer width. */
u32 LLI_SrcIncrement; /*Source increment*/
u32 LLI_DesIncrement; /*Destination increment*/
u32 LLI_PROT0; /*Cacheable Access*/
u32 LLI_PROT1; /*Bufferable Access*/
u32 LLI_PROT2; /*Privileged mode activation*/
u32 LLI_TCInterrupt; /*Terminal count interrupt activation*/
} LLI_CCR_InitTypeDef;
 
typedef struct
{
u32 LLI_SrcAdd; /* Source address of the data to be transferred.*/
 
u32 LLI_DesAdd; /* Destination address of the data to be transferred.*/
 
u32 LLI_Pointer; /* Pointer to the next LLI. */
 
u32 LLI_CCR; /* the control word. */
 
} LLI_InitTypeDef;
 
 
 
 
/* Exported constants --------------------------------------------------------*/
 
/* Interrupts masks */
 
#define DMA_ITMask_IE 0x4000 /* Interrupt error mask. */
#define DMA_ITMask_ITC 0x8000 /* Terminal count interrupt mask.*/
#define DMA_ITMask_ALL 0xC000 /* All DMA_Channelx interrupts enable/disable mask*/
 
/* Sources Request (used as masks) */
 
#define DMA_USB_RX_Mask 0x0001
#define DMA_USB_TX_Mask 0x0002
#define DMA_TIM0_Mask 0x0004
#define DMA_TIM1_Mask 0x0008
#define DMA_UART0_RX_Mask 0x0010
#define DMA_UART0_TX_Mask 0x0020
#define DMA_UART1_RX_Mask 0x0040
#define DMA_UART1_TX_Mask 0x0080
#define DMA_External_Req0_Mask 0x0100
#define DMA_External_Req1_Mask 0x0200
#define DMA_I2C0_Mask 0x0400
#define DMA_I2C1_Mask 0x0800
#define DMA_SSP0_RX_Mask 0x1000
#define DMA_SSP0_TX_Mask 0x2000
#define DMA_SSP1_RX_Mask 0x4000
#define DMA_SSP1_TX_Mask 0x8000
 
 
/* Previleged Mode and user mode */
 
#define DMA_PrevilegedMode 0x10000000
#define DMA_UserMode 0xEFFFFFFF
 
 
/* Error and Terminal Count interrupts Status, after and before"raw" masking */
#define DMA_IS 0x01
#define DMA_TCS 0x02
#define DMA_ES 0x03
#define DMA_TCRS 0x04
#define DMA_ERS 0x05
 
 
/* interrupt clear: Terminal Count flag Clear and Error flag clear*/
 
#define DMA_TCC 0x01
#define DMA_EC 0x02
 
/* channel index "0...7"*/
 
#define Channel0 0
#define Channel1 1
#define Channel2 2
#define Channel3 3
#define Channel4 4
#define Channel5 5
#define Channel6 6
#define Channel7 7
 
 
 
/* Destination request selection: selects the DMA Destination request peripheral */
 
#define DMA_DES_USB_RX 0x00
#define DMA_DES_USB_TX 0x40
#define DMA_DES_TIM0 0x80
#define DMA_DES_TIM1 0xC0
#define DMA_DES_UART0_RX 0x100
#define DMA_DES_UART0_TX 0x140
#define DMA_DES_UART1_RX 0x180
#define DMA_DES_UART1_TX 0x1C0
#define DMA_DES_External_Req0 0x200
#define DMA_DES_External_Req1 0x240
#define DMA_DES_I2C0 0x280
#define DMA_DES_I2C1 0x2C0
#define DMA_DES_SSP0_RX 0x300
#define DMA_DES_SSP0_TX 0x340
#define DMA_DES_SSP1_RX 0x380
#define DMA_DES_SSP1_TX 0x3C0
 
 
 
 
/* Source request selection: selects the DMA Source request peripheral */
 
#define DMA_SRC_USB_RX 0x00
#define DMA_SRC_USB_TX 0x02
#define DMA_SRC_TIM0 0x04
#define DMA_SRC_TIM1 0x06
#define DMA_SRC_UART0_RX 0x08
#define DMA_SRC_UART0_TX 0x0A
#define DMA_SRC_UART1_RX 0x0C
#define DMA_SRC_UART1_TX 0x0E
#define DMA_SRC_External_Req0 0x10
#define DMA_SRC_External_Req1 0x12
#define DMA_SRC_I2C0 0x14
#define DMA_SRC_I2C1 0x16
#define DMA_SRC_SSP0_RX 0x18
#define DMA_SRC_SSP0_TX 0x1A
#define DMA_SRC_SSP1_RX 0x1C
#define DMA_SRC_SSP1_TX 0x1E
 
 
 
 
 
#define DMA_FlowCntrlt0_DMA 0x00000000 /* transfer type :Memory-to-memory, flow controller:DMA */
#define DMA_FlowCntrl1_DMA 0x00000800 /* transfer type :Memory-to-peripheral, flow controller:DMA */
#define DMA_FlowCntrl2_DMA 0x00001000 /* transfer type :Peripheral-to-memory, flow controller:DMA */
#define DMA_FlowCntrl3_DMA 0x00001800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */
#define DMA_FlowCntrl_DestPerip 0x00002000 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */
#define DMA_FlowCntrl_Perip1 0x00002800 /* transfer type :Memory-to-peripheral, flow controller:peripheral */
#define DMA_FlowCntrl_Perip2 0x00003000 /* transfer type : Peripheral-to-memory, flow controller:peripheral */
#define DMA_FlowCntrl_SrcPerip 0x00003800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */
 
 
 
 
#define DMA_SrcBst_1Data 0x00000000 /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */
#define DMA_SrcBst_4Data 0x00001000 /* Source Burst transfer request IS 4 Data */
#define DMA_SrcBst_8Data 0x00002000 /* Source Burst transfer request IS 8 Data */
#define DMA_SrcBst_16Data 0x00003000 /* Source Burst transfer request IS 16 Data */
#define DMA_SrcBst_32Data 0x00004000 /* Source Burst transfer request IS 32 Data */
#define DMA_SrcBst_64Data 0x00005000 /* Source Burst transfer request IS 64Data */
#define DMA_SrcBst_128Data 0x00006000 /* Source Burst transfer request IS 128 Data */
#define DMA_SrcBst_256Data 0x00007000 /* Source Burst transfer request IS 256 Data */
 
 
 
 
#define DMA_DesBst_1Data 0x00000000 /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */
#define DMA_DesBst_4Data 0x00008000 /*Destination Burst transfer request IS 1 Data */
#define DMA_DesBst_8Data 0x00010000 /*Destination Burst transfer request IS 4 Data */
#define DMA_DesBst_16Data 0x00018000 /*Destination Burst transfer request IS 8 Data */
#define DMA_DesBst_32Data 0x00020000 /*Destination Burst transfer request IS 16 Data */
#define DMA_DesBst_64Data 0x00028000 /*Destination Burst transfer request IS 32 Data */
#define DMA_DesBst_128Data 0x00030000 /*Destination Burst transfer request IS 128 Data */
#define DMA_DesBst_256Data 0x00038000 /*Destination Burst transfer request IS 256 Data */
 
 
 
 
 
#define DMA_SrcWidth_Byte 0x00000000 /* source Width is one Byte */
#define DMA_SrcWidth_HalfWord 0x00040000 /* source Width is one HalfWord */
#define DMA_SrcWidth_Word 0x00080000 /* source Width is one Word */
 
 
 
 
#define DMA_DesWidth_Byte 0x00000000 /* Destination Width is one Byte */
#define DMA_DesWidth_HalfWord 0x00200000 /* Destination Width is one HalfWord */
#define DMA_DesWidth_Word 0x00400000 /* Destination Width is one Word */
 
/*Defined value used for linked list's control word stucture*/
 
#define DMA_SrcIncrement 0x04000000 /*Source incremented*/
#define DMA_SrcNonIncrement 0x00000000 /*Source not incremented*/
#define DMA_DesIncrement 0x08000000 /*Destination incremented*/
#define DMA_DesNonIncrement 0x00000000 /*Destination not incremented*/
#define DMA_CacheableAccess 0x10000000 /*Cacheable access */
#define DMA_NonCacheableAccess 0x00000000 /*Non Cacheable access */
#define DMA_BufferableAccess 0x20000000 /*Bufferable access */
#define DMA_NonBufferableAccess 0x00000000 /*Non Bufferable access */
#define DMA_PrivilegedAccess 0x40000000 /*Privileged Access*/
#define DMA_UsermodeAccess 0x00000000 /*User mode Access*/
#define DMA_TCInterrupt 0x80000000 /* Terminal count interrupt enabled*/
#define DMA_NonTCInterrupt 0x00000000 /* Terminal count interrupt disabled*/
 
 
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
 
void DMA_DeInit(void);
void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
void DMA_Cmd(FunctionalState NewState);
void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
FlagStatus DMA_GetChannelStatus(u8 ChannelIndx );
ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq);
void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr);
void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState);
FlagStatus DMA_GetSReq(u16 DMA_SrcReq);
FlagStatus DMA_GetLSReq(u16 DMA_SrcReq);
FlagStatus DMA_GetBReq(u16 DMA_SrcReq);
FlagStatus DMA_GetLBReq(u16 DMA_SrcReq);
FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx);
void DMA_SetSReq(u16 DMA_SrcReq);
void DMA_SetLSReq(u16 DMA_SrcReq);
void DMA_SetBReq(u16 DMA_SrcReq);
void DMA_SetLBReq(u16 DMA_SrcReq);
void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState);
void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode);
void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState);
u32 DMA_LLI_CCR_Init(LLI_CCR_InitTypeDef * LLI_CCR_InitStruct);
 
#endif /* __91x_DMA_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_emi.h
0,0 → 1,123
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_emi.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* EMI firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_EMI_H
#define __91x_EMI_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
 
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u32 EMI_Bank_IDCY;
 
u32 EMI_Bank_WSTRD;
 
u32 EMI_Bank_WSTWR;
 
u32 EMI_Bank_WSTROEN;
 
u32 EMI_Bank_WSTWEN;
u32 EMI_Bank_BRDCR;
u32 EMI_Bank_MemWidth ;
 
u32 EMI_Bank_WriteProtection;
 
u32 EMI_Burst_and_PageModeRead_TransferLength;
u32 EMI_Burst_and_PageModeRead_Selection;
u32 EMI_BurstModeWrite_TransferLength;
u32 EMI_BurstModeWrite_Selection;
u32 EMI_AccessRead_Support;
u32 EMI_AccessWrite_Support;
u32 EMI_ByteLane_Selection;
} EMI_InitTypeDef;
 
/* Exported constants --------------------------------------------------------*/
 
 
 
 
/*Transfer length valid for both burst and page mode*/
#define EMI_Read_4Data 0x00000000 /*4 transfers burst*/
#define EMI_Read_8Data 0x00000400 /*8 transfers burst*/
 
/*Transfer length valid only for burst mode*/
#define EMI_Read_16Data 0x00000800 /*16 transfers burst*/
#define EMI_Read_Continuous 0x00000C00 /* Continuous (synchron-*/
/*ous only)*/
 
/*Select or deselect the page mode read*/
#define EMI_NormalMode 0x00000000 /*Normal Mode*/
#define EMI_Burst_and_PageModeRead 0x00000100 /*Page and burst Mode Read*/
 
 
/* Write transfer length for Burst mode Write */
#define EMI_Write_4Data 0x00000000 /*4 transfers burst*/
#define EMI_Write_8Data 0x00040000 /*8 transfers burst*/
#define EMI_Write_Continuous 0x000C0000 /* Continuous (synchron-*/
/*ous only)*/
 
/*Select or deselect the Burst(or page) mode Write*/
#define EMI_NonBurstModeWrite 0x00000000 /*Non Burst Mode Write*/
#define EMI_BurstModeWrite 0x00010000 /*Burst Mode Write*/
 
/*Byte Lane feature */
#define EMI_Byte_Select_disabled 0x00000000 /*Byte select disabled*/
#define EMI_Byte_Select_enabled 0x00000001 /*Byte select enabled*/
 
/*Read access feature*/
#define EMI_Read_Asyn 0x00000000 /*Asynch access for read default)*/
#define EMI_Read_Syn 0x00000200 /*Synch access for read*/
 
/*Write access feature*/
#define EMI_Write_Asyn 0x00000000 /*Asynch access for Write(default)*/
#define EMI_Write_Syn 0x00020000 /*Synch access for Write*/
 
/*Memory width*/
#define EMI_Width_Byte 0x00000000 /*8 bits width*/
#define EMI_Width_HalfWord 0x00000010 /*16 bits width*/
 
/*Write protection feature */
#define EMI_Bank_NonWriteProtect 0x00000000 /*No write protection*/
#define EMI_Bank_WriteProtect 0x00000008 /*bank is write protected*/
 
 
/* Exported macro ------------------------------------------------------------*/
 
 
/* Exported functions ------------------------------------------------------- */
 
void EMI_DeInit(void);
void EMI_Init( EMI_Bank_TypeDef* EMI_Bankx, EMI_InitTypeDef* EMI_InitStruct);
void EMI_StructInit(EMI_InitTypeDef* EMI_InitStruct);
void EMI_BCLKCmd(FunctionalState NewState);
 
#endif /* __EMI_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_fmi.h
0,0 → 1,228
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_fmi.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* FMI firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
 
/* Define to prevent recursive inclusion ------------------------------------ */
 
#ifndef __91x_FMI_H
#define __91x_FMI_H
 
 
 
/* Includes ------------------------------------------------------------------*/
 
#include "91x_map.h"
 
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
 
/* FMI banks */
 
#ifdef Boot_Bank_1 /* Boot from Bank 1 */
 
 
#define FMI_BANK_0 ((*(vu32*)0x54000010) << 2) /* FMI Bank 0 */
#define FMI_BANK_1 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 1 */
 
#endif
 
#ifdef Boot_Bank_0 /* Boot from Bank 0 */
 
#define FMI_BANK_0 ((*(vu32*)0x5400000C) << 2) /* FMI Bank 0 */
#define FMI_BANK_1 ((*(vu32*)0x54000010) << 2) /* FMI Bank 1 */
 
#endif
 
 
#define FMI_B0S0 0x00000000 + FMI_BANK_0 /* Bank 0 sector 0*/
#define FMI_B0S1 0x00010000 + FMI_BANK_0 /* Bank 0 sector 1*/
#define FMI_B0S2 0x00020000 + FMI_BANK_0 /* Bank 0 sector 2*/
#define FMI_B0S3 0x00030000 + FMI_BANK_0 /* Bank 0 sector 3*/
#define FMI_B0S4 0x00040000 + FMI_BANK_0 /* Bank 0 sector 4*/
#define FMI_B0S5 0x00050000 + FMI_BANK_0 /* Bank 0 sector 5*/
#define FMI_B0S6 0x00060000 + FMI_BANK_0 /* Bank 0 sector 6*/
#define FMI_B0S7 0x00070000 + FMI_BANK_0 /* Bank 0 sector 7*/
#define FMI_B0S8 0x00080000 + FMI_BANK_0 /* Bank 0 sector 8*/
#define FMI_B0S9 0x00090000 + FMI_BANK_0 /* Bank 0 sector 9*/
#define FMI_B0S10 0x000A0000 + FMI_BANK_0 /* Bank 0 sector 10*/
#define FMI_B0S11 0x000B0000 + FMI_BANK_0 /* Bank 0 sector 11*/
#define FMI_B0S12 0x000C0000 + FMI_BANK_0 /* Bank 0 sector 12*/
#define FMI_B0S13 0x000D0000 + FMI_BANK_0 /* Bank 0 sector 13*/
#define FMI_B0S14 0x000E0000 + FMI_BANK_0 /* Bank 0 sector 14*/
#define FMI_B0S15 0x000F0000 + FMI_BANK_0 /* Bank 0 sector 15*/
#define FMI_B0S16 0x00100000 + FMI_BANK_0 /* Bank 0 sector 16*/
#define FMI_B0S17 0x00110000 + FMI_BANK_0 /* Bank 0 sector 17*/
#define FMI_B0S18 0x00120000 + FMI_BANK_0 /* Bank 0 sector 18*/
#define FMI_B0S19 0x00130000 + FMI_BANK_0 /* Bank 0 sector 19*/
#define FMI_B0S20 0x00140000 + FMI_BANK_0 /* Bank 0 sector 20*/
#define FMI_B0S21 0x00150000 + FMI_BANK_0 /* Bank 0 sector 21*/
#define FMI_B0S22 0x00160000 + FMI_BANK_0 /* Bank 0 sector 22*/
#define FMI_B0S23 0x00170000 + FMI_BANK_0 /* Bank 0 sector 23*/
#define FMI_B0S24 0x00180000 + FMI_BANK_0 /* Bank 0 sector 24*/
#define FMI_B0S25 0x00190000 + FMI_BANK_0 /* Bank 0 sector 25*/
#define FMI_B0S26 0x001A0000 + FMI_BANK_0 /* Bank 0 sector 26*/
#define FMI_B0S27 0x001B0000 + FMI_BANK_0 /* Bank 0 sector 27*/
#define FMI_B0S28 0x001C0000 + FMI_BANK_0 /* Bank 0 sector 28*/
#define FMI_B0S29 0x001D0000 + FMI_BANK_0 /* Bank 0 sector 29*/
#define FMI_B0S30 0x001E0000 + FMI_BANK_0 /* Bank 0 sector 30*/
#define FMI_B0S31 0x001F0000 + FMI_BANK_0 /* Bank 0 sector 31*/
 
 
#ifdef Flash_2MB_1MB
 
#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */
#define FMI_B1S1 0x00004000 + FMI_BANK_1 /* Bank 1 sector 1 */
#define FMI_B1S2 0x00008000 + FMI_BANK_1 /* Bank 1 sector 2 */
#define FMI_B1S3 0x0000C000 + FMI_BANK_1 /* Bank 1 sector 3 */
#define FMI_B1S4 0x00010000 + FMI_BANK_1 /* Bank 1 sector 4 */
#define FMI_B1S5 0x00014000 + FMI_BANK_1 /* Bank 1 sector 5 */
#define FMI_B1S6 0x00018000 + FMI_BANK_1 /* Bank 1 sector 6 */
#define FMI_B1S7 0x0001C000 + FMI_BANK_1 /* Bank 1 sector 7 */
 
#endif
 
#ifdef Flash_512KB_256KB
 
#define FMI_B1S0 0x00000000 + FMI_BANK_1 /* Bank 1 sector 0 */
#define FMI_B1S1 0x00002000 + FMI_BANK_1 /* Bank 1 sector 1 */
#define FMI_B1S2 0x00004000 + FMI_BANK_1 /* Bank 1 sector 2 */
#define FMI_B1S3 0x00006000 + FMI_BANK_1 /* Bank 1 sector 3 */
 
#endif
 
 
 
/* FMI Flags */
 
#define FMI_FLAG_SPS 0x02 /* Sector Protection Status Flag */
#define FMI_FLAG_PSS 0x04 /* Program Suspend Status Flag */
#define FMI_FLAG_PS 0x10 /* Program Status Flag */
#define FMI_FLAG_ES 0x20 /* Erase Status Flag */
#define FMI_FLAG_ESS 0x40 /* Erase Suspend Status Flag */
#define FMI_FLAG_PECS 0x80 /* FPEC Status Flag */
 
/* FMI read wait states */
 
#define FMI_READ_WAIT_STATE_1 0x0000 /* One read wait state */
#define FMI_READ_WAIT_STATE_2 0x2000 /* Two read wait states */
#define FMI_READ_WAIT_STATE_3 0x4000 /* Three read wait states */
 
/* FMI write wait states */
 
#define FMI_WRITE_WAIT_STATE_0 0xFFFFFEFF /* Zero wait state */
#define FMI_WRITE_WAIT_STATE_1 0x00000100 /* One wait state */
 
/* FMI power down configuration */
 
#define FMI_PWD_ENABLE 0x1000 /* FMI Power Down Enable */
#define FMI_PWD_DISABLE 0x0000 /* FMI Power Down Disable */
 
/* FMI low voltage detector */
 
#define FMI_LVD_ENABLE 0x0000 /* FMI Low Voltage Detector Enable */
#define FMI_LVD_DISABLE 0x0800 /* FMI Low Voltage Detector Disable */
 
/* FMI frequency range */
 
#define FMI_FREQ_LOW 0x0000 /* FMI Low bus working frequency */
#define FMI_FREQ_HIGH 0x0040 /* FMI High bus working gfrequency */
/* Above 66 MHz*/
/* FMI OTP word addresses */
 
#define FMI_OTP_WORD_0 0x00 /* OTP word 0 */
#define FMI_OTP_WORD_1 0x04 /* OTP word 1 */
#define FMI_OTP_WORD_2 0x08 /* OTP word 2 */
#define FMI_OTP_WORD_3 0x0C /* OTP word 3 */
#define FMI_OTP_WORD_4 0x10 /* OTP word 4 */
#define FMI_OTP_WORD_5 0x14 /* OTP word 5 */
#define FMI_OTP_WORD_6 0x18 /* OTP word 6 */
#define FMI_OTP_WORD_7 0x1C /* OTP word 7 */
/* FMI OTP halfword addresses */
 
#define FMI_OTP_LOW_HALFWORD_0 0x00 /* OTP Low halfword 0 */
#define FMI_OTP_HIGH_HALFWORD_0 0x02 /* OTP High halfword 0 */
#define FMI_OTP_LOW_HALFWORD_1 0x04 /* OTP Low halfword 1 */
#define FMI_OTP_HIGH_HALFWORD_1 0x06 /* OTP High halfword 1 */
#define FMI_OTP_LOW_HALFWORD_2 0x08 /* OTP Low halfword 2 */
#define FMI_OTP_HIGH_HALFWORD_2 0x0A /* OTP High halfword 2 */
#define FMI_OTP_LOW_HALFWORD_3 0x0C /* OTP Low halfword 3 */
#define FMI_OTP_HIGH_HALFWORD_3 0x0E /* OTP High halfword 3 */
#define FMI_OTP_LOW_HALFWORD_4 0x10 /* OTP Low halfword 4 */
#define FMI_OTP_HIGH_HALFWORD_4 0x12 /* OTP High halfword 4 */
#define FMI_OTP_LOW_HALFWORD_5 0x14 /* OTP Low halfword 5 */
#define FMI_OTP_HIGH_HALFWORD_5 0x16 /* OTP High halfword 5 */
#define FMI_OTP_LOW_HALFWORD_6 0x18 /* OTP Low halfword 6 */
#define FMI_OTP_HIGH_HALFWORD_6 0x1A /* OTP High halfword 6 */
#define FMI_OTP_LOW_HALFWORD_7 0x1C /* OTP Low halfword 7 */
#define FMI_OTP_HIGH_HALFWORD_7 0x1E /* OTP High halfword 7 */
 
/*FMI LSB RSIG Address*/
 
#define FMI_ReadRSIGData_0 0x00 /*Manufacturer Code*/
#define FMI_ReadRSIGData_1 0x01 /*Device Code*/
#define FMI_ReadRSIGData_2 0x02 /*Die Revision Code*/
#define FMI_ReadRSIGData_3 0x03 /*Protection Level 2 Register for 512KB Flash */
/*or Protection Level 1 Register (sectors of bank0)*/
/* for 2MB flash*/
 
#define FMI_ReadRSIGData_4 0x04 /*Protection Level 1 Register for 512KB Flash*/
/* or Protection Level 1 Register (sectors of bank1)*/
/* for 2MB flash*/
 
#define FMI_ReadRSIGData_5 0x05 /*Protection Status Register(sectors of bank0)*/
/*for 2MB flash or Flash Configuration Register*/
/*for 512KB flash*/
#define FMI_ReadRSIGData_6 0x06 /*Protection Status Register (sectors of bank1)*/
/*available only for 2MB flash*/
#define FMI_ReadRSIGData_7 0x07 /*Flash Configuration Register*/
/*available only for 2MB flash*/
 
/* Timeout error */
 
#define FMI_TIME_OUT_ERROR 0x00 /* Timeout error */
#define FMI_NO_TIME_OUT_ERROR 0x01 /* No Timeout error */
 
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
 
void FMI_BankRemapConfig(u8 FMI_BootBankSize, u8 FMI_NonBootBankSize, \
u32 FMI_BootBankAddress, u32 FMI_NonBootBankAddress);
void FMI_Config(u16 FMI_ReadWaitState, u32 FMI_WriteWaitState, u16 FMI_PWD,\
u16 FMI_LVDEN, u16 FMI_FreqRange);
void FMI_EraseSector(vu32 FMI_Sector);
void FMI_EraseBank(vu32 FMI_Bank);
void FMI_WriteHalfWord(u32 FMI_Address, u16 FMI_Data);
void FMI_WriteOTPHalfWord(u8 FMI_OTPHWAddress, u16 FMI_OTPData);
u32 FMI_ReadWord(u32 FMI_Address);
u32 FMI_ReadOTPData(u8 FMI_OTPAddress);
FlagStatus FMI_GetFlagStatus(u8 FMI_Flag, vu32 FMI_Bank);
u16 FMI_GetReadWaitStateValue(void);
u16 FMI_GetWriteWaitStateValue(void);
void FMI_SuspendEnable(vu32 FMI_Bank);
void FMI_ResumeEnable(vu32 FMI_Bank);
void FMI_ClearFlag(vu32 FMI_Bank);
void FMI_WriteProtectionCmd(vu32 FMI_Sector, FunctionalState FMI_NewState);
u8 FMI_WaitForLastOperation(vu32 FMI_Bank);
u32 FMI_ReadRSIGData(u8 FMI_LSB_RSIGAddress);
 
#endif /* __91x_FMI_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
 
/tags/V0.22a/libstr91x/include/91x_gpio.h
0,0 → 1,92
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_gpio.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion ------------------------------------ */
 
#ifndef _91x_GPIO_H
#define _91x_GPIO_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
 
/* GPIO Init structure definition */
typedef struct
{
u8 GPIO_Pin;
u8 GPIO_Direction;
u8 GPIO_Type;
u8 GPIO_IPInputConnected;
u16 GPIO_Alternate;
}GPIO_InitTypeDef;
 
/* Bit_SET and Bit_RESET enumeration */
typedef enum
{ Bit_RESET = 0,
Bit_SET
}BitAction;
 
 
/* Exported constants --------------------------------------------------------*/
#define GPIO_Pin_None 0x00
#define GPIO_Pin_0 0x01
#define GPIO_Pin_1 0x02
#define GPIO_Pin_2 0x04
#define GPIO_Pin_3 0x08
#define GPIO_Pin_4 0x10
#define GPIO_Pin_5 0x20
#define GPIO_Pin_6 0x40
#define GPIO_Pin_7 0x80
#define GPIO_Pin_All 0xFF
 
#define GPIO_PinInput 0x00
#define GPIO_PinOutput 0x01
 
#define GPIO_Type_PushPull 0x00
#define GPIO_Type_OpenCollector 0x01
 
#define GPIO_IPInputConnected_Disable 0x00
#define GPIO_IPInputConnected_Enable 0x01
 
#define GPIO_InputAlt1 0x00
#define GPIO_OutputAlt1 0x01
#define GPIO_OutputAlt2 0x02
#define GPIO_OutputAlt3 0x03
 
#define GPIO_ANAChannel0 0x01
#define GPIO_ANAChannel1 0x02
#define GPIO_ANAChannel2 0x04
#define GPIO_ANAChannel3 0x08
#define GPIO_ANAChannel4 0x10
#define GPIO_ANAChannel5 0x20
#define GPIO_ANAChannel6 0x40
#define GPIO_ANAChannel7 0x80
#define GPIO_ANAChannelALL 0xFF
 
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
u8 GPIO_ReadBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin);
u8 GPIO_Read(GPIO_TypeDef* GPIOx);
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, u8 GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef* GPIOx, u8 PortVal);
void GPIO_EMIConfig(FunctionalState NewState);
void GPIO_ANAPinConfig(u8 GPIO_ANAChannel, FunctionalState NewState);
 
 
 
#endif /* _91x_GPIO_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_i2c.h
0,0 → 1,110
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_i2c.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* I2C firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_I2C_H
#define __91x_I2C_H
 
/* Includes ----------------------------------------------------------------- */
#include "91x_map.h"
 
/* Exported types ----------------------------------------------------------- */
/* I2C Init structure definition */
typedef struct
{
u32 I2C_CLKSpeed;
u16 I2C_OwnAddress;
u8 I2C_GeneralCall;
u8 I2C_Ack;
}I2C_InitTypeDef;
 
/* Exported constants --------------------------------------------------------*/
#define I2C_GeneralCall_Enable 0x10
#define I2C_GeneralCall_Disable 0xEF
/* Acknowledgement */
#define I2C_Ack_Enable 0x04
#define I2C_Ack_Disable 0xFB
 
/* I2C Flags */
#define I2C_FLAG_SB 0x0001
#define I2C_FLAG_M_SL 0x0002
#define I2C_FLAG_ADSL 0x0004
#define I2C_FLAG_BTF 0x0008
#define I2C_FLAG_BUSY 0x0010
#define I2C_FLAG_TRA 0x0020
#define I2C_FLAG_ADD10 0x0040
#define I2C_FLAG_EVF 0x0080
#define I2C_FLAG_GCAL 0x0100
#define I2C_FLAG_BERR 0x0200
#define I2C_FLAG_ARLO 0x0400
#define I2C_FLAG_STOPF 0x0800
#define I2C_FLAG_AF 0x1000
#define I2C_FLAG_ENDAD 0x2000
#define I2C_FLAG_ACK 0x4000
 
/* I2C Events */
#define I2C_EVENT_SLAVE_ADDRESS_MATCHED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_ADSL)
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF )
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA )
#define I2C_EVENT_MASTER_MODE_SELECT ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_SB )
#define I2C_EVENT_MASTER_MODE_SELECTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_ENDAD )
#define I2C_EVENT_MASTER_BYTE_RECEIVED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF )
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL | I2C_FLAG_BTF | I2C_FLAG_TRA )
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_M_SL |I2C_FLAG_ADD10 )
#define I2C_EVENT_SLAVE_STOP_DETECTED ( I2C_FLAG_EVF | I2C_FLAG_STOPF )
#define I2C_EV31 ( I2C_FLAG_EVF | I2C_FLAG_BUSY | I2C_FLAG_BTF | I2C_FLAG_TRA | I2C_FLAG_AF)
#define I2C_EVENT_SLAVE_ACK_FAILURE ( I2C_FLAG_EVF | I2C_FLAG_BUSY |I2C_FLAG_AF)
#define I2C_EVENT_ALL ( I2C_FLAG_EVF | I2C_FLAG_BUSY |I2C_FLAG_AF |I2C_FLAG_BTF)
#define I2C_BUS_ERROR_DETECTED I2C_FLAG_BERR
#define I2C_ARBITRATION_LOST I2C_FLAG_ARLO
#define I2C_SLAVE_GENERAL_CALL (I2C_FLAG_BUSY | I2C_FLAG_GCAL)
 
/* Master/Receiver Mode */
#define I2C_MODE_TRANSMITTER 0x00
#define I2C_MODE_RECEIVER 0x01
 
/* I2C Registers offset */
#define I2C_CR 0x00
#define I2C_SR1 0x04
#define I2C_SR2 0x08
#define I2C_CCR 0x0C
#define I2C_OAR1 0x10
#define I2C_OAR2 0x14
#define I2C_DR 0x18
#define I2C_ECCR 0x1C
 
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void I2C_DeInit(I2C_TypeDef* I2Cx);
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateStart(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, u8 Address, u8 Direction);
u8 I2C_ReadRegister(I2C_TypeDef* I2Cx, u8 I2C_Register);
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, u16 I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef* I2Cx, u16 I2C_FLAG, ...);
void I2C_SendData(I2C_TypeDef* I2Cx, u8 bData);
u8 I2C_ReceiveData(I2C_TypeDef* I2Cx);
u16 I2C_GetLastEvent(I2C_TypeDef* I2Cx);
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,u16 I2C_Event);
 
#endif /* __91x_I2C_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_it.h
0,0 → 1,82
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_it.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains the headers of the interrupt
* handlers'routines
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_IT_H
#define __91x_IT_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_lib.h"
 
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#define IENABLE asm("MRS lr, spsr"); /* Copy SPSR_irq to LR */ \
asm("STMFD sp!, {lr} "); /* Save SPSR_irq */ \
asm("MSR cpsr_c, #0x1F "); /* Switch to SYS mode with IRQ enabled*/ \
asm("STMFD sp!, {lr} "); /* Save SYS mode LR */
 
#define IDISABLE asm("LDMFD sp!, {lr}"); /* Restore SYS mode LR */ \
asm("MSR cpsr_c, #0x92"); /* Switch to IRQ mode with IRQ disabled*/ \
asm("LDMFD sp!, {r0}"); /* Restore SPSR_irq to R0 */ \
asm("MSR spsr_cxsf, r0"); /* Copy R0 to SPSR_irq */
 
/* Exported functions ------------------------------------------------------- */
 
 
void Undefined_Handler(void);
void SWI_Handler(void);
void Prefetch_Handler(void);
void Abort_Handler(void);
void FIQ_Handler(void);
void WDG_IRQHandler(void);
void SW_IRQHandler(void);
void ARMRX_IRQHandler(void);
void ARMTX_IRQHandler(void);
void TIM0_IRQHandler(void);
void TIM1_IRQHandler(void);
void TIM2_IRQHandler(void);
void TIM3_IRQHandler(void);
void USBHP_IRQHandler(void);
void USBLP_IRQHandler(void);
void SCU_IRQHandler(void);
void ENET_IRQHandler(void);
void DMA_IRQHandler(void);
void CAN_IRQHandler(void);
void MC_IRQHandler(void);
void ADC_IRQHandler(void);
void UART0_IRQHandler(void);
void UART1_IRQHandler(void);
void UART2_IRQHandler(void);
void I2C0_IRQHandler(void);
void I2C1_IRQHandler(void);
void SSP0_IRQHandler(void);
void SSP1_IRQHandler(void);
void LVD_IRQHandler(void);
void RTC_IRQHandler(void);
void WIU_IRQHandler(void);
void EXTIT0_IRQHandler(void);
void EXTIT1_IRQHandler(void);
void EXTIT2_IRQHandler(void);
void EXTIT3_IRQHandler(void);
void EXTIT4_IRQHandler(void);
void USBWU_IRQHandler(void);
void PFQBC_IRQHandler(void);
void DefaultVector_Handler(void);
 
#endif /* __91x_IT_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_lib.h
0,0 → 1,111
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_lib.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : Used to include the peripherals header file in the
* user application.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
#ifndef __91x_LIB_H
#define __91x_LIB_H
 
#include "91x_map.h"
#include "91x_conf.h"
 
#ifdef _AHBAPB
#include "91x_ahbapb.h"
#endif /* _AHBAPB */
 
#ifdef _EMI
#include "91x_emi.h"
#endif /* _EMI */
 
#ifdef _DMA
#include "91x_dma.h"
#endif /* _DMA */
 
#ifdef _FMI
#include "91x_fmi.h"
#endif /* _FMI */
 
#ifdef _VIC
#include "91x_vic.h"
#endif /* _VIC */
 
#ifdef _WIU
#include "91x_wiu.h"
#endif /* _WIU */
 
#ifdef _TIM
#include "91x_tim.h"
#endif /* _TIM */
 
#ifdef _GPIO
#include "91x_gpio.h"
#endif /* _GPIO */
 
#ifdef _RTC
#include "91x_rtc.h"
#endif /* _RTC */
 
#ifdef _SCU
#include "91x_scu.h"
#endif /* _SCU */
 
#ifdef _UART
#include "91x_uart.h"
#endif /* _UART */
 
#ifdef _SSP
#include "91x_ssp.h"
#endif /* _SSP */
 
#ifdef _CAN
#include "91x_can.h"
#endif /* _CAN */
 
#ifdef _ADC
#include "91x_adc.h"
#endif /* _ADC */
 
#ifdef _WDG
#include "91x_wdg.h"
#endif /* _WDG */
 
#ifdef _I2C
#include "91x_i2c.h"
#endif /* _I2C */
 
#ifdef _WIU
#include "91x_wiu.h"
#endif
 
#ifdef _MC
#include "91x_mc.h"
#endif
 
#ifdef _ENET
#include "91x_enet.h"
#endif
 
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
 
void debug( void );
 
 
#endif /* __91x_LIB_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_map.h
0,0 → 1,1036
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_map.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : Peripherals registers definition and memory mapping.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_MAP_H
#define __91x_MAP_H
 
#ifndef EXT
#define EXT extern
#endif /* EXT */
 
/* Includes ------------------------------------------------------------------*/
#include "91x_conf.h"
#include "91x_type.h"
 
/******************************************************************************/
/* IP registers structures */
/******************************************************************************/
 
/*------------------------------------ FMI -----------------------------------*/
 
typedef struct
{
vu32 BBSR; /* Boot Bank Size Register */
vu32 NBBSR; /* Non-Boot Bank Size Register */
vu32 EMPTY1;
vu32 BBADR; /* Boot Bank Base Address Register */
vu32 NBBADR; /* Non-Boot Bank Base Address Register */
vu32 EMPTY2;
vu32 CR; /* Control Register */
vu32 SR; /* Status Register */
vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */
} FMI_TypeDef;
 
/*---------------------- Analog to Digital Convertor ------------------------*/
 
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 CCR; /* Channel Configuration Register */
vu16 EMPTY2;
vu16 HTR; /* Higher Threshold Register */
vu16 EMPTY3;
vu16 LTR; /* Lower Threshold Register */
vu16 EMPTY4;
vu16 CRR; /* Compare Result Register */
vu16 EMPTY5;
vu16 DR0; /* Data Register for Channel 0 */
vu16 EMPTY6;
vu16 DR1; /* Data Register for Channel 1 */
vu16 EMPTY7;
vu16 DR2; /* Data Register for Channel 2 */
vu16 EMPTY8;
vu16 DR3; /* Data Register for Channel 3 */
vu16 EMPTY9;
vu16 DR4; /* Data Register for Channel 4 */
vu16 EMPTY10;
vu16 DR5; /* Data Register for Channel 5 */
vu16 EMPTY11;
vu16 DR6; /* Data Register for Channel 6 */
vu16 EMPTY12;
vu16 DR7; /* Data Register for Channel 7 */
vu16 EMPTY13;
vu16 PRS; /* Prescaler Value Register */
vu16 EMPTY14;
vu16 DDR; /* ADC DMA Data Register */
vu16 EMPTY15;
vu16 CR2; /* ADC Control Register2 */
vu16 EMPTY16;
} ADC_TypeDef;
 
/*--------------------- AHB APB BRIDGE registers strcture --------------------*/
 
typedef struct
{
vu32 BSR; /* Bridge Status Register */
vu32 BCR; /* Bridge Configuration Register */
vu32 PAER; /* Peripheral Address Error register */
} AHBAPB_TypeDef;
 
/*--------------- Controller Area Network Interface Register -----------------*/
 
typedef struct
{
vu16 CRR; /* IFn Command request Register */
vu16 EMPTY1;
vu16 CMR; /* IFn Command Mask Register */
vu16 EMPTY2;
vu16 M1R; /* IFn Message Mask 1 Register */
vu16 EMPTY3;
vu16 M2R; /* IFn Message Mask 2 Register */
vu16 EMPTY4;
vu16 A1R; /* IFn Message Arbitration 1 Register */
vu16 EMPTY5;
vu16 A2R; /* IFn Message Arbitration 2 Register */
vu16 EMPTY6;
vu16 MCR; /* IFn Message Control Register */
vu16 EMPTY7;
vu16 DA1R; /* IFn DATA A 1 Register */
vu16 EMPTY8;
vu16 DA2R; /* IFn DATA A 2 Register */
vu16 EMPTY9;
vu16 DB1R; /* IFn DATA B 1 Register */
vu16 EMPTY10;
vu16 DB2R; /* IFn DATA B 2 Register */
vu16 EMPTY11[27];
} CAN_MsgObj_TypeDef;
 
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 SR; /* Status Register */
vu16 EMPTY2;
vu16 ERR; /* Error counter Register */
vu16 EMPTY3;
vu16 BTR; /* Bit Timing Register */
vu16 EMPTY4;
vu16 IDR; /* Interrupt Identifier Register */
vu16 EMPTY5;
vu16 TESTR; /* Test Register */
vu16 EMPTY6;
vu16 BRPR; /* BRP Extension Register */
vu16 EMPTY7[3];
CAN_MsgObj_TypeDef sMsgObj[2];
vu16 EMPTY8[16];
vu16 TXR1R; /* Transmission request 1 Register */
vu16 EMPTY9;
vu16 TXR2R; /* Transmission Request 2 Register */
vu16 EMPTY10[13];
vu16 ND1R; /* New Data 1 Register */
vu16 EMPTY11;
vu16 ND2R; /* New Data 2 Register */
vu16 EMPTY12[13];
vu16 IP1R; /* Interrupt Pending 1 Register */
vu16 EMPTY13;
vu16 IP2R; /* Interrupt Pending 2 Register */
vu16 EMPTY14[13];
vu16 MV1R; /* Message Valid 1 Register */
vu16 EMPTY15;
vu16 MV2R; /* Message VAlid 2 Register */
vu16 EMPTY16;
} CAN_TypeDef;
 
/*----------------------- System Control Unit---------------------------------*/
 
typedef struct
{
vu32 CLKCNTR; /* Clock Control Register */
vu32 PLLCONF; /* PLL Configuration Register */
vu32 SYSSTATUS; /* System Status Register */
vu32 PWRMNG; /* Power Management Register */
vu32 ITCMSK; /* Interrupt Mask Register */
vu32 PCGR0; /* Peripheral Clock Gating Register 0 */
vu32 PCGR1; /* Peripheral Clock Gating Register 1 */
vu32 PRR0; /* Peripheral Reset Register 0 */
vu32 PRR1; /* Peripheral Reset Register 1 */
vu32 MGR0; /* Idle Mode Mask Gating Register 0 */
vu32 MGR1; /* Idle Mode Mask Gating Register 1 */
vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */
vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */
vu32 SCR0; /* System Configuration Register 0 */
vu32 SCR1; /* System Configuration Register 1 */
vu32 SCR2; /* System Configuration Register 2 */
u32 EMPTY1;
vu32 GPIOOUT[8]; /* GPIO Output Registers */
vu32 GPIOIN[8]; /* GPIO Input Registers */
vu32 GPIOTYPE[10]; /* GPIO Type Registers */
vu32 GPIOEMI; /* GPIO EMI Selector Register */
vu32 WKUPSEL; /* Wake-Up Selection Register */
u32 EMPTY2[2];
vu32 GPIOANA; /* GPIO Analag mode Register */
} SCU_TypeDef;
 
/*------------------------- DMA Channelx Registers ---------------------------*/
 
typedef struct
{
vu32 SRC; /* Channelx Source Address Register */
vu32 DES; /* Channelx Destination Address Register */
vu32 LLI; /* Channelx Lincked List Item Register */
vu32 CC; /* Channelx Contol Register */
vu32 CCNF; /* Channelx Configuration Register */
} DMA_Channel_TypeDef;
 
/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */
 
/*----------------------------- DMA Controller -------------------------------*/
 
typedef struct
{
vu32 ISR; /* Interrupt Status Register */
vu32 TCISR; /* Terminal Count Interrupt Status Register */
vu32 TCICR; /* Terminal CountInterrupt Clear Register */
vu32 EISR; /* Error Interrupt Status Register */
vu32 EICR; /* Error Interrupt Clear Register */
vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */
vu32 ERISR; /* Raw Error Interrupt Status Register */
vu32 ENCSR; /* Enabled Channel Status Register */
vu32 SBRR; /* Software Burst Request Register */
vu32 SSRR; /* Software Single Request Register */
vu32 SLBRR; /* Software Last Burst Request Register */
vu32 SLSRR; /* Software Last Single Request Register */
vu32 CNFR; /* Configuration Register */
vu32 SYNR; /* Syncronization Register */
} DMA_TypeDef;
 
/*--------------------------------- TIM Timer --------------------------------*/
 
typedef struct
{
vu16 IC1R; /* Input Capture 1 Register */
vu16 EMPTY1;
vu16 IC2R; /* Input Capture 2 Register */
vu16 EMPTY2;
vu16 OC1R; /* Output Compare 1 Register */
vu16 EMPTY3;
vu16 OC2R; /* Output Compare 2 Register */
vu16 EMPTY4;
vu16 CNTR; /* Counter Register */
vu16 EMPTY5;
vu16 CR1; /* Control Register 1 */
vu16 EMPTY6;
vu16 CR2; /* Control Register 2 */
vu16 EMPTY7;
vu16 SR; /* Status Register */
vu16 EMPTY8;
} TIM_TypeDef;
 
/*---------------------------- EMI Bankx Registers ---------------------------*/
 
typedef struct
{
vu32 ICR; /* Bankx Idle Cycle Control Register */
vu32 RCR; /* Bankx Read Wait State Control Register */
vu32 WCR; /* Bankx Write Wait State Control Register */
vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */
vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */
vu32 BCR; /* Bankx Control Register */
vu32 EMPTY1;
vu32 BRDCR; /*Bank x burst read wait delay register (EMI_BRDCRx) */
} EMI_Bank_TypeDef;
 
/*---------------------------- Ethernet Controller ---------------------------*/
 
/* MAC Registers */
typedef struct
{
vu32 MCR; /* ENET Control Register */
vu32 MAH; /* ENET Address High Register */
vu32 MAL; /* ENET Address Low Register */
vu32 MCHA; /* Multicast Address High Register */
vu32 MCLA; /* Multicast Address Low Register */
vu32 MIIA; /* MII Address Register */
vu32 MIID; /* MII Data Register */
vu32 MCF; /* ENET Control Frame Register */
vu32 VL1; /* VLAN1 Register */
vu32 VL2; /* VLAN2 register */
vu32 MTS; /* ENET Transmission Status Register */
vu32 MRS; /* ENET Reception Status Register */
} ENET_MAC_TypeDef;
 
/* DMA Registers */
typedef struct
{
vu32 SCR; /* DMA Status and Control Register */
vu32 IER; /* DMA Interrupt Sources Enable Register */
vu32 ISR; /* DMA Interrupt Status Register */
vu32 CCR; /* Clock Control Relation : HCLK, PCLK and
ENET_CLK phase relations */
vu32 RXSTR; /* Rx DMA start Register */
vu32 RXCR; /* Rx DMA Control Register */
vu32 RXSAR; /* Rx DMA Base Address Register */
vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */
vu32 RXCAR; /* Rx DMA Current Address Register */
vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */
vu32 RXTOR; /* Rx DMA FIFO Time Out Register */
vu32 RXSR; /* Rx DMA FIFO Status Register */
vu32 TXSTR; /* Tx DMA start Register */
vu32 TXCR; /* Tx DMA Control Register */
vu32 TXSAR; /* Tx DMA Base Address Register */
vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */
vu32 TXCAR; /* Tx DMA Current Address Register */
vu32 TXTCR; /* Tx DMA Current Transfer Count Register */
vu32 TXTOR; /* Tx DMA FIFO Time Out Register */
vu32 TXSR; /* Tx DMA FIFO Status Register */
} ENET_DMA_TypeDef;
 
/*------------------------------------- GPIO ---------------------------------*/
 
typedef struct
{
vu8 DR[1021]; /* Data Register */
vu32 DDR; /* Data Direction Register */
} GPIO_TypeDef;
 
/*-------------------------------- I2C interface -----------------------------*/
 
typedef struct
{
vu8 CR; /* Control Register */
vu8 EMPTY1[3];
vu8 SR1; /* Status Register 1 */
vu8 EMPTY2[3];
vu8 SR2; /* Status Register 2 */
vu8 EMPTY3[3];
vu8 CCR; /* Clock Control Register */
vu8 EMPTY4[3];
vu8 OAR1; /* Own Address Register 1 */
vu8 EMPTY5[3];
vu8 OAR2; /* Own Address Register 2 */
vu8 EMPTY6[3];
vu8 DR; /* Data Register */
vu8 EMPTY7[3];
vu8 ECCR; /* Extended Clock Control Register */
vu8 EMPTY8[3];
} I2C_TypeDef;
 
/*------------------------------------- VIC ----------------------------------*/
 
typedef struct
{
vu32 ISR; /* IRQ Status Register */
vu32 FSR; /* FIQ Status Register */
vu32 RINTSR; /* Raw Interrupt Status Register */
vu32 INTSR; /* Interrupt Select Register */
vu32 INTER; /* Interrupt Enable Register */
vu32 INTECR; /* Interrupt Enable Clear Register */
vu32 SWINTR; /* Software Interrupt Register */
vu32 SWINTCR; /* Software Interrupt clear Register */
vu32 PER; /* Protection Enable Register */
vu32 EMPTY1[3];
vu32 VAR; /* Vector Address Register */
vu32 DVAR; /* Default Vector Address Register */
vu32 EMPTY2[50];
vu32 VAiR[16]; /* Vector Address 0-15 Register */
vu32 EMPTY3[48];
vu32 VCiR[16]; /* Vector Control 0-15 Register */
} VIC_TypeDef;
 
/*-------------------------------- Motor Control -----------------------------*/
 
typedef struct
{
vu16 TCPT; /* Tacho Capture Register */
vu16 EMPTY1;
vu16 TCMP; /* Tacho Compare Register */
vu16 EMPTY2;
vu16 IPR; /* Input Pending Register */
vu16 EMPTY3;
vu16 TPRS; /* Tacho Prescaler Register */
vu16 EMPTY4;
vu16 CPRS; /* PWM Counter Prescaler Register */
vu16 EMPTY5;
vu16 REP; /* Repetition Counter Register */
vu16 EMPTY6;
vu16 CMPW; /* Compare Phase W Preload Register */
vu16 EMPTY7;
vu16 CMPV; /* Compare Phase V Preload Register */
vu16 EMPTY8;
vu16 CMPU; /* Compare Phase U Preload Register */
vu16 EMPTY9;
vu16 CMP0; /* Compare 0 Preload Register */
vu16 EMPTY10;
vu16 PCR0; /* Peripheral Control Register 0 */
vu16 EMPTY11;
vu16 PCR1; /* Peripheral Control Register 1 */
vu16 EMPTY12;
vu16 PCR2; /* Peripheral Control Register 2 */
vu16 EMPTY13;
vu16 PSR; /* Polarity Selection Register */
vu16 EMPTY14;
vu16 OPR; /* Output Peripheral Register */
vu16 EMPTY15;
vu16 IMR; /* Interrupt Mask Register */
vu16 EMPTY16;
vu16 DTG; /* Dead Time Generator Register */
vu16 EMPTY17;
vu16 ESC; /* Emergency Stop Clear Register */
vu16 EMPTY18;
vu16 ECR; /* Enhanced Control Register */
vu16 EMPTY19;
vu16 LOK; /* Lock Register */
vu16 EMPTY20;
}MC_TypeDef;
 
/*------------------------------------- RTC ----------------------------------*/
 
typedef struct
{
vu32 TR; /* Time Register */
vu32 DTR; /* Date Register */
vu32 ATR; /* Alarm time Register */
vu32 CR; /* Control Register */
vu32 SR; /* Status Register */
vu32 MILR; /* Millisec Register */
}RTC_TypeDef;
 
/*------------------------------------- SSP ----------------------------------*/
 
typedef struct
{
vu16 CR0; /* Control Register 1 */
vu16 EMPTY1;
vu16 CR1; /* Control Register 2 */
vu16 EMPTY2;
vu16 DR; /* Data Register */
vu16 EMPTY3;
vu16 SR; /* Status Register */
vu16 EMPTY4;
vu16 PR; /* Clock Prescale Register */
vu16 EMPTY5;
vu16 IMSCR; /* Interrupt Mask Set or Clear Register */
vu16 EMPTY6;
vu16 RISR; /* Raw Interrupt Status Register */
vu16 EMPTY7;
vu16 MISR; /* Masked Interrupt Status Register */
vu16 EMPTY8;
vu16 ICR; /* Interrupt Clear Register */
vu16 EMPTY9;
vu16 DMACR; /* DMA Control Register */
vu16 EMPTY10;
}SSP_TypeDef;
 
/*------------------------------------ UART ----------------------------------*/
 
typedef struct
{
vu16 DR; /* Data Register */
vu16 EMPTY1;
vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */
vu16 EMPTY2[9];
vu16 FR; /* Flag Register */
vu16 EMPTY3[3];
vu16 ILPR; /* IrDA Low-Power counter Register */
vu16 EMPTY4;
vu16 IBRD; /* Integer Baud Rate Divisor Register */
vu16 EMPTY5;
vu16 FBRD; /* Fractional Baud Rate Divisor Register */
vu16 EMPTY6;
vu16 LCR; /* Line Control Register, High byte */
vu16 EMPTY7;
vu16 CR; /* Control Register */
vu16 EMPTY8;
vu16 IFLS; /* Interrupt FIFO Level Select Register */
vu16 EMPTY9;
vu16 IMSC; /* Interrupt Mask Set/Clear Register */
vu16 EMPTY10;
vu16 RIS; /* Raw Interrupt Status Register */
vu16 EMPTY11;
vu16 MIS; /* Masked Interrupt Status Register */
vu16 EMPTY12;
vu16 ICR; /* Interrupt Clear Register */
vu16 EMPTY13;
vu16 DMACR; /* DMA Control Register */
vu16 EMPTY14;
}UART_TypeDef;
 
/*------------------------------- Wake-up System -----------------------------*/
 
typedef struct
{
vu32 CTRL; /* Control Register */
vu32 MR; /* Mask Register */
vu32 TR; /* Trigger Register */
vu32 PR; /* Pending Register */
vu32 INTR; /* Software Interrupt Register */
} WIU_TypeDef;
 
/*------------------------------- WatchDog Timer -----------------------------*/
 
typedef struct
{
vu16 CR; /* Control Register */
vu16 EMPTY1;
vu16 PR; /* Presclar Register */
vu16 EMPTY2;
vu16 VR; /* Pre-load Value Register */
vu16 EMPTY3;
vu16 CNT; /* Counter Register */
vu16 EMPTY4;
vu16 SR; /* Status Register */
vu16 EMPTY5;
vu16 MR; /* Mask Register */
vu16 EMPTY6;
vu16 KR; /* Key Register */
vu16 EMPTY7;
} WDG_TypeDef;
 
/*******************************************************************************
* Memory Mapping of STR91x *
*******************************************************************************/
 
#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */
#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */
 
#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */
#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */
 
#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */
#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */
 
#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */
#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */
 
#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */
#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */
 
#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */
#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */
 
#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */
#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */
 
#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */
#define AHB_FMI_B (0x44000000) /* FMI buffered Space */
 
/*******************************************************************************
* Addresses related to the VICs' peripherals *
*******************************************************************************/
 
#define VIC0_BASE (AHB_VIC0_U)
#define VIC1_BASE (AHB_VIC1_U)
 
/*******************************************************************************
* Addresses related to the EMI banks *
*******************************************************************************/
 
#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */
#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */
#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */
#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */
#define AHB_EMICCR_OFST (0x00000204) /* Offset of EMI_CCR Register */
 
/*******************************************************************************
* Addresses related to the DMA peripheral *
*******************************************************************************/
 
#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */
#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */
#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */
#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */
#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */
#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */
#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */
#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */
 
/*******************************************************************************
* Addresses related to the APB0 sub-system *
*******************************************************************************/
 
#define APB_WIU_OFST (0x00001000) /* Offset of WIU */
#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */
#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */
#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */
#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */
#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */
#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */
#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */
#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */
#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */
#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */
#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */
#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */
#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */
#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */
 
/*******************************************************************************
* Addresses related to the APB1 sub-system *
*******************************************************************************/
 
#define APB_RTC_OFST (0x00001000) /* Offset of RTC */
#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */
#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */
#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */
#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */
#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */
#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */
#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */
#define APB_CAN_OFST (0x00009000) /* Offset of CAN */
#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */
#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */
#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */
#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */
 
/*----------------------------------------------------------------------------*/
/*----------------------------- Unbuffered Mode ------------------------------*/
/*----------------------------------------------------------------------------*/
 
#ifndef Buffered
 
/*******************************************************************************
* AHBAPB peripheral Unbuffered Base Address *
*******************************************************************************/
 
#define AHBAPB0_BASE (AHB_APB_BRDG0_U)
#define AHBAPB1_BASE (AHB_APB_BRDG1_U)
 
/*******************************************************************************
* ENET peripheral Unbuffered Base Address *
*******************************************************************************/
 
#define ENET_MAC_BASE (AHB_ENET_MAC_U)
#define ENET_DMA_BASE (AHB_ENET_DMA_U)
 
/*******************************************************************************
* DMA peripheral Unbuffered Base Address *
*******************************************************************************/
 
#define DMA_BASE (AHB_DMA_U)
 
/*******************************************************************************
* EMI peripheral Unbuffered Base Address *
*******************************************************************************/
 
#define EMI_BASE (AHB_EMI_U)
 
/*******************************************************************************
* FMI peripheral Unbuffered Base Address *
*******************************************************************************/
 
#define FMI_BASE (AHB_FMI_U)
 
 
#else /* Buffered */
 
/*----------------------------------------------------------------------------*/
/*------------------------------ Buffered Mode -------------------------------*/
/*----------------------------------------------------------------------------*/
 
/*******************************************************************************
* AHBAPB peripheral Buffered Base Address *
*******************************************************************************/
 
#define AHBAPB0_BASE (AHB_APB_BRDG0_B)
#define AHBAPB1_BASE (AHB_APB_BRDG1_B)
 
/*******************************************************************************
* ENET peripheral Unbuffered Base Address *
*******************************************************************************/
 
#define ENET_MAC_BASE (AHB_ENET_MAC_B)
#define ENET_DMA_BASE (AHB_ENET_DMA_B)
 
/*******************************************************************************
* DMA peripheral Buffered Base Address *
*******************************************************************************/
 
#define DMA_BASE (AHB_DMA_B)
 
/*******************************************************************************
* EMI peripheral Buffered Base Address *
*******************************************************************************/
 
#define EMI_BASE (AHB_EMI_B)
 
/*******************************************************************************
* FMI peripheral Buffered Base Address *
*******************************************************************************/
 
#define FMI_BASE (AHB_FMI_B)
 
#endif /* Buffered */
 
/*******************************************************************************
* DMA channels Base Address *
*******************************************************************************/
#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST)
#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST)
#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST)
#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST)
#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST)
#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST)
#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST)
#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST)
 
/*******************************************************************************
* EMI Banks peripheral Base Address *
*******************************************************************************/
 
#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST)
#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST)
#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST)
#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST)
#define EMI_CCR_BASE (EMI_BASE + AHB_EMICCR_OFST)
 
/*******************************************************************************
* APB0 Peripherals' Base addresses *
*******************************************************************************/
 
#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST)
#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST)
#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST)
#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST)
#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST)
#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST)
#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST)
#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST)
#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST)
#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST)
#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST)
#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST)
#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST)
#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST)
#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST)
 
/*******************************************************************************
* APB1 Peripherals' Base addresses *
*******************************************************************************/
 
#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST)
#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST)
#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST)
#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST)
#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST)
#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST)
#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST)
#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST)
#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST)
#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST)
#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST)
#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST)
#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST)
 
/*******************************************************************************
* IPs' declaration *
*******************************************************************************/
 
/*------------------------------ Non Debug Mode ------------------------------*/
 
#ifndef DEBUG
 
/*********************************** AHBAPB ***********************************/
 
#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE)
#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE)
 
/************************************* EMI ************************************/
 
#define EMI ((EMI_TypeDef *)EMI_BASE)
 
/************************************* DMA ************************************/
 
#define DMA ((DMA_TypeDef *)DMA_BASE)
#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE)
#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE)
#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE)
 
/************************************* EMI ************************************/
 
#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE)
#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE)
#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE)
#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE)
#define EMI_CCR (vu32*)EMI_CCR_BASE
/************************************* ENET_MAC ************************************/
 
#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
 
/************************************* ENET_DMA ************************************/
 
#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
 
/************************************* FMI ************************************/
 
#define FMI ((FMI_TypeDef *)FMI_BASE)
 
/************************************* VIC ************************************/
 
#define VIC0 ((VIC_TypeDef *)VIC0_BASE)
#define VIC1 ((VIC_TypeDef *)VIC1_BASE)
 
/*******************************************************************************
* APB0 Peripherals' *
*******************************************************************************/
#define WIU ((WIU_TypeDef *)WIU_BASE)
#define TIM0 ((TIM_TypeDef *)TIM0_BASE)
#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)
#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)
#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)
#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE)
#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE)
#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE)
#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE)
#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE)
#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE)
#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE)
/*******************************************************************************
* APB1 Peripherals' *
*******************************************************************************/
#define RTC ((RTC_TypeDef *)RTC_BASE)
#define SCU ((SCU_TypeDef *)SCU_BASE)
#define MC ((MC_TypeDef *)MC_BASE)
#define UART0 ((UART_TypeDef *)UART0_BASE)
#define UART1 ((UART_TypeDef *)UART1_BASE)
#define UART2 ((UART_TypeDef *)UART2_BASE)
#define SSP0 ((SSP_TypeDef *)SSP0_BASE)
#define SSP1 ((SSP_TypeDef *)SSP1_BASE)
#define CAN ((CAN_TypeDef *)CAN_BASE)
#define ADC ((ADC_TypeDef *)ADC_BASE)
#define WDG ((WDG_TypeDef *)WDG_BASE)
#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
 
#else /* DEBUG */
 
/*-------------------------------- Debug Mode --------------------------------*/
 
#ifdef _AHBAPB0
EXT AHBAPB_TypeDef *AHBAPB0;
#endif /* _AHBAPB0 */
 
#ifdef _AHBAPB1
EXT AHBAPB_TypeDef *AHBAPB1;
#endif /*_AHBAPB1 */
 
 
#ifdef _DMA
EXT DMA_TypeDef *DMA;
#endif /* _DMA */
 
 
#ifdef _DMA_Channel0
EXT DMA_Channel_TypeDef *DMA_Channel0;
#endif /* _DMA_Channel0 */
 
#ifdef _DMA_Channel1
EXT DMA_Channel_TypeDef *DMA_Channel1;
#endif /* _DMA_Channel1 */
 
#ifdef _DMA_Channel2
EXT DMA_Channel_TypeDef *DMA_Channel2;
#endif /* _DMA_Channel0 */
 
#ifdef _DMA_Channel3
EXT DMA_Channel_TypeDef *DMA_Channel3;
#endif /* _DMA_Channel0 */
 
#ifdef _DMA_Channel4
EXT DMA_Channel_TypeDef *DMA_Channel4;
#endif /* _DMA_Channel4 */
 
#ifdef _DMA_Channel5
EXT DMA_Channel_TypeDef *DMA_Channel5;
#endif /* _DMA_Channel5 */
 
#ifdef _DMA_Channel6
EXT DMA_Channel_TypeDef *DMA_Channel6;
#endif /* _DMA_Channel6 */
 
#ifdef _DMA_Channel7
EXT DMA_Channel_TypeDef *DMA_Channel7;
#endif /* _DMA_Channel7 */
 
#ifdef _EMI
EXT vu32 *EMI_CCR;
#endif /*_EMI */
 
 
#ifdef _EMI_Bank0
EXT EMI_Bank_TypeDef *EMI_Bank0;
#endif /* _EMI_Bank0 */
 
#ifdef _EMI_Bank1
EXT EMI_Bank_TypeDef *EMI_Bank1;
#endif /* _EMI_Bank1 */
 
#ifdef _EMI_Bank2
EXT EMI_Bank_TypeDef *EMI_Bank2;
#endif /* _EMI_Bank2 */
 
#ifdef _EMI_Bank3
EXT EMI_Bank_TypeDef *EMI_Bank3;
#endif /* _EMI_Bank3 */
 
#ifdef _FMI
EXT FMI_TypeDef *FMI;
#endif /* _FMI */
 
#ifdef _VIC0
EXT VIC_TypeDef *VIC0;
#endif /* _VIC0 */
 
#ifdef _VIC1
EXT VIC_TypeDef *VIC1;
#endif /* _VIC1 */
 
#ifdef _WIU
EXT WIU_TypeDef *WIU;
#endif /* _WIU */
 
#ifdef _TIM0
EXT TIM_TypeDef *TIM0;
#endif /* _TIM0 */
 
#ifdef _TIM1
EXT TIM_TypeDef *TIM1;
#endif /* _TIM1 */
 
#ifdef _TIM2
EXT TIM_TypeDef *TIM2;
#endif /* _TIM2 */
 
#ifdef _TIM3
EXT TIM_TypeDef *TIM3;
#endif /* _TIM3 */
 
#ifdef _GPIO0
EXT GPIO_TypeDef *GPIO0;
#endif /* _GPIO0 */
 
#ifdef _GPIO1
EXT GPIO_TypeDef *GPIO1;
#endif /* _GPIO1 */
 
#ifdef _GPIO2
EXT GPIO_TypeDef *GPIO2;
#endif /* _GPIO2 */
 
#ifdef _GPIO3
EXT GPIO_TypeDef *GPIO3;
#endif /* _GPIO3 */
 
 
#ifdef _GPIO4
EXT GPIO_TypeDef *GPIO4;
#endif /* _GPIO4 */
 
#ifdef _GPIO5
EXT GPIO_TypeDef *GPIO5;
#endif /* _GPIO5 */
 
#ifdef _GPIO6
EXT GPIO_TypeDef *GPIO6;
#endif /* _GPIO6 */
 
 
#ifdef _GPIO7
EXT GPIO_TypeDef *GPIO7;
#endif /* _GPIO7 */
 
#ifdef _GPIO8
EXT GPIO_TypeDef *GPIO8;
#endif /* _GPIO8 */
 
#ifdef _GPIO9
EXT GPIO_TypeDef *GPIO9;
#endif /* _GPIO9 */
 
#ifdef _RTC
EXT RTC_TypeDef *RTC;
#endif /* _RTC */
 
 
#ifdef _SCU
EXT SCU_TypeDef *SCU;
# endif /* _SCU */
 
#ifdef _MC
EXT MC_TypeDef *MC;
#endif /* _MC */
 
#ifdef _UART0
EXT UART_TypeDef *UART0;
#endif /* _UART0 */
 
#ifdef _UART1
EXT UART_TypeDef *UART1;
#endif /* _UART1 */
 
#ifdef _UART2
EXT UART_TypeDef *UART2;
#endif /* _UART2*/
 
#ifdef _SSP0
EXT SSP_TypeDef *SSP0;
#endif /* _SSP0 */
 
#ifdef _SSP1
EXT SSP_TypeDef *SSP1;
#endif /* _SSP1 */
 
#ifdef _CAN
EXT CAN_TypeDef *CAN;
#endif /* _CAN */
 
#ifdef _ADC
EXT ADC_TypeDef *ADC;
#endif /* _ADC */
 
#ifdef _WDG
EXT WDG_TypeDef *WDG;
#endif /* _WDG */
 
#ifdef _I2C0
EXT I2C_TypeDef *I2C0;
#endif /* _I2C0 */
 
#ifdef _I2C1
EXT I2C_TypeDef *I2C1;
#endif /* _I2C1 */
 
#ifdef _ENET
EXT ENET_MAC_TypeDef *ENET_MAC;
EXT ENET_DMA_TypeDef *ENET_DMA;
#endif /* _ENET */
 
#endif /* DEBUG */
 
#endif /* __91x_MAP_H*/
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
 
/tags/V0.22a/libstr91x/include/91x_mc.h
0,0 → 1,191
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_mc.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* MC firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_MC_H
#define __91x_MC_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
 
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u16 MC_OperatingMode;
u16 MC_TachoMode;
u16 MC_TachoEvent_Mode;
u8 MC_Prescaler;
u8 MC_ForcedPWMState;
u16 MC_TachoPrescaler;
u16 MC_PWMMode;
u16 MC_Complementary;
u16 MC_Emergency;
u16 MC_Period;
u16 MC_TachoPeriod;
u16 MC_Channel;
u16 MC_PulseU;
u16 MC_PulseV;
u16 MC_PulseW;
u16 MC_PolarityUL;
u16 MC_PolarityUH;
u16 MC_PolarityVL;
u16 MC_PolarityVH;
u16 MC_PolarityWL;
u16 MC_PolarityWH;
u16 MC_TachoPolarity;
u16 MC_DeadTime;
u8 MC_RepetitionCounter;
} MC_InitTypeDef;
 
typedef enum { DOWN = 0, UP = !DOWN} CountingStatus;
 
/* Exported constants --------------------------------------------------------*/
 
/* MC enable/disable complementary feature */
#define MC_Complementary_Enable 0x0001 /*MC Complementary Mode Enable*/
#define MC_Complementary_Disable 0x0002 /*MC Complementary Mode Disable*/
 
/* MC operating modes */
#define MC_HardwareOperating_Mode 0x0001 /* Hardware operating Mode*/
#define MC_SoftwareOperating_Mode 0x0002 /* Software operating Mode*/
 
/* MC PWM modes */
#define MC_PWMClassical_Mode 0x0001 /*Classical PWM Mode*/
#define MC_PWMZeroCentered_Mode 0x0002 /*Zero Centered PWM Mode*/
 
 
/* MC enable/disable emergency */
#define MC_Emergency_Enable 0x0001 /*MC Emergency Enable*/
#define MC_Emergency_Disable 0x0002 /*MC Emergency Disable*/
 
 
/* MC forced PWM state */
#define MC_Polarity_Inverted 0x0001 /*PWM signal polarity inverted*/
#define MC_Polarity_NonInverted 0x0002 /*PWM signal polarity non-inverted*/
 
 
/* MC tacho modes */
#define MC_TachoOneShot_Mode 0x0001 /*One Shot Tacho Mode*/
#define MC_TachoContinuous_Mode 0x0002 /*Continuous Tacho Mode*/
 
/* MC tacho polarity */
#define MC_TachoEventEdge_None 0x0000 /* Edge None */
#define MC_TachoEventEdge_Falling 0x0001 /* Falling Edge */
#define MC_TachoEventEdge_Rising 0x0002 /* Rising Edge */
#define MC_TachoEventEdge_RisingFalling 0x0003 /* Rising and falling Edge */
 
/* MC channels */
#define MC_Channel_U 0x0001 /* Channel U */
#define MC_Channel_V 0x0002 /* Channel V */
#define MC_Channel_W 0x0003 /* Channel W */
#define MC_Channel_ALL 0x0004 /* All Channels */
 
/* MC tacho event mode */
#define MC_TachoEvent_Hardware_Mode 0x0001 /*Hardware operating Mode*/
#define MC_TachoEvent_Software_Mode 0x0002 /*Software operating Mode*/
 
/* MC interrupts */
#define MC_IT_CMPW 0x0001 /* Compare W interrupt */
#define MC_IT_CMPV 0x0002 /* Compare V interrupt */
#define MC_IT_CMPU 0x0004 /* Compare U interrupt */
#define MC_IT_ZPC 0x0008 /* Zero of PWM counter interrupt */
#define MC_IT_ADT 0x0010 /* Automatic data transfer interrupt */
#define MC_IT_OTC 0x0020 /* Overflow of tacho counter interrupt */
#define MC_IT_CPT 0x0040 /* Capture of tacho counter interrupt */
#define MC_IT_CM0 0x0080 /* Compare 0 interrupt */
 
/* MC flags */
#define MC_FLAG_CMPW 0x0001 /* Compare W pending bit */
#define MC_FLAG_CMPV 0x0002 /* Compare V pending bit */
#define MC_FLAG_CMPU 0x0004 /* Compare U pending bit */
#define MC_FLAG_ZPC 0x0008 /* Zero of PWM counter pending bit */
#define MC_FLAG_ADT 0x0010 /* Automatic data transfer pending bit */
#define MC_FLAG_OTC 0x0020 /* Overflow of tacho counter pending bit */
#define MC_FLAG_CPT 0x0040 /* Capture of tacho counter pending bit */
#define MC_FLAG_CM0 0x0080 /* Compare 0 pending bit */
#define MC_FLAG_EST 0x0100 /* Emergency stop pending bit */
 
/* MC lock levels */
#define MC_LockLevel0 0x0001 /* Level0 */
#define MC_LockLevel1 0x0002 /* Level1 */
#define MC_LockLevel2 0x0004 /* Level2 */
#define MC_LockLevel3 0x0008 /* Level3 */
#define MC_LockLevel4 0x0010 /* Level4 */
 
/* MC counters */
#define MC_DT_Counter 0x0010 /*Dead time counter*/
#define MC_PWM_Counter 0x0020 /*PWM counter*/
 
 
/* MC double update mode feature */
#define MC_DUM 0x0001 /*Double update mode */
 
 
/* MC Trigger events to ADC conversion */
#define MC_ZPC 0x0004 /*Zero of PWM counter trigger event*/
#define MC_CM0 0x0008 /*Compare 0 of PWM trigger event*/
#define MC_ADT 0x000C /*Automatic Data Transfer trigger event */
 
 
 
 
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
void MC_Init(MC_InitTypeDef* MC_InitStruct);
void MC_DeInit(void);
void MC_StructInit(MC_InitTypeDef* MC_InitStruct);
void MC_Cmd(FunctionalState NewState);
void MC_CtrlPWMOutputs(FunctionalState Newstate);
void MC_ITConfig(u16 MC_IT, FunctionalState NewState);
void MC_SetPrescaler(u8 Prescaler);
void MC_SetPeriod(u16 MC_Period);
void MC_SetPulseU(u16 MC_PulseU);
void MC_SetPulseV(u16 MC_PulseV);
void MC_SetPulseW(u16 MC_PulseW);
void MC_SetTachoCompare(u8 MC_Compare);
void MC_PWMModeConfig(u16 MC_PWMMode);
void MC_SetDeadTime(u16 MC_DeadTime);
void MC_EmergencyCmd(FunctionalState NewState);
void MC_EmergencyClear(void);
u16 MC_GetPeriod(void);
u16 MC_GetPulseU(void);
u16 MC_GetPulseV(void);
u16 MC_GetPulseW(void);
u16 MC_GetTachoCapture(void);
void MC_ClearOnTachoCapture(FunctionalState NewState);
void MC_ForceDataTransfer(u8 MC_ForcedData);
void MC_SoftwarePreloadConfig(void);
void MC_SoftwareTachoCapture(void);
CountingStatus MC_GetCountingStatus(void);
FlagStatus MC_GetFlagStatus(u16 MC_FLAG);
void MC_ClearFlag(u16 MC_FLAG);
ITStatus MC_GetITStatus(u16 MC_IT);
void MC_ClearITPendingBit(u16 MC_IT);
void MC_ClearPWMCounter(void);
void MC_ClearTachoCounter(void);
void MC_Lock(u16 MC_LockLevel);
void MC_CounterModeConfig(u16 MC_Counter);
void MC_DoubleUpdateMode(FunctionalState NewState);
void MC_ADCTrigger(u16 IMC_Event, FunctionalState NewState);
void MC_EnhancedStop(FunctionalState NewState);
void MC_EmergencyStopPolarity(FunctionalState NewState);
void MC_DebugOutputProtection(FunctionalState NewState);
 
#endif /* __91x_MC_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
 
/tags/V0.22a/libstr91x/include/91x_rtc.h
0,0 → 1,106
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_rtc.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file provides the RTC library firmware functions
* prototypes & definitions
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_RTC_H
#define __91x_RTC_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
 
/* Private typedef -----------------------------------------------------------*/
typedef struct
{
u8 century;
u8 year;
u8 month;
u8 day;
u8 weekday;
}RTC_DATE;
 
typedef struct
{
u8 hours;
u8 minutes;
u8 seconds;
u16 milliseconds;
}RTC_TIME;
typedef struct
{
u8 day;
u8 hours;
u8 minutes;
u8 seconds;
}RTC_ALARM;
 
/* Exported constants --------------------------------------------------------*/
 
#define BINARY 0
#define BCD 1
 
/*TamperMode*/
#define RTC_TamperMode_Edge 0xFFFFFFEF
#define RTC_TamperMode_Level 0x10
 
/*TamperPol*/
#define RTC_TamperPol_High 0x4
#define RTC_TamperPol_Low 0xFFFFFFFB
 
/*PeriodicClock*/
#define RTC_Per_2Hz 0x10000
#define RTC_Per_16Hz 0x20000
#define RTC_Per_128Hz 0x40000
#define RTC_Per_1024Hz 0x80000
#define RTC_Per_DISABLE 0x0
 
/*RTC_IT*/
#define RTC_IT_Per 0x200000
#define RTC_IT_Alarm 0x800000
#define RTC_IT_Tamper 0x400000
 
/*RTC_FLAG*/
#define RTC_FLAG_Per 0x80000000
#define RTC_FLAG_Alarm 0x40000000
#define RTC_FLAG_Tamper 0x10000000
 
 
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void RTC_DeInit(void);
void RTC_SetDate(RTC_DATE Date);
void RTC_SetTime(RTC_TIME Time);
void RTC_SetAlarm(RTC_ALARM Alarm);
void RTC_GetDate(u8 Format, RTC_DATE * Date);
void RTC_GetTime(u8 Format, RTC_TIME * Time);
void RTC_GetAlarm(u8 Format, RTC_ALARM * Alarm);
void RTC_TamperConfig(u32 TamperMode, u32 TamperPol);
void RTC_TamperCmd(FunctionalState NewState);
void RTC_AlarmCmd(FunctionalState NewState);
void RTC_CalibClockCmd(FunctionalState NewState);
void RTC_SRAMBattPowerCmd(FunctionalState NewState);
void RTC_PeriodicIntConfig(u32 PeriodicClock);
void RTC_ITConfig(u32 RTC_IT, FunctionalState NewState);
FlagStatus RTC_GetFlagStatus(u32 RTC_FLAG);
void RTC_ClearFlag(u32 RTC_FLAG);
#endif /*__91x_RTC_H*/
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
 
 
 
/tags/V0.22a/libstr91x/include/91x_scu.h
0,0 → 1,196
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_scu.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file provides the SCU library firmware functions
* prototypes & definitions
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_SCU_H
#define __91x_SCU_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
 
/* Exported constants --------------------------------------------------------*/
 
/*MCLK_Source*/
#define SCU_MCLK_PLL 0x0
#define SCU_MCLK_RTC 0x1
#define SCU_MCLK_OSC 0x2
 
/*RCLK_Divisor*/
#define SCU_RCLK_Div1 0xFFFFFFE3
#define SCU_RCLK_Div2 0x4
#define SCU_RCLK_Div4 0x8
#define SCU_RCLK_Div8 0xC
#define SCU_RCLK_Div16 0x10
#define SCU_RCLK_Div1024 0x14
 
/*HCLK_Divisor*/
#define SCU_HCLK_Div1 0xFFFFFF9F
#define SCU_HCLK_Div2 0x20
#define SCU_HCLK_Div4 0x40
 
/*PCLK_Divisor*/
#define SCU_PCLK_Div1 0xFFFFFE7F
#define SCU_PCLK_Div2 0x80
#define SCU_PCLK_Div4 0x100
#define SCU_PCLK_Div8 0x180
 
/*FMICLK_Divisor*/
#define SCU_FMICLK_Div1 0xFFFEFFFF
#define SCU_FMICLK_Div2 0x10000
 
/*BRCLK_Divisor*/
#define SCU_BRCLK_Div1 0x200
#define SCU_BRCLK_Div2 0xFFFFFDFF
 
 
/*TIMx*/
#define SCU_TIM01 0x0
#define SCU_TIM23 0x1
 
 
/*USBCLK_Source*/
#define SCU_USBCLK_MCLK 0xFFFFF3FF
#define SCU_USBCLK_MCLK2 0x400
#define SCU_USBCLK_EXT 0x800
 
/*SCU_EMIBCLK*/
#define SCU_EMIBCLK_Div1 0xFFF9FFFF
#define SCU_EMIBCLK_Div2 0x20000
 
/*SCU_EMIMODE*/
#define SCU_EMI_MUX 0xFFFFFFBF
#define SCU_EMI_DEMUX 0x40
 
/*SCU_EMIALE_LEN*/
#define SCU_EMIALE_LEN1 0xFFFFFEFF
#define SCU_EMIALE_LEN2 0x100
 
/*SCU_EMIALE_POL*/
#define SCU_EMIALE_POLLow 0xFFFFFF7F
#define SCU_EMIALE_POLHigh 0x80
 
/*UART_IrDA_Mode*/
#define SCU_UARTMode_IrDA 0x1
#define SCU_UARTMode_UART 0x0
 
/*SCU_UARTx*/
#define SCU_UART0 0x0
#define SCU_UART1 0x1
#define SCU_UART2 0x2
 
/*APBPeriph*/
#define __TIM01 0x1
#define __TIM23 0x2
#define __MC 0x4
#define __UART0 0x8
#define __UART1 0x10
#define __UART2 0x20
#define __I2C0 0x40
#define __I2C1 0x80
#define __SSP0 0x100
#define __SSP1 0x200
#define __CAN 0x400
#define __ADC 0x800
#define __WDG 0x1000
#define __WIU 0x2000
#define __GPIO0 0x4000
#define __GPIO1 0x8000
#define __GPIO2 0x10000
#define __GPIO3 0x20000
#define __GPIO4 0x40000
#define __GPIO5 0x80000
#define __GPIO6 0x100000
#define __GPIO7 0x200000
#define __GPIO8 0x400000
#define __GPIO9 0x800000
#define __RTC 0x1000000
 
/*AHBPeriph*/
#define __FMI 0x1
#define __FPQBC 0x2
#define __SRAM 0x8
#define __SRAM_ARBITER 0x10
#define __VIC 0x20
#define __EMI 0x40
#define __EMI_MEM_CLK 0x80
#define __DMA 0x100
#define __USB 0x200
#define __USB48M 0x400
#define __ENET 0x800
#define __PFQBC_AHB 0x1000
 
/*SCU_IT*/
#define SCU_IT_LVD_RST 0x10
#define SCU_IT_SRAM_ERROR 0x8
#define SCU_IT_ACK_PFQBC 0x4
#define SCU_IT_LOCK_LOST 0x2
#define SCU_IT_LOCK 0x1
 
/*SCU_FLAG*/
#define SCU_FLAG_SRAM_ERROR 0x20
#define SCU_FLAG_ACK_PFQBC 0x10
#define SCU_FLAG_LVD_RESET 0x8
#define SCU_FLAG_WDG_RST 0x4
#define SCU_FLAG_LOCK_LOST 0x2
#define SCU_FLAG_LOCK 0x1
 
 
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source);
ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP);
ErrorStatus SCU_PLLCmd(FunctionalState NewState);
void SCU_RCLKDivisorConfig(u32 RCLK_Divisor);
void SCU_HCLKDivisorConfig(u32 HCLK_Divisor);
void SCU_PCLKDivisorConfig(u32 PCLK_Divisor);
void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState);
void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState);
void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState);
void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState);
void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState);
void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor);
void SCU_TIMExtCLKCmd (u8 TIMx, FunctionalState NewState);
void SCU_USBCLKConfig(u32 USBCLK_Source);
void SCU_PHYCLKConfig(FunctionalState NewState);
void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor);
void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK);
void SCU_EMIModeConfig(u32 SCU_EMIMODE);
void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL);
void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState);
FlagStatus SCU_GetFlagStatus(u32 SCU_Flag);
void SCU_ClearFlag(u32 SCU_Flag);
u32 SCU_GetPLLFreqValue(void);
u32 SCU_GetMCLKFreqValue(void);
u32 SCU_GetRCLKFreqValue(void);
u32 SCU_GetHCLKFreqValue(void);
u32 SCU_GetPCLKFreqValue(void);
void SCU_WakeUpLineConfig(u8 EXTint);
void SCU_SpecIntRunModeConfig(FunctionalState NewState);
void SCU_EnterIdleMode(void);
void SCU_EnterSleepMode(void);
void SCU_UARTIrDASelect(u8 SCU_UARTx, u8 UART_IrDA_Mode);
void SCU_PFQBCCmd(FunctionalState NewState);
void SCU_EMIByte_Select_Pinconfig(FunctionalState NewState);
void SCU_EMIclock_Pinconfig(FunctionalState NewState);
 
#endif /*__91x_SCU_H*/
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_ssp.h
0,0 → 1,116
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_ssp.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* SSP firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_SSP_H
#define __91x_SSP_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
 
/* Exported types ------------------------------------------------------------*/
/* SSP Init structure definition */
typedef struct
{
u16 SSP_FrameFormat ;
u16 SSP_Mode ;
u16 SSP_CPOL ;
u16 SSP_CPHA ;
u16 SSP_DataSize ;
u16 SSP_SlaveOutput ;
u8 SSP_ClockRate ;
u8 SSP_ClockPrescaler ;
}SSP_InitTypeDef;
 
/* Exported constants --------------------------------------------------------*/
/* SSP Frame Format Select */
#define SSP_FrameFormat_TI 0x0010
#define SSP_FrameFormat_Motorola 0xFFCF
#define SSP_FrameFormat_Microwire 0x0020
 
/* SSP Master/Slave Select */
#define SSP_Mode_Master 0xFFFB
#define SSP_Mode_Slave 0x0004
 
/* SSP Clock Polarity */
#define SSP_CPOL_Low 0xFFBF
#define SSP_CPOL_High 0x0040
 
/* SSP Clock Phase */
#define SSP_CPHA_1Edge 0xFF7F
#define SSP_CPHA_2Edge 0x0080
 
/* SSP Data Size */
#define SSP_DataSize_16b 0x000F
#define SSP_DataSize_15b 0x000E
#define SSP_DataSize_14b 0x000D
#define SSP_DataSize_13b 0x000C
#define SSP_DataSize_12b 0x000B
#define SSP_DataSize_11b 0x000A
#define SSP_DataSize_10b 0x0009
#define SSP_DataSize_9b 0x0008
#define SSP_DataSize_8b 0x0007
#define SSP_DataSize_7b 0x0006
#define SSP_DataSize_6b 0x0005
#define SSP_DataSize_5b 0x0004
#define SSP_DataSize_4b 0x0003
 
/* SSP Slave output config */
#define SSP_SlaveOutput_Enable 0xFFF7
#define SSP_SlaveOutput_Disable 0x0008
 
/* SSP Interrupts */
#define SSP_IT_TxFifo 0x0008
#define SSP_IT_RxFifo 0x0004
#define SSP_IT_RxTimeOut 0x0002
#define SSP_IT_RxOverrun 0x0001
 
/* SSP Flags */
#define SSP_FLAG_Busy 0x0024
#define SSP_FLAG_RxFifoFull 0x0023
#define SSP_FLAG_RxFifoNotEmpty 0x0022
#define SSP_FLAG_TxFifoNotFull 0x0021
#define SSP_FLAG_TxFifoEmpty 0x0020
#define SSP_FLAG_TxFifo 0x0043
#define SSP_FLAG_RxFifo 0x0042
#define SSP_FLAG_RxTimeOut 0x0041
#define SSP_FLAG_RxOverrun 0x0040
 
/* SSP DMA Requests */
#define SSP_DMA_Transmit 0x0002
#define SSP_DMA_Receive 0x0001
 
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
 
void SSP_DeInit(SSP_TypeDef* SSPx);
void SSP_Init(SSP_TypeDef* SSPx, SSP_InitTypeDef* SSP_InitStruct);
void SSP_StructInit(SSP_InitTypeDef* SSP_InitStruct);
void SSP_Cmd(SSP_TypeDef* SSPx, FunctionalState NewState);
void SSP_ITConfig(SSP_TypeDef* SSPx, u16 SSP_IT, FunctionalState NewState);
void SSP_DMACmd(SSP_TypeDef* SSPx, u16 SSP_DMATransfert, FunctionalState NewState);
void SSP_SendData(SSP_TypeDef* SSPx, u16 Data);
u16 SSP_ReceiveData(SSP_TypeDef* SSPx);
void SSP_LoopBackConfig(SSP_TypeDef* SSPx, FunctionalState NewState);
FlagStatus SSP_GetFlagStatus(SSP_TypeDef* SSPx, u16 SSP_FLAG);
void SSP_ClearFlag(SSP_TypeDef* SSPx, u16 SSP_FLAG);
ITStatus SSP_GetITStatus(SSP_TypeDef* SSPx, u16 SSP_IT);
void SSP_ClearITPendingBit(SSP_TypeDef* SSPx, u16 SSP_IT);
 
#endif /* __91x_SSP_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
 
/tags/V0.22a/libstr91x/include/91x_tim.h
0,0 → 1,152
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_tim.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* TIM firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_TIM_H
#define __91x_TIM_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
#include "91x_scu.h"
 
/* Exported types ----------------------------------------------------------- */
 
/* TIM Init structure define */
typedef struct
{
u16 TIM_Mode; /* Timer mode */
u16 TIM_OC1_Modes; /* Output Compare 1 Mode: Timing or Wave */
u16 TIM_OC2_Modes; /* Output Compare 2 Mode: Timing or Wave */
u16 TIM_Clock_Source; /* Timer Clock source APB/SCU/EXTERNAL */
u16 TIM_Clock_Edge; /* Timer Clock Edge: Rising or Falling Edge */
u16 TIM_OPM_INPUT_Edge; /* Timer Input Capture 1 Edge used in OPM Mode */
u16 TIM_ICAP1_Edge; /* Timer Input Capture 1 Edge used in ICAP1 Mode */
u16 TIM_ICAP2_Edge; /* Timer Input Capture 2 Edge used in ICAP2 Mode */
u8 TIM_Prescaler; /* Timer Prescaler factor */
u16 TIM_Pulse_Level_1; /* Level applied on the Output Compare Pin 1 */
u16 TIM_Pulse_Level_2; /* Level applied on the Output Compare Pin 2 */
u16 TIM_Period_Level; /* Level applied during the Period of a PWM Mode */
u16 TIM_Pulse_Length_1; /* Pulse 1 Length used in Output Compare 1 Mode */
u16 TIM_Pulse_Length_2; /* Pulse 2 Length used in Output Compare 2 Mode */
u16 TIM_Full_Period; /* Period Length used in PWM Mode */
} TIM_InitTypeDef;
 
typedef enum
{
TIM_START,
TIM_STOP,
TIM_CLEAR
} TIM_CounterOperations;
 
/* Exported constants --------------------------------------------------------*/
 
/* TIM MODE */
#define TIM_PWMI 0x4000 /* PWM INPUT Mode */
#define TIM_OCM_CHANNEL_1 0x0040 /* OUTPUT COMPARE CHANNEL 1 Mode */
#define TIM_OCM_CHANNEL_2 0x0080 /* OUTPUT COMPARE CHANNEL 2 Mode */
#define TIM_OCM_CHANNEL_12 0x00C0 /* OUTPUT COMPARE CHANNEL 1 & 2 Mode */
#define TIM_PWM 0x0010 /* PWM Mode */
#define TIM_OPM 0x0020 /* ONE PULSE Mode */
#define TIM_ICAP_CHANNEL_1 0x0400 /* INPUT CAPTURE 1 Mode */
#define TIM_ICAP_CHANNEL_2 0x0500 /* INPUT CAPTURE 2 Mode */
#define TIM_ICAP_CHANNEL_12 0x0600 /* INPUT CAPTURE 1 & 2 Mode */
 
/* TIM OUTPUT COMPARE MODE */
#define TIM_WAVE 0x0001
#define TIM_TIMING 0x0002
 
/* TIM CLOCK SOURCE */
#define TIM_CLK_APB 0xFFFE
#define TIM_CLK_EXTERNAL 0x0001
 
 
/* TIM CLOCK EDGE */
#define TIM_CLK_EDGE_FALLING 0xFFFD
#define TIM_CLK_EDGE_RISING 0x0002
 
/* TIM OPM INPUT EDGE */
#define TIM_OPM_EDGE_FALLING 0xFFFB
#define TIM_OPM_EDGE_RISING 0x0004
 
/* TIM ICAPA INPUT EDGE */
#define TIM_ICAP1_EDGE_FALLING 0xFFFB
#define TIM_ICAP1_EDGE_RISING 0x0004
 
/* TIM ICAPB INPUT EDGE */
#define TIM_ICAP2_EDGE_FALLING 0xFFF7
#define TIM_ICAP2_EDGE_RISING 0x0008
 
/* TIM OUTPUT LEVEL */
#define TIM_HIGH 0x0200
#define TIM_LOW 0x0300
 
/* TIM OUTPUT EDGE */
#define TIM_OUTPUT_EDGE_RISING 0x8000
#define TIM_OUTPUT_EDGE_FALLING 0x0800
 
/* TIM channels */
#define TIM_PWM_OC1_Channel 0x1 /* PWM/Output Compare 1 Channel */
#define TIM_OC2_Channel 0x2 /* Output Compare 2 Channel */
 
/* TIM DMA SOURCE */
#define TIM_DMA_IC1 0x0000 /* Input Capture Channel 1 DMA Source */
#define TIM_DMA_OC1 0x1000 /* OUTPUT Compare Channel 1 DMA Source */
#define TIM_DMA_IC2 0x2000 /* Input Capture Channel 2 DMA Source */
#define TIM_DMA_OC2 0x3000 /* OUTPUT Compare Channel 2 DMA Source */
 
/* TIM DMA ENABLE or DISABLE */
#define TIM_DMA_ENABLE 0x0400 /* DMA Enable */
#define TIM_DMA_DISABLE 0xFBFF /* DMA Disable */
 
/* TIM Interruption Sources*/
#define TIM_IT_IC1 0x8000 /* Input Capture Channel 1 Interrupt Source */
#define TIM_IT_OC1 0x4000 /* Output Compare Channel 1 Interrupt Source */
#define TIM_IT_TO 0x2000 /* Timer OverFlow Interrupt Source */
#define TIM_IT_IC2 0x1000 /* Input Capture Channel 2 Interrupt Source */
#define TIM_IT_OC2 0x0800 /* Output Compare Channel 2 Interrupt Source */
 
/* TIM Flags */
#define TIM_FLAG_IC1 0x8000 /* Input Capture Channel 1 Flag */
#define TIM_FLAG_OC1 0x4000 /* Output Compare Channel 1 Flag */
#define TIM_FLAG_TO 0x2000 /* Timer OverFlow Flag */
#define TIM_FLAG_IC2 0x1000 /* Input Capture Channel 2 Flag */
#define TIM_FLAG_OC2 0x0800 /* Output Compare Channel 2 Flag */
 
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void TIM_Init(TIM_TypeDef *TIMx, TIM_InitTypeDef *TIM_InitStruct);
void TIM_DeInit(TIM_TypeDef *TIMx);
void TIM_StructInit(TIM_InitTypeDef *TIM_InitStruct);
void TIM_CounterCmd(TIM_TypeDef *TIMx, TIM_CounterOperations TIM_operation);
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, u8 TIM_Prescaler);
u8 TIM_GetPrescalerValue(TIM_TypeDef *TIMx);
u16 TIM_GetCounterValue(TIM_TypeDef *TIMx);
u16 TIM_GetICAP1Value(TIM_TypeDef *TIMx);
u16 TIM_GetICAP2Value(TIM_TypeDef *TIMx);
void TIM_SetPulse(TIM_TypeDef *TIMx,u16 TIM_Channel ,u16 TIM_Pulse);
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, u16 TIM_Flag);
void TIM_ClearFlag(TIM_TypeDef *TIMx, u16 TIM_Flag);
u16 TIM_GetPWMIPulse(TIM_TypeDef *TIMx);
u16 TIM_GetPWMIPeriod(TIM_TypeDef *TIMx);
void TIM_ITConfig(TIM_TypeDef *TIMx, u16 TIM_IT, FunctionalState TIM_Newstate);
void TIM_DMAConfig(TIM_TypeDef *TIMx, u16 TIM_DMA_Sources);
void TIM_DMACmd(TIM_TypeDef *TIMx, FunctionalState TIM_Newstate);
 
#endif /* __91x_TIM_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_type.h
0,0 → 1,47
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_type.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : It contains common types and constants used in all the
* peripherals' drivers.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*********************************************************************************/
 
#ifndef __91x_type_H
#define __91x_type_H
 
typedef long long u64;
typedef unsigned long u32;
typedef unsigned short u16;
typedef unsigned char u8;
 
typedef signed long s32;
typedef signed short s16;
typedef signed char s8;
 
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char vu8;
 
typedef volatile signed long vs32;
typedef volatile signed short vs16;
typedef volatile signed char vs8;
 
typedef enum { FALSE = 0, TRUE = !FALSE } bool;
 
typedef enum { RESET = 0, SET = !RESET } FlagStatus, ITStatus;
 
typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
 
typedef enum { ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
 
#endif /* __91x_type_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_uart.h
0,0 → 1,171
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_uart.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* UART firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_UART_H
#define __91x_UART_H
 
/* Includes ------------------------------------------------------------------*/
#include <91x_map.h>
 
/* Exported types ------------------------------------------------------------*/
/* UART FIFO Level enumeration */
typedef enum
{
UART_FIFOLevel_1_8 = 0x0000, /* FIFO size 16 bytes, FIFO level 2 bytes */
UART_FIFOLevel_1_4 = 0x0001, /* FIFO size 16 bytes, FIFO level 4 bytes */
UART_FIFOLevel_1_2 = 0x0002, /* FIFO size 16 bytes, FIFO level 8 bytes */
UART_FIFOLevel_3_4 = 0x0003, /* FIFO size 16 bytes, FIFO level 12 bytes */
UART_FIFOLevel_7_8 = 0x0004 /* FIFO size 16 bytes, FIFO level 14 bytes */
}UART_FIFOLevel;
 
/* UART Init Structure definition */
typedef struct
{
u16 UART_WordLength;
u16 UART_StopBits;
u16 UART_Parity;
u32 UART_BaudRate;
u16 UART_HardwareFlowControl;
u16 UART_Mode;
u16 UART_FIFO;
UART_FIFOLevel UART_TxFIFOLevel;
UART_FIFOLevel UART_RxFIFOLevel;
}UART_InitTypeDef;
 
 
/* UART RTS enumeration */
typedef enum
{
LowLevel = 0,
HighLevel
}UART_LevelTypeDef;
 
/* Exported constants --------------------------------------------------------*/
/* UART Data Length */
#define UART_WordLength_5D 0x0000 /* 5 bits Data */
#define UART_WordLength_6D 0x0020 /* 6 bits Data */
#define UART_WordLength_7D 0x0040 /* 7 bits Data */
#define UART_WordLength_8D 0x0060 /* 8 bits Data */
 
/* UART Stop Bits */
#define UART_StopBits_1 0xFFF7 /* Disable two stop bit is transmitted
at the end of frame */
#define UART_StopBits_2 0x0008 /* Enable Two stop bits are transmitted
at the end of frame */
/* UART Parity */
#define UART_Parity_No 0x0000 /* Parity Disable */
#define UART_Parity_Even 0x0006 /* Even Parity */
#define UART_Parity_Odd 0x0002 /* Odd Parity */
#define UART_Parity_OddStick 0x0082 /* 1 is transmitted as bit parity */
#define UART_Parity_EvenStick 0x0086 /* 0 is transmitted as bit parity */
 
/* UART Hardware Flow Control */
#define UART_HardwareFlowControl_None 0x0000 /* HFC Disable */
#define UART_HardwareFlowControl_RTS 0x4000 /* RTS Enable */
#define UART_HardwareFlowControl_CTS 0x8000 /* CTS Enable */
#define UART_HardwareFlowControl_RTS_CTS 0xC000 /* CTS and RTS Enable */
 
/* UART Mode */
#define UART_Mode_Rx 0x0200 /* UART Rx Enabled */
#define UART_Mode_Tx 0x0100 /* UART Tx Enbled */
#define UART_Mode_Tx_Rx 0x0300 /* UART Tx and Rx Enabled */
 
/* UART FIFO */
#define UART_FIFO_Disable 0xFFEF /* FIFOs Disable */
#define UART_FIFO_Enable 0x0010 /* FIFOs Enable */
 
/* UART Interrupt definition */
#define UART_IT_OverrunError 0x0400 /* Overrun Error interrupt mask */
#define UART_IT_BreakError 0x0200 /* Break Error interrupt mask */
#define UART_IT_ParityError 0x0100 /* Parity Error interrupt mask */
#define UART_IT_FrameError 0x0080 /* Frame Error interrupt mask */
#define UART_IT_ReceiveTimeOut 0x0040 /* Receive Time Out interrupt mask */
#define UART_IT_Transmit 0x0020 /* Transmit interrupt mask */
#define UART_IT_Receive 0x0010 /* Receive interrupt mask */
#define UART_IT_DSR 0x0008 /* DSR interrupt mask */
#define UART_IT_DCD 0x0004 /* DCD interrupt mask */
#define UART_IT_CTS 0x0002 /* CTS interrupt mask */
#define UART_IT_RI 0x0001 /* RI interrupt mask */
 
/* UART DMA On Error */
#define UART_DMAOnError_Enable 0xFFFB /* DMA receive request enabled
when the UART error interrupt
is asserted. */
#define UART_DMAOnError_Disable 0x0004 /* DMA receive request disabled
when the UART error interrupt
is asserted. */
/* UART DMA Request */
#define UART_DMAReq_Tx 0x02 /* Transmit DMA Enable */
#define UART_DMAReq_Rx 0x01 /* Receive DMA Enable */
 
/* UART FLAG */
#define UART_FLAG_OverrunError 0x23 /* Overrun error flag */
#define UART_FLAG_Break 0x22 /* break error flag */
#define UART_FLAG_ParityError 0x21 /* parity error flag */
#define UART_FLAG_FrameError 0x20 /* frame error flag */
#define UART_FLAG_RI 0x48 /* RI flag */
#define UART_FLAG_TxFIFOEmpty 0x47 /* Transmit FIFO Empty flag */
#define UART_FLAG_RxFIFOFull 0x46 /* Receive FIFO Full flag */
#define UART_FLAG_TxFIFOFull 0x45 /* Transmit FIFO Full flag */
#define UART_FLAG_RxFIFOEmpty 0x44 /* Receive FIFO Empty flag */
#define UART_FLAG_Busy 0x43 /* UART Busy flag */
#define UART_FLAG_DCD 0x42 /* DCD flag */
#define UART_FLAG_DSR 0x41 /* DSR flag */
#define UART_FLAG_CTS 0x40 /* CTS flag */
#define UART_RawIT_OverrunError 0x6A /* Overrun Error Raw IT flag */
#define UART_RawIT_BreakError 0x69 /* Break Error Raw IT flag */
#define UART_RawIT_ParityError 0x68 /* Parity Error Raw IT flag */
#define UART_RawIT_FrameError 0x67 /* Frame Error Raw IT flag */
#define UART_RawIT_ReceiveTimeOut 0x66 /* ReceiveTimeOut Raw IT flag */
#define UART_RawIT_Transmit 0x65 /* Transmit Raw IT flag */
#define UART_RawIT_Receive 0x64 /* Receive Raw IT flag */
#define UART_RawIT_DSR 0x63 /* DSR Raw IT flag */
#define UART_RawIT_DCD 0x62 /* DCD Raw IT flag */
#define UART_RawIT_CTS 0x61 /* CTS Raw IT flag */
#define UART_RawIT_RI 0x60 /* RI Raw IT flag */
 
/*IrDAx select*/
#define IrDA0 0x01 /*IrDA0 select*/
#define IrDA1 0x02 /*IrDA0 select*/
#define IrDA2 0x03 /*IrDA0 select*/
 
/* Exported macro ------------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
void UART_DeInit(UART_TypeDef* UARTx);
void UART_Init(UART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct);
void UART_StructInit(UART_InitTypeDef* UART_InitStruct);
void UART_Cmd(UART_TypeDef* UARTx, FunctionalState NewState);
void UART_ITConfig(UART_TypeDef* UARTx, u16 UART_IT, FunctionalState NewState);
void UART_DMAConfig(UART_TypeDef* UARTx, u16 UART_DMAOnError);
void UART_DMACmd(UART_TypeDef* UARTx, u8 UART_DMAReq, FunctionalState NewState);
void UART_LoopBackConfig(UART_TypeDef* UARTx, FunctionalState NewState);
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, u16 UART_FLAG);
void UART_ClearFlag(UART_TypeDef* UARTx);
void UART_ClearITPendingBit(UART_TypeDef* UARTx, u16 UART_IT);
void UART_IrDALowPowerConfig(u8 IrDAx, FunctionalState NewState);
void UART_IrDACmd(u8 IrDAx, FunctionalState NewState);
void UART_IrDASetCounter(u8 IrDAx, u32 IrDA_Counter);
void UART_SendData(UART_TypeDef* UARTx, u8 Data);
u8 UART_ReceiveData(UART_TypeDef* UARTx);
void UART_SendBreak(UART_TypeDef* UARTx);
void UART_DTRConfig(UART_LevelTypeDef LevelState);
void UART_RTSConfig(UART_LevelTypeDef LevelState);
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, u16 UART_IT);
 
#endif /* __91x_UART_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_vic.h
0,0 → 1,92
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_vic.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* VIC firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
 
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_VIC_H
#define __91x_VIC_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
#include "91x_it.h"
 
/* Exported types ------------------------------------------------------------*/
/* Type of interrupt */
typedef enum
{
VIC_IRQ,
VIC_FIQ
} VIC_ITLineMode;
 
/* Exported constants --------------------------------------------------------*/
 
/* VIC sources*/
 
#define WDG_ITLine 0
#define SW_ITLine 1
#define ARMRX_ITLine 2
#define ARMTX_ITLine 3
#define TIM0_ITLine 4
#define TIM1_ITLine 5
#define TIM2_ITLine 6
#define TIM3_ITLine 7
#define USBHP_ITLine 8
#define USBLP_ITLine 9
#define SCU_ITLine 10
#define ENET_ITLine 11
#define DMA_ITLine 12
#define CAN_ITLine 13
#define MC_ITLine 14
#define ADC_ITLine 15
#define UART0_ITLine 16
#define UART1_ITLine 17
#define UART2_ITLine 18
#define I2C0_ITLine 19
#define I2C1_ITLine 20
#define SSP0_ITLine 21
#define SSP1_ITLine 22
#define LVD_ITLine 23
#define RTC_ITLine 24
#define WIU_ITLine 25
#define EXTIT0_ITLine 26
#define EXTIT1_ITLine 27
#define EXTIT2_ITLine 28
#define EXTIT3_ITLine 29
#define USBWU_ITLine 30
#define PFQBC_ITLine 31
 
 
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
 
void VIC_DeInit(void);
void VIC_InitDefaultVectors(void);
FlagStatus VIC_GetIRQStatus(u16 VIC_Source);
FlagStatus VIC_GetFIQStatus(u16 VIC_Source);
FlagStatus VIC_GetSourceITStatus(u16 VIC_Source);
void VIC_ITCmd(u16 VIC_Source, FunctionalState VIC_NewState);
void VIC_SWITCmd(u16 VIC_Source, FunctionalState VIC_NewState);
void VIC_ProtectionCmd(FunctionalState VIC_NewState);
u32 VIC_GetCurrentISRAdd(VIC_TypeDef* VICx);
u32 VIC_GetISRVectAdd(u16 VIC_Source,u16 VIC_Priority);
void VIC_Config(u16 VIC_Source, VIC_ITLineMode VIC_LineMode, u8 VIC_Priority);
 
#endif /* __91x_VIC_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
 
/tags/V0.22a/libstr91x/include/91x_wdg.h
0,0 → 1,78
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_wdg.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* WDG firmware library.
********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
 
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __91x_WDG_H
#define __91x_WDG_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
 
/* Exported types ------------------------------------------------------------*/
typedef struct
{
u16 WDG_ClockSource;
u16 WDG_Prescaler;
u16 WDG_Preload;
 
} WDG_InitTypeDef;
 
/* Exported constants --------------------------------------------------------*/
 
/* WDG_Mode */
#define WDG_Mode_Wdg 0x0001 /*WDG configured to run in watchdog mode.*/
#define WDG_Mode_Timer 0xFFFE /*WDG configured to be in Free-running Timer mode.*/
 
 
/* WDG_ClockSource */
#define WDG_ClockSource_Rtc 0x0004 /* External clock ( 32 khz RTC clock ) will be used as counting clock.*/
#define WDG_ClockSource_Apb 0xFFFB /*The APB clock signal will be used as counting clock.*/
 
/* WDG_Prescaler */
/*This member must be a number between 0x00 and 0xFF.
Specifies the Prescaler value to divide the clock source.
The clock of the Watchdog Timer Counter is divided by " WDG_Prescaler + 1".*/
 
 
 
/* WDG_Preload */
/*This member must be a number between 0x0000 and 0xFFFF.
This value is loaded in the WDG Counter when it starts counting.*/
 
 
/* WDG Sequence */
#define WDG_KeyValue1 0xA55A
#define WDG_KeyValue2 0x5AA5
 
/* Exported macro ------------------------------------------------------------*/
 
 
/* Exported functions ------------------------------------------------------- */
 
void WDG_Init(WDG_InitTypeDef* WDG_InitStruct);
void WDG_StructInit(WDG_InitTypeDef* WDG_InitStruct);
void WDG_TimerModeCmd(FunctionalState NewState);
void WDG_StartWatchdogMode(void);
void WDG_ITConfig(FunctionalState NewState);
u16 WDG_GetCounter(void);
FlagStatus WDG_GetFlagStatus(void);
void WDG_ClearFlag(void);
ITStatus WDG_GetITStatus(void);
void WDG_ClearITPendingBit(void);
void WDG_Reload(void);
#endif /* __WDG_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/
/tags/V0.22a/libstr91x/include/91x_wiu.h
0,0 → 1,90
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
* File Name : 91x_wiu.h
* Author : MCD Application Team
* Version : V2.1
* Date : 12/22/2008
* Description : This file contains all the functions prototypes for the
* WIU firmware library.
**********************************************************************************
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*********************************************************************************/
 
/* Define to prevent recursive inclusion ------------------------------------ */
#ifndef __91x_WIU_H
#define __91x_WIU_H
 
/* Includes ------------------------------------------------------------------*/
#include "91x_map.h"
 
/* Exported types ------------------------------------------------------------*/
/* WIU Init structure type define */
typedef struct
{
u8 WIU_TriggerEdge;
u32 WIU_Line ;
}WIU_InitTypeDef ;
 
/* Exported constants --------------------------------------------------------*/
/* Wake-up line triggering edge */
#define WIU_FallingEdge 0x00
#define WIU_RisingEdge 0x01
 
/* Wake-up lines*/
#define WIU_Line0 0x0001
#define WIU_Line1 (WIU_Line0<<1)
#define WIU_Line2 (WIU_Line1<<1)
#define WIU_Line3 (WIU_Line2<<1)
#define WIU_Line4 (WIU_Line3<<1)
#define WIU_Line5 (WIU_Line4<<1)
#define WIU_Line6 (WIU_Line5<<1)
#define WIU_Line7 (WIU_Line6<<1)
#define WIU_Line8 (WIU_Line7<<1)
#define WIU_Line9 (WIU_Line8<<1)
#define WIU_Line10 (WIU_Line9<<1)
#define WIU_Line11 (WIU_Line10<<1)
#define WIU_Line12 (WIU_Line11<<1)
#define WIU_Line13 (WIU_Line12<<1)
#define WIU_Line14 (WIU_Line13<<1)
#define WIU_Line15 (WIU_Line14<<1)
#define WIU_Line16 (WIU_Line15<<1)
#define WIU_Line17 (WIU_Line16<<1)
#define WIU_Line18 (WIU_Line17<<1)
#define WIU_Line19 (WIU_Line18<<1)
#define WIU_Line20 (WIU_Line19<<1)
#define WIU_Line21 (WIU_Line20<<1)
#define WIU_Line22 (WIU_Line21<<1)
#define WIU_Line23 (WIU_Line22<<1)
#define WIU_Line24 (WIU_Line23<<1)
#define WIU_Line25 (WIU_Line24<<1)
#define WIU_Line26 (WIU_Line25<<1)
#define WIU_Line27 (WIU_Line26<<1)
#define WIU_Line28 (WIU_Line27<<1)
#define WIU_Line29 (WIU_Line28<<1)
#define WIU_Line30 (WIU_Line29<<1)
#define WIU_Line31 (WIU_Line30<<1)
 
/* Exported constants --------------------------------------------------------*/
/* Module private variables --------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
 
void WIU_DeInit(void);
void WIU_StructInit(WIU_InitTypeDef* WIU_InitStruct);
void WIU_Init(WIU_InitTypeDef* WIU_InitStruct);
void WIU_Cmd(FunctionalState NewState );
void WIU_GenerateSWInterrupt(u32 WIU_Line);
FlagStatus WIU_GetFlagStatus(u32 WIU_Line);
void WIU_ClearFlag(u32 WIU_Line);
ITStatus WIU_GetITStatus(u32 WIU_Line);
void WIU_ClearITPendingBit(u32 WIU_Line);
 
#endif /* __91x_WIU_H */
 
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/