| 47,16 → 47,22 |
|---|
| |
| // Normal Mode (bits: WGM13=0, WGM12=0, WGM11=0, WGM10=0) |
| // Compare output pin A & B is disabled (bits: COM1A1=0, COM1A0=0, COM1B1=0, COM1B0=0) |
| // Set clock source to SYSCLK/64 (bit: CS12=0, CS11=1, CS10=1) |
| // Set clock source to SYSCLK/8 (bit: CS12=0, CS11=1, CS10=0) |
| // Enable input capture noise cancler (bit: ICNC1=1) |
| // Trigger on positive edge of the input capture pin (bit: ICES1=1), |
| // Therefore the counter incremets at a clock of 20 MHz/64 = 312.5 kHz or 3.2�s |
| // The longest period is 0xFFFF / 312.5 kHz = 0.209712 s. |
| TCCR1A &= ~((1 << COM1A1) | (1 << COM1A0) | (1 << COM1B1) | (1 << COM1B0) | (1 << WGM11) | (1 << WGM10)); |
| TCCR1B &= ~((1 << WGM13) | (1 << WGM12) | (1 << CS12)); |
| TCCR1B |= (1 << CS11) | (1 << ICES1) | (1 << ICNC1); |
| TCCR1C &= ~((1 << FOC1A) | (1 << FOC1B)); |
| TCCR1A &= ~((1<<COM1A1)| (1<<COM1A0) | (1<<COM1B1) | (1<<COM1B0) | (1<<WGM11) | (1<<WGM10)); |
| TCCR1B &= ~((1<<WGM13) | (1<<WGM12) | (1<<CS12)); |
| TCCR1B |= (1<<CS11) | (1<<ICNC1); |
| TCCR1C &= ~((1<<FOC1A) | (1<<FOC1B)); |
| |
| if (channelMap.RCPolarity) { |
| TCCR1B |= (1<<ICES1); |
| } else { |
| TCCR1B &= ~(1<<ICES1); |
| } |
| |
| // Timer/Counter1 Interrupt Mask Register |
| // Enable Input Capture Interrupt (bit: ICIE1=1) |
| // Disable Output Compare A & B Match Interrupts (bit: OCIE1B=0, OICIE1A=0) |
| 232,6 → 238,6 |
|---|
| // Do nothing. |
| } |
| |
| int16_t RC_getZeroThrottle() { |
| int16_t RC_getZeroThrottle(void) { |
| return TIME (-0.5); |
| } |