Subversion Repositories NaviCtrl

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Ignore whitespace Rev 674 → Rev 675

/trunk/uart1.c
140,12 → 140,12
#endif
 
// the primary rx fifo
#define UART1_RX_FIFO_LEN 1024
#define UART1_RX_FIFO_LEN 1500
u8 UART1_rxfifobuffer[UART1_RX_FIFO_LEN];
fifo_t UART1_rx_fifo;
 
// the rx buffer
#define UART1_RX_BUFFER_LEN 1024
#define UART1_RX_BUFFER_LEN 1500
u8 UART1_rbuffer[UART1_RX_BUFFER_LEN];
Buffer_t UART1_rx_buffer;
 
271,6 → 271,15
GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2; // UART1_TX
GPIO_Init(GPIO3, &GPIO_InitStructure);
 
// Control of PORT3.7 (FC-UART)
GPIO_StructInit(&GPIO_InitStructure);
GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7;
GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt1;
GPIO_Init(GPIO3, &GPIO_InitStructure);
DISABLE_FC_UART;
 
/* UART1 configured as follow:
- Word Length = 8 Bits
- One Stop Bit
369,6 → 378,7
fifo_purge(&UART1_rx_fifo); // flush the whole fifo init buffer
}
DebugUART = UART1;
DISABLE_FC_UART;
}
abortState = 0;
break;
522,6 → 532,7
switch(SerialMsg.pData[0])
{
case UART_FLIGHTCTRL:
ENABLE_FC_UART;
UART2_Init(); // initialize UART2 to FC pins
fifo_purge(&UART1_rx_fifo);
TIMER2_Deinit(); // reduce irq load
/trunk/uart1.h
15,6 → 15,9
#define NC_ERROR0_GPS_RX 0x10
#define NC_ERROR0_COMPASS_VALUE 0x20
 
#define DISABLE_FC_UART GPIO_WriteBit(GPIO3, GPIO_Pin_7, Bit_SET);
#define ENABLE_FC_UART GPIO_WriteBit(GPIO3, GPIO_Pin_7, Bit_RESET);
 
typedef struct
{
u8 SWMajor;