| 147,12 → 147,11 |
|---|
| static unsigned char UartState = 0; |
| unsigned char CrcOkay = 0; |
| |
| if (JetiUpdateModeActive) { UDR1 = UDR0; return; } |
| if (JetiUpdateModeActive == 1) { UDR1 = UDR0; return; } |
| if (JetiUpdateModeActive == 2) { RxdBuffer[0] = UDR0; return; } |
| |
| SioTmp = UDR0; |
| |
| |
| |
| if(buf_ptr >= MAX_SENDE_BUFF) UartState = 0; |
| if(SioTmp == '\r' && UartState == 2) |
| { |
| 470,35 → 469,70 |
|---|
| case 'j': |
| { uint16_t ubrr = (uint16_t) ((uint32_t) F_CPU/ (8 * 38400L) - 1); |
| |
| JetiUpdateModeActive = 1; |
| |
| |
| UBRR1H = (uint8_t)(ubrr>>8); |
| UBRR1L = (uint8_t)ubrr; |
| cli(); |
| |
| UBRR0H = UBRR1H; |
| UBRR0L = UBRR1L; |
| // disable receiver and transmitter |
| UCSR0B &= ~(1 << TXEN0); |
| UCSR0B &= ~(1 << RXEN0); |
| UCSR1B &= ~(1 << TXEN1); |
| UCSR1B &= ~(1 << RXEN1); |
| |
| UCSR1C &= ~(1 << UPM11); // 0 = parity disabled |
| UCSR1C &= ~(1 << UPM10); |
| // disable RX-Interrupt |
| UCSR0B &= ~(1 << RXCIE0); |
| UCSR1B &= ~(1 << RXCIE1); |
| // disable TX-Interrupt |
| UCSR0B &= ~(1 << TXCIE0); |
| UCSR1B &= ~(1 << TXCIE1); |
| |
| // 1 stop bit |
| UCSR1C &= ~(1 << USBS1); |
| UCSR0C &= ~(1 << USBS0); |
| // flush receive buffer explicit |
| while ( UCSR1A & (1<<RXC1) ) UDR1; |
| while ( UCSR0A & (1<<RXC0) ) UDR0; |
| |
| // 8-bit |
| UCSR1B &= ~(1 << UCSZ12); |
| UCSR1C |= (1 << UCSZ11); |
| UCSR1C |= (1 << UCSZ10); |
| |
| UCSR0B &= ~(1 << TXCIE0); |
| UCSR1B &= ~(1 << TXCIE1); |
| if (pRxData[0] == 0) |
| { |
| UBRR1H = (uint8_t)(ubrr>>8); |
| UBRR1L = (uint8_t)ubrr; |
| |
| UBRR0H = UBRR1H; |
| UBRR0L = UBRR1L; |
| // 8-bit |
| UCSR1B &= ~(1 << UCSZ12); |
| UCSR1C |= (1 << UCSZ11); |
| UCSR1C |= (1 << UCSZ10); |
| |
| UCSR1C &= ~(1 << UPM11); // 0 = parity disabled |
| UCSR1C &= ~(1 << UPM10); |
| JetiUpdateModeActive = 1; |
| |
| |
| } |
| else JetiUpdateModeActive = 2; |
| |
| // 1 stop bit |
| UCSR1C &= ~(1 << USBS1); |
| UCSR0C &= ~(1 << USBS0); |
| |
| UCSR1B &= ~(1<<TXB81); |
| |
| UCSR1B |= (1 << RXEN1); // enable RX |
| UCSR0B |= (1 << RXEN0); // enable RX |
| UCSR1B |= (1 << TXEN1); // enable TX |
| UCSR0B |= (1 << TXEN0); // enable TX |
| |
| // ensable RX-Interrupt |
| UCSR0B |= (1 << RXCIE0); |
| UCSR1B |= (1 << RXCIE1); |
| |
| |
| TIMSK1 &= ~_BV(ICIE1); // disable other Interrupts |
| TIMSK2 &= ~(1<<OCIE2A); |
| TIMSK0 &= ~_BV(TOIE0); |
| |
| sei(); |
| |
| } |
| break; |
| |