WebSVN - Projects - Blame - Rev 19 - /IR-TX-BL/trunk/V0.01/IR-Tx_V0

Rev	Author	Line No.	Line
14	walter	1
		2	IR-Tx_V0_01.elf: file format elf32-avr
		3
		4	Sections:
		5	Idx Name Size VMA LMA File off Algn
		6
		7	CONTENTS, ALLOC, LOAD, READONLY, CODE
		8	1 .data 00000006 00800060 00000636 000006ca 2**0
		9	CONTENTS, ALLOC, LOAD, DATA
		10	2 .bss 00000016 00800066 00800066 000006d0 2**0
		11	ALLOC
		12	3 .stab 00000378 00000000 00000000 000006d0 2**2
		13	CONTENTS, READONLY, DEBUGGING
		14	4 .stabstr 00000071 00000000 00000000 00000a48 2**0
		15	CONTENTS, READONLY, DEBUGGING
		16	5 .debug_aranges 00000040 00000000 00000000 00000ab9 2**0
		17	CONTENTS, READONLY, DEBUGGING
		18	6 .debug_pubnames 000000f4 00000000 00000000 00000af9 2**0
		19	CONTENTS, READONLY, DEBUGGING
		20	7 .debug_info 00000263 00000000 00000000 00000bed 2**0
		21	CONTENTS, READONLY, DEBUGGING
		22	8 .debug_abbrev 00000148 00000000 00000000 00000e50 2**0
		23	CONTENTS, READONLY, DEBUGGING
		24	9 .debug_line 000004ec 00000000 00000000 00000f98 2**0
		25	CONTENTS, READONLY, DEBUGGING
		26	10 .debug_frame 000000b0 00000000 00000000 00001484 2**2
		27	CONTENTS, READONLY, DEBUGGING
		28	11 .debug_str 0000012f 00000000 00000000 00001534 2**0
		29	CONTENTS, READONLY, DEBUGGING
		30	12 .debug_loc 0000003c 00000000 00000000 00001663 2**0
		31	CONTENTS, READONLY, DEBUGGING
		32	Disassembly of section .text:
		33
		34	00000000 <__vectors>:
		35	0: 12 c0 rjmp .+36 ; 0x26 <__ctors_end>
		36	2: 2c c0 rjmp .+88 ; 0x5c <__bad_interrupt>
		37	4: 2b c0 rjmp .+86 ; 0x5c <__bad_interrupt>
		38	6: 2a c0 rjmp .+84 ; 0x5c <__bad_interrupt>
		39	8: 29 c0 rjmp .+82 ; 0x5c <__bad_interrupt>
		40	a: 3a c0 rjmp .+116 ; 0x80 <__vector_5>
		41	c: 27 c0 rjmp .+78 ; 0x5c <__bad_interrupt>
		42	e: 26 c0 rjmp .+76 ; 0x5c <__bad_interrupt>
		43	10: 26 c0 rjmp .+76 ; 0x5e <__vector_8>
		44	12: af c0 rjmp .+350 ; 0x172 <__vector_9>
		45	14: 23 c0 rjmp .+70 ; 0x5c <__bad_interrupt>
		46	16: 22 c0 rjmp .+68 ; 0x5c <__bad_interrupt>
		47	18: 21 c0 rjmp .+66 ; 0x5c <__bad_interrupt>
		48	1a: 20 c0 rjmp .+64 ; 0x5c <__bad_interrupt>
		49	1c: 1f c0 rjmp .+62 ; 0x5c <__bad_interrupt>
		50	1e: 1e c0 rjmp .+60 ; 0x5c <__bad_interrupt>
		51	20: 1d c0 rjmp .+58 ; 0x5c <__bad_interrupt>
		52	22: 1c c0 rjmp .+56 ; 0x5c <__bad_interrupt>
		53	24: 1b c0 rjmp .+54 ; 0x5c <__bad_interrupt>
		54
		55	00000026 <__ctors_end>:
		56	26: 11 24 eor r1, r1
		57	28: 1f be out 0x3f, r1 ; 63
		58	2a: cf e5 ldi r28, 0x5F ; 95
		59	2c: d4 e0 ldi r29, 0x04 ; 4
		60	2e: de bf out 0x3e, r29 ; 62
		61	30: cd bf out 0x3d, r28 ; 61
		62
		63	00000032 <__do_copy_data>:
		64	32: 10 e0 ldi r17, 0x00 ; 0
		65	34: a0 e6 ldi r26, 0x60 ; 96
		66	36: b0 e0 ldi r27, 0x00 ; 0
		67	38: e6 e3 ldi r30, 0x36 ; 54
		68	3a: f6 e0 ldi r31, 0x06 ; 6
		69	3c: 02 c0 rjmp .+4 ; 0x42 <.do_copy_data_start>
		70
		71	0000003e <.do_copy_data_loop>:
		72	3e: 05 90 lpm r0, Z+
		73	40: 0d 92 st X+, r0
		74
		75	00000042 <.do_copy_data_start>:
		76	42: a6 36 cpi r26, 0x66 ; 102
		77	44: b1 07 cpc r27, r17
		78	46: d9 f7 brne .-10 ; 0x3e <.do_copy_data_loop>
		79
		80	00000048 <__do_clear_bss>:
		81	48: 10 e0 ldi r17, 0x00 ; 0
		82	4a: a6 e6 ldi r26, 0x66 ; 102
		83	4c: b0 e0 ldi r27, 0x00 ; 0
		84	4e: 01 c0 rjmp .+2 ; 0x52 <.do_clear_bss_start>
		85
		86	00000050 <.do_clear_bss_loop>:
		87	50: 1d 92 st X+, r1
		88
		89	00000052 <.do_clear_bss_start>:
		90	52: ac 37 cpi r26, 0x7C ; 124
		91	54: b1 07 cpc r27, r17
		92	56: e1 f7 brne .-8 ; 0x50 <.do_clear_bss_loop>
		93	58: 11 d1 rcall .+546 ; 0x27c <main>
		94	5a: ec c2 rjmp .+1496 ; 0x634 <_exit>
		95
		96	0000005c <__bad_interrupt>:
		97	5c: d1 cf rjmp .-94 ; 0x0 <__vectors>
		98
		99	0000005e <__vector_8>:
		100	volatile unsigned char IRbit = 0;
		101
		102
		103	SIGNAL(SIG_OVERFLOW1)
		104	{
		105	5e: 1f 92 push r1
		106	60: 0f 92 push r0
		107	62: 0f b6 in r0, 0x3f ; 63
		108	64: 0f 92 push r0
		109	66: 11 24 eor r1, r1
		110	68: 8f 93 push r24
		111	TMR1OvF++;
		112	6a: 80 91 6a 00 lds r24, 0x006A
		113	6e: 8f 5f subi r24, 0xFF ; 255
		114	70: 80 93 6a 00 sts 0x006A, r24
		115	74: 8f 91 pop r24
		116	76: 0f 90 pop r0
		117	78: 0f be out 0x3f, r0 ; 63
		118	7a: 0f 90 pop r0
		119	7c: 1f 90 pop r1
		120	7e: 18 95 reti
		121
		122	00000080 <__vector_5>:
		123	}
		124
		125
		126	SIGNAL(SIG_INPUT_CAPTURE1)
		127	{
		128	80: 1f 92 push r1
		129	82: 0f 92 push r0
		130	84: 0f b6 in r0, 0x3f ; 63
		131	86: 0f 92 push r0
		132	88: 11 24 eor r1, r1
		133	8a: 2f 93 push r18
		134	8c: 3f 93 push r19
		135	8e: 4f 93 push r20
		136	90: 8f 93 push r24
		137	92: 9f 93 push r25
		138	static unsigned int pos_ICR;
		139	static unsigned int ppm;
		140
		141	if ((TCCR1B & (1<<ICES1)) != 0)
		142	94: 0e b4 in r0, 0x2e ; 46
		143	96: 06 fe sbrs r0, 6
		144	98: 0c c0 rjmp .+24 ; 0xb2 <__vector_5+0x32>
		145	{
		146	TCCR1B &= ~(1<<ICES1); //invert trigger
		147	9a: 8e b5 in r24, 0x2e ; 46
		148	9c: 8f 7b andi r24, 0xBF ; 191
		149	9e: 8e bd out 0x2e, r24 ; 46
		150	TMR1OvF = 0;
		151	a0: 10 92 6a 00 sts 0x006A, r1
		152	pos_ICR = ICR1;
		153	a4: 86 b5 in r24, 0x26 ; 38
		154	a6: 97 b5 in r25, 0x27 ; 39
		155	a8: 90 93 71 00 sts 0x0071, r25
		156	ac: 80 93 70 00 sts 0x0070, r24
		157	b0: 4c c0 rjmp .+152 ; 0x14a <__vector_5+0xca>
		158	}
		159	else //Negative Flanke
		160	{
		161	TCCR1B \|= (1<<ICES1);
		162	b2: 8e b5 in r24, 0x2e ; 46
		163	b4: 80 64 ori r24, 0x40 ; 64
		164	b6: 8e bd out 0x2e, r24 ; 46
		165	ppm = (ICR1 - pos_ICR + (int) TMR1OvF * 65536);
		166	b8: 26 b5 in r18, 0x26 ; 38
		167	ba: 37 b5 in r19, 0x27 ; 39
		168	bc: 80 91 6a 00 lds r24, 0x006A
		169	c0: 80 91 70 00 lds r24, 0x0070
		170	c4: 90 91 71 00 lds r25, 0x0071
		171	c8: 28 1b sub r18, r24
		172	ca: 39 0b sbc r19, r25
		173	cc: 30 93 6f 00 sts 0x006F, r19
		174	d0: 20 93 6e 00 sts 0x006E, r18
		175	if ((ppm > 600) && (ppm < 2400))
		176	d4: c9 01 movw r24, r18
		177	d6: 89 55 subi r24, 0x59 ; 89
		178	d8: 92 40 sbci r25, 0x02 ; 2
		179	da: 87 50 subi r24, 0x07 ; 7
		180	dc: 97 40 sbci r25, 0x07 ; 7
		181	de: a8 f5 brcc .+106 ; 0x14a <__vector_5+0xca>
		182	{
		183	if (ppm > 2100) ppm = 2100;
		184	e0: 88 e0 ldi r24, 0x08 ; 8
		185	e2: 25 33 cpi r18, 0x35 ; 53
		186	e4: 38 07 cpc r19, r24
		187	e6: 18 f0 brcs .+6 ; 0xee <__vector_5+0x6e>
		188	e8: 84 e3 ldi r24, 0x34 ; 52
		189	ea: 98 e0 ldi r25, 0x08 ; 8
		190	ec: 05 c0 rjmp .+10 ; 0xf8 <__vector_5+0x78>
		191	if (ppm < 900) ppm = 900;
		192	ee: 24 58 subi r18, 0x84 ; 132
		193	f0: 33 40 sbci r19, 0x03 ; 3
		194	f2: 30 f4 brcc .+12 ; 0x100 <__vector_5+0x80>
		195	f4: 84 e8 ldi r24, 0x84 ; 132
		196	f6: 93 e0 ldi r25, 0x03 ; 3
		197	f8: 90 93 6f 00 sts 0x006F, r25
		198	fc: 80 93 6e 00 sts 0x006E, r24
		199	ppm = (ppm_signal * 7 + ppm) / 8;
		200	100: 20 91 66 00 lds r18, 0x0066
		201	104: 30 91 67 00 lds r19, 0x0067
		202	108: c9 01 movw r24, r18
		203	10a: 43 e0 ldi r20, 0x03 ; 3
		204	10c: 88 0f add r24, r24
		205	10e: 99 1f adc r25, r25
		206	110: 4a 95 dec r20
		207	112: e1 f7 brne .-8 ; 0x10c <__vector_5+0x8c>
		208	114: 82 1b sub r24, r18
		209	116: 93 0b sbc r25, r19
		210	118: 20 91 6e 00 lds r18, 0x006E
		211	11c: 30 91 6f 00 lds r19, 0x006F
		212	120: 82 0f add r24, r18
		213	122: 93 1f adc r25, r19
		214	124: 23 e0 ldi r18, 0x03 ; 3
		215	126: 96 95 lsr r25
		216	128: 87 95 ror r24
		217	12a: 2a 95 dec r18
		218	12c: e1 f7 brne .-8 ; 0x126 <__vector_5+0xa6>
		219	12e: 90 93 6f 00 sts 0x006F, r25
		220	132: 80 93 6e 00 sts 0x006E, r24
		221	ppm_signal = ppm;
		222	136: 90 93 67 00 sts 0x0067, r25
		223	13a: 80 93 66 00 sts 0x0066, r24
		224	ppm_new = 1;
		225	13e: 81 e0 ldi r24, 0x01 ; 1
		226	140: 90 e0 ldi r25, 0x00 ; 0
		227	142: 90 93 69 00 sts 0x0069, r25
		228	146: 80 93 68 00 sts 0x0068, r24
		229	14a: 9f 91 pop r25
		230	14c: 8f 91 pop r24
		231	14e: 4f 91 pop r20
		232	150: 3f 91 pop r19
		233	152: 2f 91 pop r18
		234	154: 0f 90 pop r0
		235	156: 0f be out 0x3f, r0 ; 63
		236	158: 0f 90 pop r0
		237	15a: 1f 90 pop r1
		238	15c: 18 95 reti
		239
		240	0000015e <StartIRModulation>:
		241	}
		242
		243	}
		244
		245	}
		246
		247
		248
		249	/##############################################################################/
		250	void StartIRModulation(void)
		251	{
		252	15e: 89 e0 ldi r24, 0x09 ; 9
		253	160: 85 bd out 0x25, r24 ; 37
		254	//Timer1 Config for generation the 38Khz IR Modulation
		255	TCCR2 = (0<<FOC2)\|(0<<WGM20)\|(0<<COM21)\|(0<<COM20)\|
		256	(1<<WGM21) \|(0<<CS22) \|(0<<CS21) \|(1<<CS20);
		257
		258	OCR2 = 108; //~38Khz @ 8Mhz
		259	162: 8c e6 ldi r24, 0x6C ; 108
		260	164: 83 bd out 0x23, r24 ; 35
		261
		262	//Timer 0 Config for getting right timing for IR Pattern
		263	TCCR0 = (1<<CS02)\|(0<<CS01)\|(1<<CS00); // clk(@8MHz) / 1024 = 128us / clk (resolution)
		264	166: 85 e0 ldi r24, 0x05 ; 5
		265	168: 83 bf out 0x33, r24 ; 51
		266	TIMSK &= ~(1<<TOIE0); //
		267	16a: 89 b7 in r24, 0x39 ; 57
		268	16c: 8e 7f andi r24, 0xFE ; 254
		269	16e: 89 bf out 0x39, r24 ; 57
		270	170: 08 95 ret
		271
		272	00000172 <__vector_9>:
		273
		274	}
		275
		276
		277	SIGNAL(SIG_OVERFLOW0)
		278	{
		279	172: 1f 92 push r1
		280	174: 0f 92 push r0
		281	176: 0f b6 in r0, 0x3f ; 63
		282	178: 0f 92 push r0
		283	17a: 11 24 eor r1, r1
		284	17c: 8f 93 push r24
		285	17e: 9f 93 push r25
		286
		287	switch (IRstate)
		288	180: 90 91 6b 00 lds r25, 0x006B
		289	184: 92 30 cpi r25, 0x02 ; 2
		290	186: b1 f0 breq .+44 ; 0x1b4 <__vector_9+0x42>
		291	188: 93 30 cpi r25, 0x03 ; 3
		292	18a: 20 f4 brcc .+8 ; 0x194 <__vector_9+0x22>
		293	18c: 91 30 cpi r25, 0x01 ; 1
		294	18e: 09 f0 breq .+2 ; 0x192 <__vector_9+0x20>
		295	190: 52 c0 rjmp .+164 ; 0x236 <__vector_9+0xc4>
		296	192: 06 c0 rjmp .+12 ; 0x1a0 <__vector_9+0x2e>
		297	194: 93 30 cpi r25, 0x03 ; 3
		298	196: e9 f0 breq .+58 ; 0x1d2 <__vector_9+0x60>
		299	198: 94 30 cpi r25, 0x04 ; 4
		300	19a: 09 f0 breq .+2 ; 0x19e <__vector_9+0x2c>
		301	19c: 4c c0 rjmp .+152 ; 0x236 <__vector_9+0xc4>
		302	19e: 36 c0 rjmp .+108 ; 0x20c <__vector_9+0x9a>
		303	{
		304	case 1:
		305	TCCR2 setbit (1<<COM20);
		306	1a0: 85 b5 in r24, 0x25 ; 37
		307	1a2: 80 61 ori r24, 0x10 ; 16
		308	1a4: 85 bd out 0x25, r24 ; 37
		309	IRstate = 2;
		310	1a6: 82 e0 ldi r24, 0x02 ; 2
		311	1a8: 80 93 6b 00 sts 0x006B, r24
		312	IRbit = 0;
		313	1ac: 10 92 6d 00 sts 0x006D, r1
		314	TCNT0 = 255 - (13000 / 128);
		315	1b0: 8a e9 ldi r24, 0x9A ; 154
		316	1b2: 0b c0 rjmp .+22 ; 0x1ca <__vector_9+0x58>
		317	break;
		318	case 2:
		319	TCCR2 clrbit (1<<COM20);
		320	1b4: 85 b5 in r24, 0x25 ; 37
		321	1b6: 8f 7e andi r24, 0xEF ; 239
		322	1b8: 85 bd out 0x25, r24 ; 37
		323	IRstate = 3;
		324	1ba: 83 e0 ldi r24, 0x03 ; 3
		325	1bc: 80 93 6b 00 sts 0x006B, r24
		326	if ((IRdat & 0x40) == 0) TCNT0 = 255 - (1000 / 128);
		327	1c0: 80 91 6c 00 lds r24, 0x006C
		328	1c4: 86 fd sbrc r24, 6
		329	1c6: 03 c0 rjmp .+6 ; 0x1ce <__vector_9+0x5c>
		330	1c8: 88 ef ldi r24, 0xF8 ; 248
		331	1ca: 82 bf out 0x32, r24 ; 50
		332	1cc: 39 c0 rjmp .+114 ; 0x240 <__vector_9+0xce>
		333	else TCNT0 = 255 - (3000 / 128);
		334	1ce: 88 ee ldi r24, 0xE8 ; 232
		335	1d0: fc cf rjmp .-8 ; 0x1ca <__vector_9+0x58>
		336	break;
		337	case 3:
		338	TCCR2 setbit (1<<COM20);
		339	1d2: 85 b5 in r24, 0x25 ; 37
		340	1d4: 80 61 ori r24, 0x10 ; 16
		341	1d6: 85 bd out 0x25, r24 ; 37
		342	TCNT0 = 255 - (1000 / 128);
		343	1d8: 88 ef ldi r24, 0xF8 ; 248
		344	1da: 82 bf out 0x32, r24 ; 50
		345	IRdat = IRdat << 1;
		346	1dc: 80 91 6c 00 lds r24, 0x006C
		347	1e0: 88 0f add r24, r24
		348	1e2: 80 93 6c 00 sts 0x006C, r24
		349	IRbit++;
		350	1e6: 80 91 6d 00 lds r24, 0x006D
		351	1ea: 8f 5f subi r24, 0xFF ; 255
		352	1ec: 80 93 6d 00 sts 0x006D, r24
		353	if (IRbit < 7) IRstate = 2;
		354	1f0: 80 91 6d 00 lds r24, 0x006D
		355	1f4: 87 30 cpi r24, 0x07 ; 7
		356	1f6: 20 f4 brcc .+8 ; 0x200 <__vector_9+0x8e>
		357	1f8: 82 e0 ldi r24, 0x02 ; 2
		358	1fa: 80 93 6b 00 sts 0x006B, r24
		359	1fe: 20 c0 rjmp .+64 ; 0x240 <__vector_9+0xce>
		360	else
		361	{
		362	IRstate = 4;
		363	200: 84 e0 ldi r24, 0x04 ; 4
		364	202: 80 93 6b 00 sts 0x006B, r24
		365	IRbit = 0;
		366	206: 10 92 6d 00 sts 0x006D, r1
		367	20a: 1a c0 rjmp .+52 ; 0x240 <__vector_9+0xce>
		368	}
		369	break;
		370	case 4:
		371	TCCR2 clrbit (1<<COM20);
		372	20c: 85 b5 in r24, 0x25 ; 37
		373	20e: 8f 7e andi r24, 0xEF ; 239
		374	210: 85 bd out 0x25, r24 ; 37
		375	TCNT0 = 255 - (25000 / 128);
		376	212: 8c e3 ldi r24, 0x3C ; 60
		377	214: 82 bf out 0x32, r24 ; 50
		378	if (IRbit < 20) IRstate = 4;
		379	216: 80 91 6d 00 lds r24, 0x006D
		380	21a: 84 31 cpi r24, 0x14 ; 20
		381	21c: 18 f4 brcc .+6 ; 0x224 <__vector_9+0xb2>
		382	21e: 90 93 6b 00 sts 0x006B, r25
		383	222: 03 c0 rjmp .+6 ; 0x22a <__vector_9+0xb8>
		384	else IRstate = 5;
		385	224: 85 e0 ldi r24, 0x05 ; 5
		386	226: 80 93 6b 00 sts 0x006B, r24
		387	IRbit++;
		388	22a: 80 91 6d 00 lds r24, 0x006D
		389	22e: 8f 5f subi r24, 0xFF ; 255
		390	230: 80 93 6d 00 sts 0x006D, r24
		391	234: 05 c0 rjmp .+10 ; 0x240 <__vector_9+0xce>
		392	break;
		393	default:
		394	TIMSK &= ~(1<<TOIE0);
		395	236: 89 b7 in r24, 0x39 ; 57
		396	238: 8e 7f andi r24, 0xFE ; 254
		397	23a: 89 bf out 0x39, r24 ; 57
		398	IRstate = 0;
		399	23c: 10 92 6b 00 sts 0x006B, r1
		400	240: 9f 91 pop r25
		401	242: 8f 91 pop r24
		402	244: 0f 90 pop r0
		403	246: 0f be out 0x3f, r0 ; 63
		404	248: 0f 90 pop r0
		405	24a: 1f 90 pop r1
		406	24c: 18 95 reti
		407
		408	0000024e <SendIRSignal>:
		409	break;
		410
		411	}
		412
		413	}
		414
		415
		416
		417
		418
		419	/##############################################################################/
		420	void SendIRSignal(unsigned char txbyte)
		421	{
		422	24e: 98 2f mov r25, r24
		423	while (IRstate != 0) {} //IR already in action ?, if so, wait
		424	250: 80 91 6b 00 lds r24, 0x006B
		425	254: 88 23 and r24, r24
		426	256: e1 f7 brne .-8 ; 0x250 <SendIRSignal+0x2>
		427	IRstate = 1; //initial State
		428	258: 81 e0 ldi r24, 0x01 ; 1
		429	25a: 80 93 6b 00 sts 0x006B, r24
		430	IRdat = txbyte; //copy IR Data
		431	25e: 90 93 6c 00 sts 0x006C, r25
		432	TIFR &= TOV0; //set TMR0 Int Flag
		433	262: 88 b7 in r24, 0x38 ; 56
		434	264: 18 be out 0x38, r1 ; 56
		435	TIMSK setbit (1<<TOIE0); //Enable TMR0 Int
		436	266: 89 b7 in r24, 0x39 ; 57
		437	268: 81 60 ori r24, 0x01 ; 1
		438	26a: 89 bf out 0x39, r24 ; 57
		439	26c: 08 95 ret
		440
		441	0000026e <StartPPM>:
		442	}
		443
		444
		445
		446
		447
		448
		449
		450	/##############################################################################/
		451	void StartPPM(void)
		452	{
		453	26e: 1f bc out 0x2f, r1 ; 47
		454
		455	//global timer1 Config
		456	TCCR1A = (0<<COM1A1)\|(0<<COM1A0)\|(0<<COM1B1)\|(0<<COM1B0)\|
		457	(0<<FOC1A) \|(0<<FOC1B) \|(0<<WGM10) \|(0<<WGM11);
		458	TCCR1B = (1<<ICNC1)\|(1<<ICES1)\|(0<<WGM13)\|
		459	270: 82 ec ldi r24, 0xC2 ; 194
		460	272: 8e bd out 0x2e, r24 ; 46
		461	(0<<WGM12)\|(0<<CS12)\|(1<<CS11)\|(0<<CS10); //ICP_POS_FLANKE
		462
		463	// interrupts
		464	TIMSK \|= (1<<TICIE1)\|(1<<TOIE1); //ICP_INT_ENABLE and TIMER1_INT_ENABLE
		465	274: 89 b7 in r24, 0x39 ; 57
		466	276: 84 62 ori r24, 0x24 ; 36
		467	278: 89 bf out 0x39, r24 ; 57
		468	27a: 08 95 ret
		469
		470	0000027c <main>:
		471
		472	}
		473
		474
		475
		476
		477	/##############################################################################/
		478	// MAIN
		479	/##############################################################################/
		480	int main (void)
		481	{
		482	27c: 88 e0 ldi r24, 0x08 ; 8
		483	27e: 84 bb out 0x14, r24 ; 20
		484
		485	DDRC = (1<<ledred);
		486	PORTC = 0x00;
		487	280: 15 ba out 0x15, r1 ; 21
		488	DDRD = (1<<ledgreen);
		489	282: 80 e8 ldi r24, 0x80 ; 128
		490	284: 81 bb out 0x11, r24 ; 17
		491	PORTD = 0x00;
		492	286: 12 ba out 0x12, r1 ; 18
		493	DDRB = (1<<1)\|(1<<2)\|(1<<3);
		494	288: 8e e0 ldi r24, 0x0E ; 14
		495	28a: 87 bb out 0x17, r24 ; 23
		496	PORTB = 0x00;
		497	28c: 18 ba out 0x18, r1 ; 24
		498
		499
		500	StartUART();
		501	28e: 44 d0 rcall .+136 ; 0x318 <StartUART>
		502	290: 1f bc out 0x2f, r1 ; 47
		503	292: 82 ec ldi r24, 0xC2 ; 194
		504	294: 8e bd out 0x2e, r24 ; 46
		505	296: 89 b7 in r24, 0x39 ; 57
		506	298: 84 62 ori r24, 0x24 ; 36
		507	29a: 89 bf out 0x39, r24 ; 57
		508	StartPPM();
		509	StartIRModulation();
		510	29c: 60 df rcall .-320 ; 0x15e <StartIRModulation>
		511	sei();
		512	29e: 78 94 sei
		513
		514
		515	while (1)
		516	{
		517	//printf("%d ",ppm_signal);
		518	if (ppm_new == 1)
		519	2a0: 80 91 68 00 lds r24, 0x0068
		520	2a4: 90 91 69 00 lds r25, 0x0069
		521	2a8: 01 97 sbiw r24, 0x01 ; 1
		522	2aa: d1 f7 brne .-12 ; 0x2a0 <main+0x24>
		523	{
		524	ppm_new = 0;
		525	2ac: 10 92 69 00 sts 0x0069, r1
		526	2b0: 10 92 68 00 sts 0x0068, r1
		527	if (ppm_signal > 1750)
		528	2b4: 80 91 66 00 lds r24, 0x0066
		529	2b8: 90 91 67 00 lds r25, 0x0067
		530	2bc: 87 5d subi r24, 0xD7 ; 215
		531	2be: 96 40 sbci r25, 0x06 ; 6
		532	2c0: 58 f0 brcs .+22 ; 0x2d8 <main+0x5c>
		533	{
		534	SendIRSignal(ZOOM);
		535	2c2: 81 e4 ldi r24, 0x41 ; 65
		536	2c4: c4 df rcall .-120 ; 0x24e <SendIRSignal>
		537	PORTC \|= (1<<ledred);
		538	2c6: ab 9a sbi 0x15, 3 ; 21
		539	while (ppm_signal > 1650) {}
		540	2c8: 80 91 66 00 lds r24, 0x0066
		541	2cc: 90 91 67 00 lds r25, 0x0067
		542	2d0: 83 57 subi r24, 0x73 ; 115
		543	2d2: 96 40 sbci r25, 0x06 ; 6
		544	2d4: c8 f7 brcc .-14 ; 0x2c8 <main+0x4c>
		545	PORTC &= ~(1<<ledred);
		546	2d6: ab 98 cbi 0x15, 3 ; 21
		547	}
		548
		549	if (ppm_signal < 1250)
		550	2d8: 80 91 66 00 lds r24, 0x0066
		551	2dc: 90 91 67 00 lds r25, 0x0067
		552	2e0: 82 5e subi r24, 0xE2 ; 226
		553	2e2: 94 40 sbci r25, 0x04 ; 4
		554	2e4: e8 f6 brcc .-70 ; 0x2a0 <main+0x24>
		555	{
		556	PORTD \|= (1<<ledgreen);
		557	2e6: 97 9a sbi 0x12, 7 ; 18
		558	SendIRSignal(TRIGGER);
		559	2e8: 80 e4 ldi r24, 0x40 ; 64
		560	2ea: b1 df rcall .-158 ; 0x24e <SendIRSignal>
		561	while (ppm_signal < 1350) {}
		562	2ec: 80 91 66 00 lds r24, 0x0066
		563	2f0: 90 91 67 00 lds r25, 0x0067
		564	2f4: 86 54 subi r24, 0x46 ; 70
		565	2f6: 95 40 sbci r25, 0x05 ; 5
		566	2f8: c8 f3 brcs .-14 ; 0x2ec <main+0x70>
		567	PORTD &= ~(1<<ledgreen);
		568	2fa: 97 98 cbi 0x12, 7 ; 18
		569	2fc: d1 cf rjmp .-94 ; 0x2a0 <main+0x24>
		570
		571	000002fe <uart_putchar>:
		572
		573	}
		574
		575	int uart_putchar (char c)
		576	{
		577	2fe: 1f 93 push r17
		578	300: 18 2f mov r17, r24
		579	if (c == '\n') uart_putchar('\r');
		580	302: 8a 30 cpi r24, 0x0A ; 10
		581	304: 11 f4 brne .+4 ; 0x30a <uart_putchar+0xc>
		582	306: 8d e0 ldi r24, 0x0D ; 13
		583	308: fa df rcall .-12 ; 0x2fe <uart_putchar>
		584	loop_until_bit_is_set(UCSRA, UDRE);
		585	30a: 5d 9b sbis 0x0b, 5 ; 11
		586	30c: fe cf rjmp .-4 ; 0x30a <uart_putchar+0xc>
		587	UDR = c;
		588	30e: 1c b9 out 0x0c, r17 ; 12
		589
		590	return (0);
		591	}
		592	310: 80 e0 ldi r24, 0x00 ; 0
		593	312: 90 e0 ldi r25, 0x00 ; 0
		594	314: 1f 91 pop r17
		595	316: 08 95 ret
		596
		597	00000318 <StartUART>:
		598	318: 59 9a sbi 0x0b, 1 ; 11
		599	31a: 88 e1 ldi r24, 0x18 ; 24
		600	31c: 8a b9 out 0x0a, r24 ; 10
		601	31e: 86 e8 ldi r24, 0x86 ; 134
		602	320: 80 bd out 0x20, r24 ; 32
		603	322: 89 e1 ldi r24, 0x19 ; 25
		604	324: 89 b9 out 0x09, r24 ; 9
		605	326: 60 e0 ldi r22, 0x00 ; 0
		606	328: 70 e0 ldi r23, 0x00 ; 0
		607	32a: 8f e7 ldi r24, 0x7F ; 127
		608	32c: 91 e0 ldi r25, 0x01 ; 1
		609	32e: 01 d0 rcall .+2 ; 0x332 <fdevopen>
		610	330: 08 95 ret
		611
		612	00000332 <fdevopen>:
		613	332: ef 92 push r14
		614	334: ff 92 push r15
		615	336: 0f 93 push r16
		616	338: 1f 93 push r17
		617	33a: cf 93 push r28
		618	33c: df 93 push r29
		619	33e: 8c 01 movw r16, r24
		620	340: 7b 01 movw r14, r22
		621	342: 89 2b or r24, r25
		622	344: 11 f4 brne .+4 ; 0x34a <fdevopen+0x18>
		623	346: 67 2b or r22, r23
		624	348: c9 f1 breq .+114 ; 0x3bc <fdevopen+0x8a>
		625	34a: 6e e0 ldi r22, 0x0E ; 14
		626	34c: 70 e0 ldi r23, 0x00 ; 0
		627	34e: 81 e0 ldi r24, 0x01 ; 1
		628	350: 90 e0 ldi r25, 0x00 ; 0
		629	352: 3b d0 rcall .+118 ; 0x3ca <calloc>
		630	354: fc 01 movw r30, r24
		631	356: 00 97 sbiw r24, 0x00 ; 0
		632	358: 89 f1 breq .+98 ; 0x3bc <fdevopen+0x8a>
		633	35a: dc 01 movw r26, r24
		634	35c: 80 e8 ldi r24, 0x80 ; 128
		635	35e: 83 83 std Z+3, r24 ; 0x03
		636	360: e1 14 cp r14, r1
		637	362: f1 04 cpc r15, r1
		638	364: 71 f0 breq .+28 ; 0x382 <fdevopen+0x50>
		639	366: f3 86 std Z+11, r15 ; 0x0b
		640	368: e2 86 std Z+10, r14 ; 0x0a
		641	36a: 81 e8 ldi r24, 0x81 ; 129
		642	36c: 83 83 std Z+3, r24 ; 0x03
		643	36e: 80 91 72 00 lds r24, 0x0072
		644	372: 90 91 73 00 lds r25, 0x0073
		645	376: 89 2b or r24, r25
		646	378: 21 f4 brne .+8 ; 0x382 <fdevopen+0x50>
		647	37a: f0 93 73 00 sts 0x0073, r31
		648	37e: e0 93 72 00 sts 0x0072, r30
		649	382: 01 15 cp r16, r1
		650	384: 11 05 cpc r17, r1
		651	386: e1 f0 breq .+56 ; 0x3c0 <fdevopen+0x8e>
		652	388: 11 87 std Z+9, r17 ; 0x09
		653	38a: 00 87 std Z+8, r16 ; 0x08
		654	38c: 83 81 ldd r24, Z+3 ; 0x03
		655	38e: 82 60 ori r24, 0x02 ; 2
		656	390: 83 83 std Z+3, r24 ; 0x03
		657	392: 80 91 74 00 lds r24, 0x0074
		658	396: 90 91 75 00 lds r25, 0x0075
		659	39a: 89 2b or r24, r25
		660	39c: 89 f4 brne .+34 ; 0x3c0 <fdevopen+0x8e>
		661	39e: f0 93 75 00 sts 0x0075, r31
		662	3a2: e0 93 74 00 sts 0x0074, r30
		663	3a6: 80 91 76 00 lds r24, 0x0076
		664	3aa: 90 91 77 00 lds r25, 0x0077
		665	3ae: 89 2b or r24, r25
		666	3b0: 39 f4 brne .+14 ; 0x3c0 <fdevopen+0x8e>
		667	3b2: f0 93 77 00 sts 0x0077, r31
		668	3b6: e0 93 76 00 sts 0x0076, r30
		669	3ba: 02 c0 rjmp .+4 ; 0x3c0 <fdevopen+0x8e>
		670	3bc: a0 e0 ldi r26, 0x00 ; 0
		671	3be: b0 e0 ldi r27, 0x00 ; 0
		672	3c0: cd 01 movw r24, r26
		673	3c2: e6 e0 ldi r30, 0x06 ; 6
		674	3c4: cd b7 in r28, 0x3d ; 61
		675	3c6: de b7 in r29, 0x3e ; 62
		676	3c8: 26 c1 rjmp .+588 ; 0x616 <__epilogue_restores__+0x18>
		677
		678	000003ca <calloc>:
		679	3ca: 0f 93 push r16
		680	3cc: 1f 93 push r17
		681	3ce: cf 93 push r28
		682	3d0: df 93 push r29
		683	3d2: 86 9f mul r24, r22
		684	3d4: 80 01 movw r16, r0
		685	3d6: 87 9f mul r24, r23
		686	3d8: 10 0d add r17, r0
		687	3da: 96 9f mul r25, r22
		688	3dc: 10 0d add r17, r0
		689	3de: 11 24 eor r1, r1
		690	3e0: c8 01 movw r24, r16
		691	3e2: 0d d0 rcall .+26 ; 0x3fe <malloc>
		692	3e4: ec 01 movw r28, r24
		693	3e6: 00 97 sbiw r24, 0x00 ; 0
		694	3e8: 21 f0 breq .+8 ; 0x3f2 <calloc+0x28>
		695	3ea: a8 01 movw r20, r16
		696	3ec: 60 e0 ldi r22, 0x00 ; 0
		697	3ee: 70 e0 ldi r23, 0x00 ; 0
		698	3f0: ff d0 rcall .+510 ; 0x5f0 <memset>
		699	3f2: ce 01 movw r24, r28
		700	3f4: df 91 pop r29
		701	3f6: cf 91 pop r28
		702	3f8: 1f 91 pop r17
		703	3fa: 0f 91 pop r16
		704	3fc: 08 95 ret
		705
		706	000003fe <malloc>:
		707	3fe: cf 93 push r28
		708	400: df 93 push r29
		709	402: ac 01 movw r20, r24
		710	404: 02 97 sbiw r24, 0x02 ; 2
		711	406: 10 f4 brcc .+4 ; 0x40c <malloc+0xe>
		712	408: 42 e0 ldi r20, 0x02 ; 2
		713	40a: 50 e0 ldi r21, 0x00 ; 0
		714	40c: a0 91 7a 00 lds r26, 0x007A
		715	410: b0 91 7b 00 lds r27, 0x007B
		716	414: fd 01 movw r30, r26
		717	416: c0 e0 ldi r28, 0x00 ; 0
		718	418: d0 e0 ldi r29, 0x00 ; 0
		719	41a: 20 e0 ldi r18, 0x00 ; 0
		720	41c: 30 e0 ldi r19, 0x00 ; 0
		721	41e: 20 c0 rjmp .+64 ; 0x460 <__stack+0x1>
		722	420: 80 81 ld r24, Z
		723	422: 91 81 ldd r25, Z+1 ; 0x01
		724	424: 84 17 cp r24, r20
		725	426: 95 07 cpc r25, r21
		726	428: 69 f4 brne .+26 ; 0x444 <malloc+0x46>
		727	42a: 82 81 ldd r24, Z+2 ; 0x02
		728	42c: 93 81 ldd r25, Z+3 ; 0x03
		729	42e: 20 97 sbiw r28, 0x00 ; 0
		730	430: 19 f0 breq .+6 ; 0x438 <malloc+0x3a>
		731	432: 9b 83 std Y+3, r25 ; 0x03
		732	434: 8a 83 std Y+2, r24 ; 0x02
		733	436: 04 c0 rjmp .+8 ; 0x440 <malloc+0x42>
		734	438: 90 93 7b 00 sts 0x007B, r25
		735	43c: 80 93 7a 00 sts 0x007A, r24
		736	440: cf 01 movw r24, r30
		737	442: 32 c0 rjmp .+100 ; 0x4a8 <__stack+0x49>
		738	444: 48 17 cp r20, r24
		739	446: 59 07 cpc r21, r25
		740	448: 38 f4 brcc .+14 ; 0x458 <malloc+0x5a>
		741	44a: 21 15 cp r18, r1
		742	44c: 31 05 cpc r19, r1
		743	44e: 19 f0 breq .+6 ; 0x456 <malloc+0x58>
		744	450: 82 17 cp r24, r18
		745	452: 93 07 cpc r25, r19
		746	454: 08 f4 brcc .+2 ; 0x458 <malloc+0x5a>
		747	456: 9c 01 movw r18, r24
		748	458: ef 01 movw r28, r30
		749	45a: 02 80 ldd r0, Z+2 ; 0x02
		750	45c: f3 81 ldd r31, Z+3 ; 0x03
		751	45e: e0 2d mov r30, r0
		752	460: 30 97 sbiw r30, 0x00 ; 0
		753	462: f1 f6 brne .-68 ; 0x420 <malloc+0x22>
		754	464: 21 15 cp r18, r1
		755	466: 31 05 cpc r19, r1
		756	468: 89 f1 breq .+98 ; 0x4cc <__stack+0x6d>
		757	46a: c9 01 movw r24, r18
		758	46c: 84 1b sub r24, r20
		759	46e: 95 0b sbc r25, r21
		760	470: 04 97 sbiw r24, 0x04 ; 4
		761	472: 08 f4 brcc .+2 ; 0x476 <__stack+0x17>
		762	474: a9 01 movw r20, r18
		763	476: e0 e0 ldi r30, 0x00 ; 0
		764	478: f0 e0 ldi r31, 0x00 ; 0
		765	47a: 26 c0 rjmp .+76 ; 0x4c8 <__stack+0x69>
		766	47c: 8d 91 ld r24, X+
		767	47e: 9c 91 ld r25, X
		768	480: 11 97 sbiw r26, 0x01 ; 1
		769	482: 82 17 cp r24, r18
		770	484: 93 07 cpc r25, r19
		771	486: e9 f4 brne .+58 ; 0x4c2 <__stack+0x63>
		772	488: 48 17 cp r20, r24
		773	48a: 59 07 cpc r21, r25
		774	48c: 79 f4 brne .+30 ; 0x4ac <__stack+0x4d>
		775	48e: ed 01 movw r28, r26
		776	490: 8a 81 ldd r24, Y+2 ; 0x02
		777	492: 9b 81 ldd r25, Y+3 ; 0x03
		778	494: 30 97 sbiw r30, 0x00 ; 0
		779	496: 19 f0 breq .+6 ; 0x49e <__stack+0x3f>
		780	498: 93 83 std Z+3, r25 ; 0x03
		781	49a: 82 83 std Z+2, r24 ; 0x02
		782	49c: 04 c0 rjmp .+8 ; 0x4a6 <__stack+0x47>
		783	49e: 90 93 7b 00 sts 0x007B, r25
		784	4a2: 80 93 7a 00 sts 0x007A, r24
		785	4a6: cd 01 movw r24, r26
		786	4a8: 02 96 adiw r24, 0x02 ; 2
		787	4aa: 49 c0 rjmp .+146 ; 0x53e <__stack+0xdf>
		788	4ac: 84 1b sub r24, r20
		789	4ae: 95 0b sbc r25, r21
		790	4b0: fd 01 movw r30, r26
		791	4b2: e8 0f add r30, r24
		792	4b4: f9 1f adc r31, r25
		793	4b6: 41 93 st Z+, r20
		794	4b8: 51 93 st Z+, r21
		795	4ba: 02 97 sbiw r24, 0x02 ; 2
		796	4bc: 8d 93 st X+, r24
		797	4be: 9c 93 st X, r25
		798	4c0: 3a c0 rjmp .+116 ; 0x536 <__stack+0xd7>
		799	4c2: fd 01 movw r30, r26
		800	4c4: a2 81 ldd r26, Z+2 ; 0x02
		801	4c6: b3 81 ldd r27, Z+3 ; 0x03
		802	4c8: 10 97 sbiw r26, 0x00 ; 0
		803	4ca: c1 f6 brne .-80 ; 0x47c <__stack+0x1d>
		804	4cc: 80 91 78 00 lds r24, 0x0078
		805	4d0: 90 91 79 00 lds r25, 0x0079
		806	4d4: 89 2b or r24, r25
		807	4d6: 41 f4 brne .+16 ; 0x4e8 <__stack+0x89>
		808	4d8: 80 91 62 00 lds r24, 0x0062
		809	4dc: 90 91 63 00 lds r25, 0x0063
		810	4e0: 90 93 79 00 sts 0x0079, r25
		811	4e4: 80 93 78 00 sts 0x0078, r24
		812	4e8: 20 91 64 00 lds r18, 0x0064
		813	4ec: 30 91 65 00 lds r19, 0x0065
		814	4f0: 21 15 cp r18, r1
		815	4f2: 31 05 cpc r19, r1
		816	4f4: 41 f4 brne .+16 ; 0x506 <__stack+0xa7>
		817	4f6: 2d b7 in r18, 0x3d ; 61
		818	4f8: 3e b7 in r19, 0x3e ; 62
		819	4fa: 80 91 60 00 lds r24, 0x0060
		820	4fe: 90 91 61 00 lds r25, 0x0061
		821	502: 28 1b sub r18, r24
		822	504: 39 0b sbc r19, r25
		823	506: e0 91 78 00 lds r30, 0x0078
		824	50a: f0 91 79 00 lds r31, 0x0079
		825	50e: 2e 1b sub r18, r30
		826	510: 3f 0b sbc r19, r31
		827	512: 24 17 cp r18, r20
		828	514: 35 07 cpc r19, r21
		829	516: 88 f0 brcs .+34 ; 0x53a <__stack+0xdb>
		830	518: ca 01 movw r24, r20
		831	51a: 02 96 adiw r24, 0x02 ; 2
		832	51c: 28 17 cp r18, r24
		833	51e: 39 07 cpc r19, r25
		834	520: 60 f0 brcs .+24 ; 0x53a <__stack+0xdb>
		835	522: cf 01 movw r24, r30
		836	524: 84 0f add r24, r20
		837	526: 95 1f adc r25, r21
		838	528: 02 96 adiw r24, 0x02 ; 2
		839	52a: 90 93 79 00 sts 0x0079, r25
		840	52e: 80 93 78 00 sts 0x0078, r24
		841	532: 41 93 st Z+, r20
		842	534: 51 93 st Z+, r21
		843	536: cf 01 movw r24, r30
		844	538: 02 c0 rjmp .+4 ; 0x53e <__stack+0xdf>
		845	53a: 80 e0 ldi r24, 0x00 ; 0
		846	53c: 90 e0 ldi r25, 0x00 ; 0
		847	53e: df 91 pop r29
		848	540: cf 91 pop r28
		849	542: 08 95 ret
		850
		851	00000544 <free>:
		852	544: cf 93 push r28
		853	546: df 93 push r29
		854	548: 00 97 sbiw r24, 0x00 ; 0
		855	54a: 09 f4 brne .+2 ; 0x54e <free+0xa>
		856	54c: 4e c0 rjmp .+156 ; 0x5ea <free+0xa6>
		857	54e: ec 01 movw r28, r24
		858	550: 22 97 sbiw r28, 0x02 ; 2
		859	552: 1b 82 std Y+3, r1 ; 0x03
		860	554: 1a 82 std Y+2, r1 ; 0x02
		861	556: a0 91 7a 00 lds r26, 0x007A
		862	55a: b0 91 7b 00 lds r27, 0x007B
		863	55e: 10 97 sbiw r26, 0x00 ; 0
		864	560: 11 f1 breq .+68 ; 0x5a6 <free+0x62>
		865	562: 40 e0 ldi r20, 0x00 ; 0
		866	564: 50 e0 ldi r21, 0x00 ; 0
		867	566: 01 c0 rjmp .+2 ; 0x56a <free+0x26>
		868	568: dc 01 movw r26, r24
		869	56a: ac 17 cp r26, r28
		870	56c: bd 07 cpc r27, r29
		871	56e: 00 f1 brcs .+64 ; 0x5b0 <free+0x6c>
		872	570: bb 83 std Y+3, r27 ; 0x03
		873	572: aa 83 std Y+2, r26 ; 0x02
		874	574: fe 01 movw r30, r28
		875	576: 21 91 ld r18, Z+
		876	578: 31 91 ld r19, Z+
		877	57a: e2 0f add r30, r18
		878	57c: f3 1f adc r31, r19
		879	57e: ea 17 cp r30, r26
		880	580: fb 07 cpc r31, r27
		881	582: 71 f4 brne .+28 ; 0x5a0 <free+0x5c>
		882	584: 2e 5f subi r18, 0xFE ; 254
		883	586: 3f 4f sbci r19, 0xFF ; 255
		884	588: 8d 91 ld r24, X+
		885	58a: 9c 91 ld r25, X
		886	58c: 11 97 sbiw r26, 0x01 ; 1
		887	58e: 82 0f add r24, r18
		888	590: 93 1f adc r25, r19
		889	592: 99 83 std Y+1, r25 ; 0x01
		890	594: 88 83 st Y, r24
		891	596: fd 01 movw r30, r26
		892	598: 82 81 ldd r24, Z+2 ; 0x02
		893	59a: 93 81 ldd r25, Z+3 ; 0x03
		894	59c: 9b 83 std Y+3, r25 ; 0x03
		895	59e: 8a 83 std Y+2, r24 ; 0x02
		896	5a0: 41 15 cp r20, r1
		897	5a2: 51 05 cpc r21, r1
		898	5a4: 59 f4 brne .+22 ; 0x5bc <free+0x78>
		899	5a6: d0 93 7b 00 sts 0x007B, r29
		900	5aa: c0 93 7a 00 sts 0x007A, r28
		901	5ae: 1d c0 rjmp .+58 ; 0x5ea <free+0xa6>
		902	5b0: fd 01 movw r30, r26
		903	5b2: 82 81 ldd r24, Z+2 ; 0x02
		904	5b4: 93 81 ldd r25, Z+3 ; 0x03
		905	5b6: ad 01 movw r20, r26
		906	5b8: 00 97 sbiw r24, 0x00 ; 0
		907	5ba: b1 f6 brne .-84 ; 0x568 <free+0x24>
		908	5bc: fa 01 movw r30, r20
		909	5be: d3 83 std Z+3, r29 ; 0x03
		910	5c0: c2 83 std Z+2, r28 ; 0x02
		911	5c2: 21 91 ld r18, Z+
		912	5c4: 31 91 ld r19, Z+
		913	5c6: e2 0f add r30, r18
		914	5c8: f3 1f adc r31, r19
		915	5ca: ec 17 cp r30, r28
		916	5cc: fd 07 cpc r31, r29
		917	5ce: 69 f4 brne .+26 ; 0x5ea <free+0xa6>
		918	5d0: 2e 5f subi r18, 0xFE ; 254
		919	5d2: 3f 4f sbci r19, 0xFF ; 255
		920	5d4: 88 81 ld r24, Y
		921	5d6: 99 81 ldd r25, Y+1 ; 0x01
		922	5d8: 82 0f add r24, r18
		923	5da: 93 1f adc r25, r19
		924	5dc: fa 01 movw r30, r20
		925	5de: 91 83 std Z+1, r25 ; 0x01
		926	5e0: 80 83 st Z, r24
		927	5e2: 8a 81 ldd r24, Y+2 ; 0x02
		928	5e4: 9b 81 ldd r25, Y+3 ; 0x03
		929	5e6: 93 83 std Z+3, r25 ; 0x03
		930	5e8: 82 83 std Z+2, r24 ; 0x02
		931	5ea: df 91 pop r29
		932	5ec: cf 91 pop r28
		933	5ee: 08 95 ret
		934
		935	000005f0 <memset>:
		936	5f0: dc 01 movw r26, r24
		937	5f2: 01 c0 rjmp .+2 ; 0x5f6 <memset+0x6>
		938	5f4: 6d 93 st X+, r22
		939	5f6: 41 50 subi r20, 0x01 ; 1
		940	5f8: 50 40 sbci r21, 0x00 ; 0
		941	5fa: e0 f7 brcc .-8 ; 0x5f4 <memset+0x4>
		942	5fc: 08 95 ret
		943
		944	000005fe <__epilogue_restores__>:
		945	5fe: 2a 88 ldd r2, Y+18 ; 0x12
		946	600: 39 88 ldd r3, Y+17 ; 0x11
		947	602: 48 88 ldd r4, Y+16 ; 0x10
		948	604: 5f 84 ldd r5, Y+15 ; 0x0f
		949	606: 6e 84 ldd r6, Y+14 ; 0x0e
		950	608: 7d 84 ldd r7, Y+13 ; 0x0d
		951	60a: 8c 84 ldd r8, Y+12 ; 0x0c
		952	60c: 9b 84 ldd r9, Y+11 ; 0x0b
		953	60e: aa 84 ldd r10, Y+10 ; 0x0a
		954	610: b9 84 ldd r11, Y+9 ; 0x09
		955	612: c8 84 ldd r12, Y+8 ; 0x08
		956	614: df 80 ldd r13, Y+7 ; 0x07
		957	616: ee 80 ldd r14, Y+6 ; 0x06
		958	618: fd 80 ldd r15, Y+5 ; 0x05
		959	61a: 0c 81 ldd r16, Y+4 ; 0x04
		960	61c: 1b 81 ldd r17, Y+3 ; 0x03
		961	61e: aa 81 ldd r26, Y+2 ; 0x02
		962	620: b9 81 ldd r27, Y+1 ; 0x01
		963	622: ce 0f add r28, r30
		964	624: d1 1d adc r29, r1
		965	626: 0f b6 in r0, 0x3f ; 63
		966	628: f8 94 cli
		967	62a: de bf out 0x3e, r29 ; 62
		968	62c: 0f be out 0x3f, r0 ; 63
		969	62e: cd bf out 0x3d, r28 ; 61
		970	630: ed 01 movw r28, r26
		971	632: 08 95 ret
		972
		973	00000634 <_exit>:
		974	634: ff cf rjmp .-2 ; 0x634 <_exit>

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(root)/IR-TX-BL/trunk/V0.01/IR-Tx_V0_01.lss - Rev 19