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273 killagreg 1
 
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#include <stdlib.h>
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include "analog.h"
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volatile uint16_t Adc0, Adc1, Adc2, Adc3, Adc4, Adc5, Adc6, Adc7;
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volatile uint8_t ADReady = 1;
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/*****************************************************/
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/*     Initialize Analog Digital Converter           */
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/*****************************************************/
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void ADC_Init(void)
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{
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        uint8_t sreg = SREG;
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        // disable all interrupts before reconfiguration
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        cli();
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        //ADC0 ... ADC7 is connected to PortA pin 0 ... 7
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        DDRA = 0x00;
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        PORTA = 0x00;
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        // Digital Input Disable Register 0
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        // Disable digital input buffer for analog adc_channel pins
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        DIDR0 = 0xFF;
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        // external reference AREF, adjust data to the right
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    ADMUX &= ~((1 << REFS1)|(1 << REFS0)|(1 << ADLAR));
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    // set muxer to ADC adc_channel 0 (0 to 7 is a valid choice)
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    ADMUX = (ADMUX & 0xE0) | 0x00;
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    //Set ADC Control and Status Register A
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    //Auto Trigger Enable, Prescaler Select Bits to Division Factor 128, i.e. ADC clock = SYSCKL/128 = 156.25 kHz
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        ADCSRA = (0<<ADEN)|(0<<ADSC)|(0<<ADATE)|(1<<ADPS2)|(1<<ADPS1)|(1<<ADPS0)|(0<<ADIE);
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        //Set ADC Control and Status Register B
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        //Trigger Source to Free Running Mode
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        ADCSRB &= ~((1 << ADTS2)|(1 << ADTS1)|(1 << ADTS0));
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        // Start AD conversion
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        ADC_Enable();
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    // restore global interrupt flags
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    SREG = sreg;
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}
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/*****************************************************/
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/*     Interrupt Service Routine for ADC             */
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/*****************************************************/
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// runs at 312.5 kHz or 3.2 Ás
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// if after (60.8Ás) all 19 states are processed the interrupt is disabled
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// and the update of further ads is stopped
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#define ADC0    0
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#define ADC1    1
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#define ADC2    2
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#define ADC3    3
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#define ADC4    4
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#define ADC5    5
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#define ADC6    6
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#define ADC7    7
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ISR(ADC_vect)
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{
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    static uint8_t ad_channel = ADC0, state = 0;
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    // state machine
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        switch(state++)
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        {
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                case 0:
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                        Adc0 = ADC;
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                        ad_channel = ADC1;
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                        break;
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                case 1:
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                        Adc1 = ADC;
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                        ad_channel = ADC2;
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                        break;
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                case 2:
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                        Adc2 = ADC;
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                        ad_channel = ADC3;
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                        break;
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                case 3:
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                        Adc3 = ADC;
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                        ad_channel = ADC4;
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            break;
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                case 4:
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                        Adc4 = ADC;
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                        ad_channel = ADC5;
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                        break;
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                case 5:
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                        Adc5 = ADC;
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                        ad_channel = ADC6;
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                        break;
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                case 6:
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                        Adc6 = ADC;
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                        ad_channel = ADC7;
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                        break;
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                case 7:
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                        Adc7 = ADC;
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                        ad_channel = ADC0;
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                        state = 0;
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                        ADReady = 1;
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            break;
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                default:
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                        ad_channel = ADC0;
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                        state = 0;
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                        ADReady = 1;
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                        break;
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        }
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    // set adc muxer to next ad_channel
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    ADMUX = (ADMUX & 0xE0) | ad_channel;
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    // after full cycle stop further interrupts
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    if(state != 0) ADC_Enable();
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}