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/****************************************************************************
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 *   Copyright (C) 2009 by Claas Anders "CaScAdE" Rathje                    *
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 *   admiralcascade@gmail.com                                               *
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 *   Project-URL: http://www.mylifesucks.de/oss/c-osd/                      *
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 *                                                                          *
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 *   This program is free software; you can redistribute it and/or modify   *
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 *   it under the terms of the GNU General Public License as published by   *
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 *   the Free Software Foundation; either version 2 of the License.         *
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 *                                                                          *
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 *   This program is distributed in the hope that it will be useful,        *
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 *   but WITHOUT ANY WARRANTY; without even the implied warranty of         *
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 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the          *
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 *   GNU General Public License for more details.                           *
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 *                                                                          *
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 *   You should have received a copy of the GNU General Public License      *
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 *   along with this program; if not, write to the                          *
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 *   Free Software Foundation, Inc.,                                        *
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 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.              *
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 ****************************************************************************/
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#include <avr/io.h>
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#include <avr/interrupt.h>
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#include "spi.h"
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#include "main.h"
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volatile uint16_t icnt = 0;
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volatile unsigned char * iptr;
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volatile unsigned char spi_cmd_buffer[8];
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volatile uint8_t spi_ready = 1;
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int16_t ampere = 0, max_ampere = 0;
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int32_t ampere_wasted = 0;
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#define INT0_HIGH                       PORTD |=  (1 << PD2);
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#define INT0_LOW                        PORTD &= ~(1 << PD2);
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/**
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 * init the SPI as master
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 */
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void SpiMasterInit(void) {
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    volatile char IOReg;
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    // set PB4(/SS), PB5(MOSI), PB7(SCK) as output
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    DDRB = (1 << PB4) | (1 << PB5) | (1 << PB7);
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    PORTB |= (1 << PB4); // pullup SS
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    // enable SPI Interrupt and SPI in Master Mode with SCK = CK/128
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    SPCR = (1 << SPIE) | (1 << SPE) | (1 << MSTR) | (1 << SPR0) | (1 << SPR1);
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    IOReg = SPSR; // clear SPIF bit in SPSR
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    IOReg = SPDR;
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    //sei(); // we do it later
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}
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/**
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 * SPI interrupt handler
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 */
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ISR(SPI_STC_vect) {
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    *iptr++ = SPDR; // safe received byte to buffer
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    icnt--; // dec length
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    if (icnt) {
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        //SPDR = *iptr; // send next byte
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        spi_ready = 1; // we _should_ send later because the slave needs more time
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    } else {
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        SPCR &= ~_BV(SPIE); // deactivate interrupt
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        INT0_HIGH // transfer is done, slave does not need to listen
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    }
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}
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/**
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 * check if SPI transfer is still busy
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 */
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int TransferIsBusy(void) {
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    return SPCR & _BV(SPIE);
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}
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/**
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 * start a new transfer of <data> with length <len>
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 */
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void StartTransfer(unsigned char *data, uint16_t len) {
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    INT0_LOW // /SS LOW ^= SS HIGH ^= slave should listen
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    // set up pointer and length for interrupt handler
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    iptr = data;
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    icnt = len;
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    SPCR |= _BV(SPIE); // enable spi interrupt
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    SPDR = *iptr; // start transfer by first bye
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}