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196 killagreg 1
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
1 ingob 2
* File Name          : usb_regs.h
3
* Author             : MCD Application Team
196 killagreg 4
* Version            : V4.0.0
5
* Date               : 09/29/2008
6
* Description        : Interface prototype functions to USB cell registers.
1 ingob 7
********************************************************************************
196 killagreg 8
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
1 ingob 9
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10
* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11
* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12
* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13
* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14
*******************************************************************************/
196 killagreg 15
 
1 ingob 16
/* Define to prevent recursive inclusion -------------------------------------*/
17
#ifndef __USB_REGS_H
18
#define __USB_REGS_H
196 killagreg 19
 
1 ingob 20
/* Includes ------------------------------------------------------------------*/
21
/* Exported types ------------------------------------------------------------*/
22
 
196 killagreg 23
typedef enum _EP_DBUF_DIR{  /* double buffered endpoint direction */
24
  EP_DBUF_ERR,
25
  EP_DBUF_OUT,
26
  EP_DBUF_IN
1 ingob 27
}EP_DBUF_DIR;
28
 
29
/* endpoint buffer number */
196 killagreg 30
enum EP_BUF_NUM{
31
  EP_NOBUF,
32
  EP_BUF0,
33
  EP_BUF1
1 ingob 34
};
35
 
36
/* Exported constants --------------------------------------------------------*/
37
#ifdef STR7xx
38
 
196 killagreg 39
#ifdef STR71x /*STR71x family*/
40
#define RegBase  (0xC0008800L)  /* USB_IP Peripheral Registers base address */
41
#define PMAAddr  (0xC0008000L)  /* USB_IP Packet Memory Area base address   */
42
#endif /*end of STR71x family*/
43
 
44
#ifdef STR75x /*STR75x family*/
45
#define RegBase  (0xFFFFA800L)  /* USB_IP Peripheral Registers base address */
46
#define PMAAddr  (0xFFFFA000L)  /* USB_IP Packet Memory Area base address   */
47
#endif /*end of STR75x family*/
48
 
1 ingob 49
#endif /*end of STR7xx family*/
50
 
51
#ifdef STR91x /*STR91x family*/
52
 
196 killagreg 53
#ifdef STR91x_USB_BUFFERED
54
#define RegBase  (0x60000800L)  /* USB_IP Peripheral Registers base address */
55
#define PMAAddr  (0x60000000L)  /* USB_IP Packet Memory Area base address */
1 ingob 56
#endif
57
 
196 killagreg 58
#ifdef STR91x_USB_NON_BUFFERED
59
#define RegBase  (0x70000800L)  /* USB_IP Peripheral Registers base address */
60
#define PMAAddr  (0x70000000L)  /* USB_IP Packet Memory Area base address */
61
#endif
62
#endif
63
 
1 ingob 64
/* General registers */
196 killagreg 65
/* Control register */
66
#define CNTR    ((volatile unsigned *)(RegBase + 0x40))
67
/* Interrupt status register */
68
#define ISTR    ((volatile unsigned *)(RegBase + 0x44))
69
/* Frame number register */
70
#define FNR     ((volatile unsigned *)(RegBase + 0x48))
71
/* Device address register */
72
#define DADDR   ((volatile unsigned *)(RegBase + 0x4C))
73
/* Buffer Table address register */
74
#define BTABLE  ((volatile unsigned *)(RegBase + 0x50))
1 ingob 75
 
76
#ifdef STR91x /*STR91x family DMA registers*/
196 killagreg 77
/* DMA control register 1 */
78
#define DMACR1  ((volatile unsigned *)(RegBase + 0x54))
79
/* DMA control register 2 */
80
#define DMACR2  ((volatile unsigned *)(RegBase + 0x58))
81
/* DMA control register 3 */
82
#define DMACR3  ((volatile unsigned *)(RegBase + 0x5C))
83
/* DMA burst size register */
84
#define DMABSIZE ((volatile unsigned *)(RegBase + 0x60))
85
/* DMA LLI register */
86
#define DMALLI  ((volatile unsigned *)(RegBase + 0x64))
1 ingob 87
 
88
#endif
89
 
90
/* Endpoint registers */
196 killagreg 91
/* endpoint 0 register address */
92
#define EP0REG  ((volatile unsigned *)(RegBase))
1 ingob 93
/* endpoints enumeration */
196 killagreg 94
#define ENDP0  ((u8)0)
95
#define ENDP1  ((u8)1)
96
#define ENDP2  ((u8)2)
97
#define ENDP3  ((u8)3)
98
#define ENDP4  ((u8)4)
99
#define ENDP5  ((u8)5)
100
#define ENDP6  ((u8)6)
101
#define ENDP7  ((u8)7)  /* Only 8  endpoints for STR75x Family */
102
#define ENDP8  ((u8)8)
103
#define ENDP9  ((u8)9)  /* Only 10 endpoints for STR91x Family */
104
#define ENDP10  ((u8)10)
105
#define ENDP11  ((u8)11)
106
#define ENDP12  ((u8)12)
107
#define ENDP13  ((u8)13)
108
#define ENDP14  ((u8)14)
109
#define ENDP15  ((u8)15)
1 ingob 110
 
196 killagreg 111
/******************************************************************************/
112
/*                       ISTR interrupt events                     */
113
/******************************************************************************/
114
#define ISTR_CTR    (0x8000) /* Correct TRansfer         (clear-only bit) */
115
#define ISTR_DOVR   (0x4000) /* DMA OVeR/underrun  (clear-only bit) */
116
#define ISTR_ERR    (0x2000) /* ERRor   (clear-only bit) */
117
#define ISTR_WKUP   (0x1000) /* WaKe UP   (clear-only bit) */
118
#define ISTR_SUSP   (0x0800) /* SUSPend   (clear-only bit) */
119
#define ISTR_RESET  (0x0400) /* RESET   (clear-only bit) */
120
#define ISTR_SOF    (0x0200) /* Start Of Frame  (clear-only bit) */
121
#define ISTR_ESOF   (0x0100) /* Expected Start Of Frame (clear-only bit) */
1 ingob 122
 
123
#ifdef STR91x /*STR91x family*/
196 killagreg 124
#define ISTR_SZDPR      (0x0080) /* Short or Zero-Length Received Data Packet */
125
#endif
1 ingob 126
 
196 killagreg 127
#define ISTR_DIR    (0x0010)  /* DIRection of transaction (read-only bit)  */
128
#define ISTR_EP_ID  (0x000F)  /* EndPoint IDentifier  (read-only bit)  */
1 ingob 129
 
196 killagreg 130
#define CLR_CTR    (~ISTR_CTR)      /* clear Correct TRansfer bit */
131
#define CLR_DOVR   (~ISTR_DOVR)     /* clear DMA OVeR/underrun bit*/
132
#define CLR_ERR    (~ISTR_ERR)      /* clear ERRor bit */
133
#define CLR_WKUP   (~ISTR_WKUP)     /* clear WaKe UP bit     */
134
#define CLR_SUSP   (~ISTR_SUSP)     /* clear SUSPend bit     */
135
#define CLR_RESET  (~ISTR_RESET)    /* clear RESET bit      */
136
#define CLR_SOF    (~ISTR_SOF)      /* clear Start Of Frame bit   */
137
#define CLR_ESOF   (~ISTR_ESOF)     /* clear Expected Start Of Frame bit */
1 ingob 138
 
139
#ifdef STR91x /*STR91x family*/
196 killagreg 140
#define CLR_SZDPR   (~ISTR_SZDPR)    /* clear SZDPR bit */
141
#endif
1 ingob 142
 
196 killagreg 143
/******************************************************************************/
144
/*             CNTR control register bits definitions                    */
145
/******************************************************************************/
146
#define CNTR_CTRM   (0x8000) /* Correct TRansfer Mask */
147
#define CNTR_DOVRM  (0x4000) /* DMA OVeR/underrun Mask */
148
#define CNTR_ERRM   (0x2000) /* ERRor Mask */
149
#define CNTR_WKUPM  (0x1000) /* WaKe UP Mask */
150
#define CNTR_SUSPM  (0x0800) /* SUSPend Mask */
151
#define CNTR_RESETM (0x0400) /* RESET Mask   */
152
#define CNTR_SOFM   (0x0200) /* Start Of Frame Mask */
153
#define CNTR_ESOFM  (0x0100) /* Expected Start Of Frame Mask */
1 ingob 154
 
155
#ifdef STR91x /*STR91x family*/
196 killagreg 156
#define CNTR_SZDPRM (0x0080) /* Short or Zero-Length Received Data Packet Mask*/
1 ingob 157
#endif
158
 
196 killagreg 159
#define CNTR_RESUME (0x0010) /* RESUME request */
160
#define CNTR_FSUSP  (0x0008) /* Force SUSPend */
161
#define CNTR_LPMODE (0x0004) /* Low-power MODE */
162
#define CNTR_PDWN   (0x0002) /* Power DoWN */
163
#define CNTR_FRES   (0x0001) /* Force USB RESet */
1 ingob 164
 
196 killagreg 165
/******************************************************************************/
166
/*              FNR Frame Number Register bit definitions              */
167
/******************************************************************************/
168
#define FNR_RXDP (0x8000) /* status of D+ data line */
169
#define FNR_RXDM (0x4000) /* status of D- data line */
170
#define FNR_LCK  (0x2000) /* LoCKed */
171
#define FNR_LSOF (0x1800) /* Lost SOF */
172
#define FNR_FN  (0x07FF) /* Frame Number */
173
/******************************************************************************/
174
/*                DADDR Device ADDRess bit definitions                */
175
/******************************************************************************/
176
#define DADDR_EF (0x80)
177
#define DADDR_ADD (0x7F)
178
 
179
/******************************************************************************/
1 ingob 180
/* Endpoint register */
196 killagreg 181
#define EP_CTR_RX      (0x8000) /* EndPoint Correct TRansfer RX  */
1 ingob 182
#define EP_DTOG_RX     (0x4000) /* EndPoint Data TOGGLE RX */
196 killagreg 183
#define EPRX_STAT      (0x3000) /* EndPoint RX STATus bit field */
184
#define EP_SETUP       (0x0800) /* EndPoint SETUP */
1 ingob 185
#define EP_T_FIELD     (0x0600) /* EndPoint TYPE */
186
#define EP_KIND        (0x0100) /* EndPoint KIND */
187
#define EP_CTR_TX      (0x0080) /* EndPoint Correct TRansfer TX */
188
#define EP_DTOG_TX     (0x0040) /* EndPoint Data TOGGLE TX */
196 killagreg 189
#define EPTX_STAT      (0x0030) /* EndPoint TX STATus bit field */
1 ingob 190
#define EPADDR_FIELD   (0x000F) /* EndPoint ADDRess FIELD */
191
 
192
/* EndPoint REGister MASK (no toggle fields) */
196 killagreg 193
#define EPREG_MASK     (EP_CTR_RX | EP_SETUP | EP_T_FIELD | EP_KIND |\
194
                        EP_CTR_TX |EPADDR_FIELD)
1 ingob 195
 
196
/* EP_TYPE[1:0] EndPoint TYPE */
197
#define EP_TYPE_MASK   (0x0600) /* EndPoint TYPE Mask */
196 killagreg 198
#define EP_BULK        (0x0000) /* EndPoint BULK */
1 ingob 199
#define EP_CONTROL     (0x0200) /* EndPoint CONTROL */
200
#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
201
#define EP_INTERRUPT   (0x0600) /* EndPoint INTERRUPT */
202
#define EP_T_MASK      (~EP_T_FIELD & EPREG_MASK)
203
 
204
 
205
/* EP_KIND EndPoint KIND */
206
#define EPKIND_MASK    (~EP_KIND & EPREG_MASK)
207
 
208
/* STAT_TX[1:0] STATus for TX transfer */
196 killagreg 209
#define EP_TX_DIS      (0x0000) /* EndPoint TX DISabled */
210
#define EP_TX_STALL    (0x0010) /* EndPoint TX STALLed */
1 ingob 211
#define EP_TX_NAK      (0x0020) /* EndPoint TX NAKed */
196 killagreg 212
#define EP_TX_VALID    (0x0030) /* EndPoint TX VALID */
213
#define EPTX_DTOG1     (0x0010) /* EndPoint TX Data TOGgle bit1 */
214
#define EPTX_DTOG2     (0x0020) /* EndPoint TX Data TOGgle bit2 */
1 ingob 215
#define EPTX_DTOGMASK  (EPTX_STAT|EPREG_MASK)
216
 
217
/* STAT_RX[1:0] STATus for RX transfer */
196 killagreg 218
#define EP_RX_DIS      (0x0000) /* EndPoint RX DISabled */
219
#define EP_RX_STALL    (0x1000) /* EndPoint RX STALLed */
220
#define EP_RX_NAK      (0x2000) /* EndPoint RX NAKed */
221
#define EP_RX_VALID    (0x3000) /* EndPoint RX VALID */
222
#define EPRX_DTOG1     (0x1000) /* EndPoint RX Data TOGgle bit1 */
223
#define EPRX_DTOG2     (0x2000) /* EndPoint RX Data TOGgle bit1 */
1 ingob 224
#define EPRX_DTOGMASK  (EPRX_STAT|EPREG_MASK)
225
 
196 killagreg 226
/* Exported macro */
227
 
1 ingob 228
/* SetCNTR */
196 killagreg 229
#define _SetCNTR(wRegValue)  (*CNTR   = (u16)wRegValue)
230
 
1 ingob 231
/* SetISTR */
196 killagreg 232
#define _SetISTR(wRegValue)  (*ISTR   = (u16)wRegValue)
233
 
1 ingob 234
/* SetDADDR */
235
#define _SetDADDR(wRegValue) (*DADDR  = (u16)wRegValue)
196 killagreg 236
 
1 ingob 237
/* SetBTABLE */
238
#define _SetBTABLE(wRegValue)(*BTABLE = (u16)(wRegValue & 0xFFF8))
196 killagreg 239
 
1 ingob 240
/* GetCNTR */
241
#define _GetCNTR()   ((u16) *CNTR)
196 killagreg 242
 
1 ingob 243
/* GetISTR */
244
#define _GetISTR()   ((u16) *ISTR)
196 killagreg 245
 
1 ingob 246
/* GetFNR */
247
#define _GetFNR()    ((u16) *FNR)
196 killagreg 248
 
1 ingob 249
/* GetDADDR */
196 killagreg 250
#define _GetDADDR()  ((u16) *DADDR)
251
 
1 ingob 252
/* GetBTABLE */
253
#define _GetBTABLE() ((u16) *BTABLE)
196 killagreg 254
 
1 ingob 255
/* SetENDPOINT */
256
#define _SetENDPOINT(bEpNum,wRegValue)  (*(EP0REG + bEpNum)= \
196 killagreg 257
    (u16)wRegValue)
258
 
1 ingob 259
/* GetENDPOINT */
196 killagreg 260
#define _GetENDPOINT(bEpNum)        ((u16)(*(EP0REG + bEpNum)))
261
/*******************************************************************************
262
* Macro Name     : SetEPType
263
* Description    : sets the type in the endpoint register(bits EP_TYPE[1:0])
264
* Input          : bEpNum: Endpoint Number.
265
*                  wType
266
* Output         : None.
267
* Return         : None.
268
*******************************************************************************/
269
#define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\
270
                                  ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType)))
271
 
272
/*******************************************************************************
273
* Macro Name     : GetEPType
274
* Description    : gets the type in the endpoint register(bits EP_TYPE[1:0])
275
* Input          : bEpNum: Endpoint Number.
276
* Output         : None.
277
* Return         : Endpoint Type
278
*******************************************************************************/
1 ingob 279
#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
196 killagreg 280
 
281
/*******************************************************************************
282
* Macro Name     : SetEPTxStatus
283
* Description    : sets the status for tx transfer (bits STAT_TX[1:0]).
284
* Input          : bEpNum: Endpoint Number.
285
*                  wState: new state
286
* Output         : None.
287
* Return         : None.
288
*******************************************************************************/
1 ingob 289
#define _SetEPTxStatus(bEpNum,wState) {\
196 killagreg 290
    register u16 _wRegVal;       \
291
    _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\
292
    /* toggle first bit ? */     \
293
    if((EPTX_DTOG1 & wState)!= 0)      \
294
      _wRegVal ^= EPTX_DTOG1;        \
295
    /* toggle second bit ?  */         \
296
    if((EPTX_DTOG2 & wState)!= 0)      \
297
      _wRegVal ^= EPTX_DTOG2;        \
298
    _SetENDPOINT(bEpNum, _wRegVal);    \
299
  } /* _SetEPTxStatus */
1 ingob 300
 
196 killagreg 301
/*******************************************************************************
302
* Macro Name     : SetEPRxStatus
303
* Description    : sets the status for rx transfer (bits STAT_TX[1:0])
304
* Input          : bEpNum: Endpoint Number.
305
*                  wState: new state.
306
* Output         : None.
307
* Return         : None.
308
*******************************************************************************/
1 ingob 309
#define _SetEPRxStatus(bEpNum,wState) {\
196 killagreg 310
    register u16 _wRegVal;   \
311
    \
312
    _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\
313
    /* toggle first bit ? */  \
314
    if((EPRX_DTOG1 & wState)!= 0) \
315
      _wRegVal ^= EPRX_DTOG1;  \
316
    /* toggle second bit ? */  \
317
    if((EPRX_DTOG2 & wState)!= 0) \
318
      _wRegVal ^= EPRX_DTOG2;  \
319
    _SetENDPOINT(bEpNum, _wRegVal); \
320
  } /* _SetEPRxStatus */
321
 
322
/*******************************************************************************
323
* Macro Name     : GetEPTxStatus / GetEPRxStatus
324
* Description    : gets the status for tx/rx transfer (bits STAT_TX[1:0]
325
*                  /STAT_RX[1:0])
326
* Input          : bEpNum: Endpoint Number.
327
* Output         : None.
328
* Return         : status .
329
*******************************************************************************/
1 ingob 330
#define _GetEPTxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPTX_STAT)
331
#define _GetEPRxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPRX_STAT)
196 killagreg 332
 
333
/*******************************************************************************
334
* Macro Name     : SetEPTxValid / SetEPRxValid
335
* Description    : sets directly the VALID tx/rx-status into the enpoint register
336
* Input          : bEpNum: Endpoint Number.
337
* Output         : None.
338
* Return         : None.
339
*******************************************************************************/
1 ingob 340
#define _SetEPTxValid(bEpNum)     (_SetEPTxStatus(bEpNum, EP_TX_VALID))
341
#define _SetEPRxValid(bEpNum)     (_SetEPRxStatus(bEpNum, EP_RX_VALID))
196 killagreg 342
 
343
/*******************************************************************************
344
* Macro Name     : GetTxStallStatus / GetRxStallStatus.
345
* Description    : checks stall condition in an endpoint.
346
* Input          : bEpNum: Endpoint Number.
347
* Output         : None.
348
* Return         : TRUE = endpoint in stall condition.
349
*******************************************************************************/
1 ingob 350
#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \
196 killagreg 351
                                   == EP_TX_STALL)
1 ingob 352
#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \
196 killagreg 353
                                   == EP_RX_STALL)
354
/*******************************************************************************
355
* Macro Name     : SetEP_KIND / ClearEP_KIND.
356
* Description    : set & clear EP_KIND bit.
357
* Input          : bEpNum: Endpoint Number.
358
* Output         : None.
359
* Return         : None.
360
*******************************************************************************/
1 ingob 361
#define _SetEP_KIND(bEpNum)    (_SetENDPOINT(bEpNum, \
196 killagreg 362
                                (_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))
1 ingob 363
#define _ClearEP_KIND(bEpNum)  (_SetENDPOINT(bEpNum, \
196 killagreg 364
                                (_GetENDPOINT(bEpNum) & EPKIND_MASK)))
365
 
366
/*******************************************************************************
367
* Macro Name     : Set_Status_Out / Clear_Status_Out.
368
* Description    : Sets/clears directly STATUS_OUT bit in the endpoint register.
369
* Input          : bEpNum: Endpoint Number.
370
* Output         : None.
371
* Return         : None.
372
*******************************************************************************/
373
#define _Set_Status_Out(bEpNum)    _SetEP_KIND(bEpNum)
1 ingob 374
#define _Clear_Status_Out(bEpNum)  _ClearEP_KIND(bEpNum)
196 killagreg 375
 
376
/*******************************************************************************
377
* Macro Name     : SetEPDoubleBuff / ClearEPDoubleBuff.
378
* Description    : Sets/clears directly EP_KIND bit in the endpoint register.
379
* Input          : bEpNum: Endpoint Number.
380
* Output         : None.
381
* Return         : None.
382
*******************************************************************************/
1 ingob 383
#define _SetEPDoubleBuff(bEpNum)   _SetEP_KIND(bEpNum)
384
#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
196 killagreg 385
 
386
/*******************************************************************************
387
* Macro Name     : ClearEP_CTR_RX / ClearEP_CTR_TX.
388
* Description    : Clears bit CTR_RX / CTR_TX in the endpoint register.
389
* Input          : bEpNum: Endpoint Number.
390
* Output         : None.
391
* Return         : None.
392
*******************************************************************************/
1 ingob 393
#define _ClearEP_CTR_RX(bEpNum)   (_SetENDPOINT(bEpNum,\
196 killagreg 394
                                   _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
1 ingob 395
#define _ClearEP_CTR_TX(bEpNum)   (_SetENDPOINT(bEpNum,\
196 killagreg 396
                                   _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
397
 
398
/*******************************************************************************
399
* Macro Name     : ToggleDTOG_RX / ToggleDTOG_TX .
400
* Description    : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
401
* Input          : bEpNum: Endpoint Number.
402
* Output         : None.
403
* Return         : None.
404
*******************************************************************************/
1 ingob 405
#define _ToggleDTOG_RX(bEpNum)    (_SetENDPOINT(bEpNum, \
196 killagreg 406
                                   EP_DTOG_RX | _GetENDPOINT(bEpNum) & EPREG_MASK))
1 ingob 407
#define _ToggleDTOG_TX(bEpNum)    (_SetENDPOINT(bEpNum, \
196 killagreg 408
                                   EP_DTOG_TX | _GetENDPOINT(bEpNum) & EPREG_MASK))
409
 
410
/*******************************************************************************
411
* Macro Name     : ClearDTOG_RX / ClearDTOG_TX.
412
* Description    : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
413
* Input          : bEpNum: Endpoint Number.
414
* Output         : None.
415
* Return         : None.
416
*******************************************************************************/
1 ingob 417
#define _ClearDTOG_RX(bEpNum)  if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\
196 killagreg 418
    _ToggleDTOG_RX(bEpNum)
1 ingob 419
#define _ClearDTOG_TX(bEpNum)  if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\
196 killagreg 420
    _ToggleDTOG_TX(bEpNum)
421
/*******************************************************************************
422
* Macro Name     : SetEPAddress.
423
* Description    : Sets address in an endpoint register.
424
* Input          : bEpNum: Endpoint Number.
425
*                  bAddr: Address.
426
* Output         : None.
427
* Return         : None.
428
*******************************************************************************/
1 ingob 429
 
430
#define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\
196 killagreg 431
    _GetENDPOINT(bEpNum) & EPREG_MASK | bAddr)
432
/*******************************************************************************
433
* Macro Name     : GetEPAddress.
434
* Description    : Gets address in an endpoint register.
435
* Input          : bEpNum: Endpoint Number.
436
* Output         : None.
437
* Return         : None.
438
*******************************************************************************/
1 ingob 439
#define _GetEPAddress(bEpNum) ((u8)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
196 killagreg 440
 
1 ingob 441
#ifdef STR7xx /*STR7xx family*/
196 killagreg 442
#define _pEPTxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8  )*2 + PMAAddr))
443
#define _pEPTxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr))
444
#define _pEPRxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr))
445
#define _pEPRxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr))
446
#endif
1 ingob 447
 
448
#ifdef STR91x /*STR91x family*/
449
/* Pointers on endpoint(bEpNum) Count & Addr registers on PMA */
196 killagreg 450
#define _pEPBufCount(bEpNum) ((u32 *)(_GetBTABLE()+bEpNum*8 + 4   + PMAAddr))
451
#define _pEPBufAddr(bEpNum) ((u32 *)(_GetBTABLE()+bEpNum*8         + PMAAddr))
1 ingob 452
#endif
196 killagreg 453
/*******************************************************************************
454
* Macro Name     : SetEPTxAddr / SetEPRxAddr.
455
* Description    : sets address of the tx/rx buffer.
456
* Input          : bEpNum: Endpoint Number.
457
*                  wAddr: address to be set (must be word aligned).
458
* Output         : None.
459
* Return         : None.
460
*******************************************************************************/
1 ingob 461
#ifdef STR7xx /*STR7xx family*/
462
#define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
463
#define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
464
#endif
465
 
466
#ifdef STR91x /*STR91x family*/
467
#define _SetEPTxAddr(bEpNum , wAddr) {\
196 killagreg 468
    *_pEPBufAddr(bEpNum) &=0xFFFF0000; \
469
    *_pEPBufAddr(bEpNum) |=((wAddr)&0x0FFFC);\
470
  }
1 ingob 471
#define _SetEPRxAddr(bEpNum, wAddr) {\
196 killagreg 472
    *_pEPBufAddr(bEpNum) &=0x0000FFFF;\
473
    *_pEPBufAddr(bEpNum) |=((wAddr<<16)&0xFFFC0000);\
474
  }
1 ingob 475
#endif
476
 
196 killagreg 477
/*******************************************************************************
478
* Macro Name     : GetEPTxAddr / GetEPRxAddr.
479
* Description    : Gets address of the tx/rx buffer.
480
* Input          : bEpNum: Endpoint Number.
481
* Output         : None.
482
* Return         : address of the buffer.
483
*******************************************************************************/
1 ingob 484
#ifdef STR7xx /*STR7xx family*/
485
#define _GetEPTxAddr(bEpNum) ((u16)*_pEPTxAddr(bEpNum))
486
#define _GetEPRxAddr(bEpNum) ((u16)*_pEPRxAddr(bEpNum))
487
#endif
488
 
489
#ifdef STR91x /*STR91x family*/
490
#define _GetEPTxAddr(bEpNum) ((u16)(*_pEPBufAddr(bEpNum) &0x0000FFFF))
491
#define _GetEPRxAddr(bEpNum) ((u16)((*_pEPBufAddr(bEpNum)&0xFFFF0000)>>16))
492
#endif
196 killagreg 493
/*******************************************************************************
494
* Macro Name     : SetEPCountRxReg.
495
* Description    : Sets counter of rx buffer with no. of blocks.
496
* Input          : pdwReg: pointer to counter.
497
*                  wCount: Counter.
498
* Output         : None.
499
* Return         : None.
500
*******************************************************************************/
1 ingob 501
#ifdef STR7xx /*STR7xx family*/
502
#define _BlocksOf32(dwReg,wCount,wNBlocks) {\
196 killagreg 503
    wNBlocks = wCount >> 5;\
504
    if((wCount & 0x1f) == 0)\
505
      wNBlocks--;\
506
    *pdwReg = (u32)((wNBlocks << 10) | 0x8000);\
507
  }/* _BlocksOf32 */
1 ingob 508
 
509
#define _BlocksOf2(dwReg,wCount,wNBlocks) {\
196 killagreg 510
    wNBlocks = wCount >> 1;\
511
    if((wCount & 0x1) != 0)\
512
      wNBlocks++;\
513
    *pdwReg = (u32)(wNBlocks << 10);\
514
  }/* _BlocksOf2 */
1 ingob 515
 
516
#define _SetEPCountRxReg(dwReg,wCount)  {\
196 killagreg 517
    u16 wNBlocks;\
518
    if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\
519
    else {_BlocksOf2(dwReg,wCount,wNBlocks);}\
520
  }/* _SetEPCountRxReg */
1 ingob 521
 
522
#define _SetEPRxDblBuf0Count(bEpNum,wCount) {\
196 killagreg 523
    u32 *pdwReg = _pEPTxCount(bEpNum); \
524
    _SetEPCountRxReg(pdwReg, wCount);\
525
  }
526
#endif
527
/*******************************************************************************
528
* Macro Name     : SetEPTxCount / SetEPRxCount.
529
* Description    : sets counter for the tx/rx buffer.
530
* Input          : bEpNum: endpoint number.
531
*                  wCount: Counter value.
532
* Output         : None.
533
* Return         : None.
534
*******************************************************************************/
1 ingob 535
 
536
#ifdef STR7xx /*STR7xx family*/
537
#define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount)
538
#define _SetEPRxCount(bEpNum,wCount) {\
196 killagreg 539
    u32 *pdwReg = _pEPRxCount(bEpNum); \
540
    _SetEPCountRxReg(pdwReg, wCount);\
541
  }
542
#endif
1 ingob 543
 
544
#ifdef STR91x /*STR91x family*/
545
#define _SetEPTxCount(bEpNum,wCount) {\
196 killagreg 546
    *_pEPBufCount(bEpNum) &=0xFFFFFC00;\
547
    *_pEPBufCount(bEpNum) |=wCount;\
548
  }
1 ingob 549
 
550
#define _SetEPRxCount(bEpNum,wCount) {\
196 killagreg 551
    u32 BLsize=0;\
552
    u32 Blocks;\
553
    if (wCount < 64) Blocks = wCount>>1;\
554
    else\
555
    {\
556
      BLsize = 0x80000000;\
557
      Blocks = wCount>>6;\
558
    }\
559
    *_pEPBufCount(bEpNum) &=~0x80000000;\
560
    *_pEPBufCount(bEpNum) |=BLsize;\
561
    *_pEPBufCount(bEpNum)  &=0x83FFFFFF;\
562
    *_pEPBufCount(bEpNum) |=Blocks<<26;\
563
    *_pEPBufCount(bEpNum) &=0xFC00FFFF;\
564
  }
565
#endif
566
/*******************************************************************************
567
* Macro Name     : GetEPTxCount / GetEPRxCount.
568
* Description    : gets counter of the tx buffer.
569
* Input          : bEpNum: endpoint number.
570
* Output         : None.
571
* Return         : Counter value.
572
*******************************************************************************/
1 ingob 573
#ifdef STR7xx /*STR7xx family*/
574
#define _GetEPTxCount(bEpNum)((u16)(*_pEPTxCount(bEpNum)) & 0x3ff)
575
#define _GetEPRxCount(bEpNum)((u16)(*_pEPRxCount(bEpNum)) & 0x3ff)
196 killagreg 576
#endif
1 ingob 577
 
578
#ifdef STR91x /*STR91x family*/
579
#define _GetEPTxCount(bEpNum) (u16)(*_pEPBufCount(bEpNum)&0x3FF)
580
#define _GetEPRxCount(bEpNum) (u16)((*_pEPBufCount(bEpNum)&0x3FF0000)>>16)
196 killagreg 581
#endif
582
 
583
/*******************************************************************************
584
* Macro Name     : SetEPDblBuf0Addr / SetEPDblBuf1Addr.
585
* Description    : Sets buffer 0/1 address in a double buffer endpoint.
586
* Input          : bEpNum: endpoint number.
587
*                : wBuf0Addr: buffer 0 address.
588
* Output         : None.
589
* Return         : None.
590
*******************************************************************************/
1 ingob 591
#define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);}
592
#define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);}
593
 
196 killagreg 594
/*******************************************************************************
595
* Macro Name     : SetEPDblBuffAddr.
596
* Description    : Sets addresses in a double buffer endpoint.
597
* Input          : bEpNum: endpoint number.
598
*                : wBuf0Addr: buffer 0 address.
599
*                : wBuf1Addr = buffer 1 address.
600
* Output         : None.
601
* Return         : None.
602
*******************************************************************************/
1 ingob 603
#define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \
196 killagreg 604
    _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\
605
    _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\
606
  } /* _SetEPDblBuffAddr */
607
 
608
/*******************************************************************************
609
* Macro Name     : GetEPDblBuf0Addr / GetEPDblBuf1Addr.
610
* Description    : Gets buffer 0/1 address of a double buffer endpoint.
611
* Input          : bEpNum: endpoint number.
612
* Output         : None.
613
* Return         : None.
614
*******************************************************************************/
1 ingob 615
#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
616
#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
617
 
196 killagreg 618
/*******************************************************************************
619
* Macro Name     : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count.
620
* Description    : Gets buffer 0/1 address of a double buffer endpoint.
621
* Input          : bEpNum: endpoint number.
622
*                : bDir: endpoint dir  EP_DBUF_OUT = OUT
623
*                                      EP_DBUF_IN  = IN
624
*                : wCount: Counter value
625
* Output         : None.
626
* Return         : None.
627
*******************************************************************************/
1 ingob 628
#ifdef STR7xx /*STR7xx family*/
629
 
630
#define _SetEPDblBuf0Count(bEpNum, bDir, wCount)  { \
196 killagreg 631
    if(bDir == EP_DBUF_OUT)\
632
      /* OUT endpoint */ \
633
    {_SetEPRxDblBuf0Count(bEpNum,wCount);} \
634
    else if(bDir == EP_DBUF_IN)\
635
      /* IN endpoint */ \
636
      *_pEPTxCount(bEpNum) = (u32)wCount;  \
637
  } /* SetEPDblBuf0Count*/
1 ingob 638
 
639
#define _SetEPDblBuf1Count(bEpNum, bDir, wCount)  { \
196 killagreg 640
    if(bDir == EP_DBUF_OUT)\
641
      /* OUT endpoint */ \
642
    {_SetEPRxCount(bEpNum,wCount);}\
643
    else if(bDir == EP_DBUF_IN)\
644
      /* IN endpoint */\
645
      *_pEPRxCount(bEpNum) = (u32)wCount; \
646
  } /* SetEPDblBuf1Count */
1 ingob 647
 
648
#define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\
196 killagreg 649
    _SetEPDblBuf0Count(bEpNum, bDir, wCount); \
650
    _SetEPDblBuf1Count(bEpNum, bDir, wCount); \
651
  } /* _SetEPDblBuffCount  */
652
#endif
653
 
654
/*******************************************************************************
655
* Macro Name     : GetEPDblBuf0Count / GetEPDblBuf1Count.
656
* Description    : Gets buffer 0/1 rx/tx counter for double buffering.
657
* Input          : bEpNum: endpoint number.
658
* Output         : None.
659
* Return         : None.
660
*******************************************************************************/
1 ingob 661
#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
662
#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
663
 
664
/* External variables --------------------------------------------------------*/
665
extern volatile u16 wIstr;  /* ISTR register last read value */
666
 
667
/* Exported functions ------------------------------------------------------- */
668
void SetCNTR(u16 /*wRegValue*/);
669
void SetISTR(u16 /*wRegValue*/);
670
void SetDADDR(u16 /*wRegValue*/);
671
void SetBTABLE(u16 /*wRegValue*/);
672
void SetBTABLE(u16 /*wRegValue*/);
673
u16 GetCNTR(void);
674
u16 GetISTR(void);
675
u16 GetFNR(void);
676
u16 GetDADDR(void);
677
u16 GetBTABLE(void);
196 killagreg 678
void SetENDPOINT(u8 /*bEpNum*/, u16 /*wRegValue*/);
1 ingob 679
u16 GetENDPOINT(u8 /*bEpNum*/);
196 killagreg 680
void SetEPType(u8 /*bEpNum*/, u16 /*wType*/);
1 ingob 681
u16 GetEPType(u8 /*bEpNum*/);
196 killagreg 682
void SetEPTxStatus(u8 /*bEpNum*/, u16 /*wState*/);
683
void SetEPRxStatus(u8 /*bEpNum*/, u16 /*wState*/);
684
void SetDouBleBuffEPStall(u8 /*bEpNum*/, u8 bDir);
1 ingob 685
u16 GetEPTxStatus(u8 /*bEpNum*/);
686
u16 GetEPRxStatus(u8 /*bEpNum*/);
687
void SetEPTxValid(u8 /*bEpNum*/);
688
void SetEPRxValid(u8 /*bEpNum*/);
689
u16 GetTxStallStatus(u8 /*bEpNum*/);
690
u16 GetRxStallStatus(u8 /*bEpNum*/);
691
void SetEP_KIND(u8 /*bEpNum*/);
692
void ClearEP_KIND(u8 /*bEpNum*/);
693
void Set_Status_Out(u8 /*bEpNum*/);
694
void Clear_Status_Out(u8 /*bEpNum*/);
695
void SetEPDoubleBuff(u8 /*bEpNum*/);
696
void ClearEPDoubleBuff(u8 /*bEpNum*/);
697
void ClearEP_CTR_RX(u8 /*bEpNum*/);
698
void ClearEP_CTR_TX(u8 /*bEpNum*/);
699
void ToggleDTOG_RX(u8 /*bEpNum*/);
700
void ToggleDTOG_TX(u8 /*bEpNum*/);
701
void ClearDTOG_RX(u8 /*bEpNum*/);
702
void ClearDTOG_TX(u8 /*bEpNum*/);
196 killagreg 703
void SetEPAddress(u8 /*bEpNum*/, u8 /*bAddr*/);
1 ingob 704
u8 GetEPAddress(u8 /*bEpNum*/);
196 killagreg 705
void SetEPTxAddr(u8 /*bEpNum*/, u16 /*wAddr*/);
706
void SetEPRxAddr(u8 /*bEpNum*/, u16 /*wAddr*/);
1 ingob 707
u16 GetEPTxAddr(u8 /*bEpNum*/);
708
u16 GetEPRxAddr(u8 /*bEpNum*/);
709
void SetEPCountRxReg(u32 * /*pdwReg*/, u16 /*wCount*/);
196 killagreg 710
void SetEPTxCount(u8 /*bEpNum*/, u16 /*wCount*/);
711
void SetEPRxCount(u8 /*bEpNum*/, u16 /*wCount*/);
1 ingob 712
u16 GetEPTxCount(u8 /*bEpNum*/);
713
u16 GetEPRxCount(u8 /*bEpNum*/);
196 killagreg 714
void SetEPDblBuf0Addr(u8 /*bEpNum*/, u16 /*wBuf0Addr*/);
715
void SetEPDblBuf1Addr(u8 /*bEpNum*/, u16 /*wBuf1Addr*/);
716
void SetEPDblBuffAddr(u8 /*bEpNum*/, u16 /*wBuf0Addr*/, u16 /*wBuf1Addr*/);
1 ingob 717
u16 GetEPDblBuf0Addr(u8 /*bEpNum*/);
718
u16 GetEPDblBuf1Addr(u8 /*bEpNum*/);
719
void SetEPDblBuffCount(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/);
720
void SetEPDblBuf0Count(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/);
721
void SetEPDblBuf1Count(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/);
722
u16 GetEPDblBuf0Count(u8 /*bEpNum*/);
723
u16 GetEPDblBuf1Count(u8 /*bEpNum*/);
724
EP_DBUF_DIR GetEPDblBufDir(u8 /*bEpNum*/);
196 killagreg 725
void FreeUserBuffer(u8 bEpNum/*bEpNum*/, u8 bDir);
726
u16 ToWord(u8, u8);
1 ingob 727
u16 ByteSwap(u16);
728
 
729
#ifdef STR91x /*STR91x family*/
730
/* DMA Functions */
731
void SetDMABurstTxSize(u8 /*DestBsize*/);
732
void SetDMABurstRxSize(u8 /*SrcBsize*/);
196 killagreg 733
void DMAUnlinkedModeTxConfig(u8 /*bEpNum*/ , u8 /*index*/);
1 ingob 734
void DMAUnlinkedModeTxEnable(u8 /*index*/);
735
void DMAUnlinkedModeTxDisable(u8 /*index*/);
736
void DMAUnlinkedModeRxEnable(u8 /*bEpNum*/);
737
void DMAUnlinkedModeRxDisable(u8 /*bEpNum*/);
738
void DMALinkedModeRxConfig(u8 /*bEpNum*/);
739
void DMALinkedModeTxConfig(u8 /*bEpNum*/);
740
void DMALinkedModeRxEnable(void);
741
void DMALinkedModeTxEnable(void);
742
void DMALinkedModeRxDisable(void);
743
void DMALinkedModeTxDisable(void);
744
void DMASynchEnable(void);
745
void DMASynchDisable(void);
746
void SetDMALLITxLength(u8 /*length*/);
747
void SetDMALLIRxLength(u8 /*length*/ );
748
void SetDMALLIRxPacketNum(u8 /*PacketNum*/);
749
u8 GetDMALLIRxPacketNum(void);
750
#endif /* End of STR91x family*/
751
 
752
#endif /* __USB_REGS_H */
753
 
754
 
196 killagreg 755
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/