Subversion Repositories NaviCtrl

Rev

Go to most recent revision | Details | Last modification | View Log | RSS feed

Rev Author Line No. Line
196 killagreg 1
/******************** (C) COPYRIGHT 2008 STMicroelectronics ********************
1 ingob 2
* File Name          : 91x_scu.h
3
* Author             : MCD Application Team
196 killagreg 4
* Version            : V2.1
5
* Date               : 12/22/2008
6
* Description        : This file provides the SCU library firmware functions
1 ingob 7
*                      prototypes & definitions
8
********************************************************************************
9
* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
10
* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
11
* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
12
* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
13
* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
14
* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
15
*******************************************************************************/
16
 
17
/* Define to prevent recursive inclusion -------------------------------------*/
18
#ifndef __91x_SCU_H
19
#define __91x_SCU_H
20
 
21
/* Includes ------------------------------------------------------------------*/
22
#include "91x_map.h"
23
 
24
/* Exported constants --------------------------------------------------------*/
25
 
26
/*MCLK_Source*/
27
#define SCU_MCLK_PLL      0x0
28
#define SCU_MCLK_RTC      0x1
29
#define SCU_MCLK_OSC      0x2
30
 
31
/*RCLK_Divisor*/
32
#define SCU_RCLK_Div1     0xFFFFFFE3
33
#define SCU_RCLK_Div2     0x4
34
#define SCU_RCLK_Div4     0x8
35
#define SCU_RCLK_Div8     0xC
36
#define SCU_RCLK_Div16    0x10
37
#define SCU_RCLK_Div1024  0x14
38
 
39
/*HCLK_Divisor*/
40
#define SCU_HCLK_Div1 0xFFFFFF9F
41
#define SCU_HCLK_Div2 0x20
42
#define SCU_HCLK_Div4 0x40
43
 
44
/*PCLK_Divisor*/
45
#define SCU_PCLK_Div1 0xFFFFFE7F
46
#define SCU_PCLK_Div2 0x80
47
#define SCU_PCLK_Div4 0x100
48
#define SCU_PCLK_Div8 0x180
49
 
50
/*FMICLK_Divisor*/
51
#define SCU_FMICLK_Div1 0xFFFEFFFF
52
#define SCU_FMICLK_Div2 0x10000
53
 
54
/*BRCLK_Divisor*/
55
#define SCU_BRCLK_Div1 0x200
56
#define SCU_BRCLK_Div2 0xFFFFFDFF
57
 
58
 
59
/*TIMx*/
60
#define SCU_TIM01 0x0
61
#define SCU_TIM23 0x1
62
 
63
 
64
/*USBCLK_Source*/
65
#define SCU_USBCLK_MCLK  0xFFFFF3FF
66
#define SCU_USBCLK_MCLK2 0x400
67
#define SCU_USBCLK_EXT   0x800
68
 
69
/*SCU_EMIBCLK*/
70
#define SCU_EMIBCLK_Div1 0xFFF9FFFF
71
#define SCU_EMIBCLK_Div2 0x20000
72
 
73
/*SCU_EMIMODE*/
74
#define SCU_EMI_MUX   0xFFFFFFBF
75
#define SCU_EMI_DEMUX 0x40
76
 
77
/*SCU_EMIALE_LEN*/
78
#define SCU_EMIALE_LEN1 0xFFFFFEFF
79
#define SCU_EMIALE_LEN2 0x100
80
 
81
/*SCU_EMIALE_POL*/
82
#define SCU_EMIALE_POLLow  0xFFFFFF7F
83
#define SCU_EMIALE_POLHigh 0x80
84
 
85
/*UART_IrDA_Mode*/
86
#define SCU_UARTMode_IrDA 0x1
87
#define SCU_UARTMode_UART 0x0
88
 
89
/*SCU_UARTx*/
90
#define SCU_UART0 0x0
91
#define SCU_UART1 0x1
92
#define SCU_UART2 0x2
93
 
94
/*APBPeriph*/
95
#define __TIM01 0x1
96
#define __TIM23 0x2
97
#define __MC    0x4
98
#define __UART0 0x8
99
#define __UART1 0x10
100
#define __UART2 0x20
101
#define __I2C0  0x40
102
#define __I2C1  0x80
103
#define __SSP0  0x100
104
#define __SSP1  0x200
105
#define __CAN   0x400
106
#define __ADC   0x800
107
#define __WDG   0x1000
108
#define __WIU   0x2000
109
#define __GPIO0 0x4000
110
#define __GPIO1 0x8000
111
#define __GPIO2 0x10000
112
#define __GPIO3 0x20000
113
#define __GPIO4 0x40000
114
#define __GPIO5 0x80000
115
#define __GPIO6 0x100000
116
#define __GPIO7 0x200000
117
#define __GPIO8 0x400000
118
#define __GPIO9 0x800000
119
#define __RTC   0x1000000
120
 
121
/*AHBPeriph*/
122
#define __FMI          0x1
123
#define __FPQBC        0x2
124
#define __SRAM         0x8
125
#define __SRAM_ARBITER 0x10
126
#define __VIC          0x20
127
#define __EMI          0x40
128
#define __EMI_MEM_CLK  0x80
129
#define __DMA          0x100
130
#define __USB          0x200
131
#define __USB48M       0x400
132
#define __ENET         0x800
133
#define __PFQBC_AHB    0x1000
134
 
135
/*SCU_IT*/
136
#define SCU_IT_LVD_RST    0x10
137
#define SCU_IT_SRAM_ERROR 0x8
138
#define SCU_IT_ACK_PFQBC  0x4
139
#define SCU_IT_LOCK_LOST  0x2
140
#define SCU_IT_LOCK       0x1
141
 
142
/*SCU_FLAG*/
143
#define SCU_FLAG_SRAM_ERROR 0x20
144
#define SCU_FLAG_ACK_PFQBC  0x10
145
#define SCU_FLAG_LVD_RESET  0x8
146
#define SCU_FLAG_WDG_RST    0x4
147
#define SCU_FLAG_LOCK_LOST  0x2
148
#define SCU_FLAG_LOCK       0x1
149
 
150
 
151
/* Module private variables --------------------------------------------------*/
152
/* Exported macro ------------------------------------------------------------*/
153
/* Private functions ---------------------------------------------------------*/
154
/* Exported functions ------------------------------------------------------- */
155
ErrorStatus SCU_MCLKSourceConfig(u32 MCLK_Source);
156
ErrorStatus SCU_PLLFactorsConfig(u8 PLLN, u8 PLLM, u8 PLLP);
157
ErrorStatus SCU_PLLCmd(FunctionalState NewState);
158
void SCU_RCLKDivisorConfig(u32 RCLK_Divisor);
159
void SCU_HCLKDivisorConfig(u32 HCLK_Divisor);
160
void SCU_PCLKDivisorConfig(u32 PCLK_Divisor);
161
void SCU_APBPeriphClockConfig(u32 APBPeriph, FunctionalState NewState);
162
void SCU_AHBPeriphClockConfig(u32 AHBPeriph, FunctionalState NewState);
163
void SCU_APBPeriphReset(u32 APBPeriph, FunctionalState NewState);
164
void SCU_AHBPeriphReset(u32 AHBPeriph, FunctionalState NewState);
165
void SCU_APBPeriphIdleConfig(u32 APBPeriph, FunctionalState NewState);
166
void SCU_AHBPeriphIdleConfig(u32 AHBPeriph, FunctionalState NewState);
167
void SCU_APBPeriphDebugConfig(u32 APBPeriph, FunctionalState NewState);
168
void SCU_AHBPeriphDebugConfig(u32 AHBPeriph, FunctionalState NewState);
169
void SCU_BRCLKDivisorConfig(u32 BRCLK_Divisor);
196 killagreg 170
void SCU_TIMExtCLKCmd (u8 TIMx, FunctionalState NewState);
1 ingob 171
void SCU_USBCLKConfig(u32 USBCLK_Source);
172
void SCU_PHYCLKConfig(FunctionalState NewState);
173
void SCU_FMICLKDivisorConfig(u32 FMICLK_Divisor);
174
void SCU_EMIBCLKDivisorConfig(u32 SCU_EMIBCLK);
175
void SCU_EMIModeConfig(u32 SCU_EMIMODE);
176
void SCU_EMIALEConfig(u32 SCU_EMIALE_LEN, u32 SCU_EMIALE_POL);
177
void SCU_ITConfig(u32 SCU_IT, FunctionalState NewState);
178
FlagStatus SCU_GetFlagStatus(u32 SCU_Flag);
179
void SCU_ClearFlag(u32 SCU_Flag);
180
u32 SCU_GetPLLFreqValue(void);
181
u32 SCU_GetMCLKFreqValue(void);
182
u32 SCU_GetRCLKFreqValue(void);
183
u32 SCU_GetHCLKFreqValue(void);
184
u32 SCU_GetPCLKFreqValue(void);
185
void SCU_WakeUpLineConfig(u8 EXTint);
186
void SCU_SpecIntRunModeConfig(FunctionalState NewState);
187
void SCU_EnterIdleMode(void);
188
void SCU_EnterSleepMode(void);
189
void SCU_UARTIrDASelect(u8 SCU_UARTx, u8 UART_IrDA_Mode);
190
void SCU_PFQBCCmd(FunctionalState NewState);
196 killagreg 191
void SCU_EMIByte_Select_Pinconfig(FunctionalState NewState);
192
void SCU_EMIclock_Pinconfig(FunctionalState NewState);
1 ingob 193
 
194
#endif /*__91x_SCU_H*/
195
 
196 killagreg 196
/******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/