WebSVN - BL-Ctrl - Blame - Rev 116 - /branches/V0.41-Hexa/uart.lst

Rev	Author	Line No.	Line
116	-	1	1 .file "uart.c"
		2	2 __SREG__ = 0x3f
		3	3 __SP_H__ = 0x3e
		4	4 __SP_L__ = 0x3d
		5	5 __CCP__ = 0x34
		6	6 __tmp_reg__ = 0
		7	7 __zero_reg__ = 1
		8	15 .Ltext0:
		9	16 .global __vector_13
		10	18 __vector_13:
		11	19 .LFB3:
		12	20 .LM1:
		13	21 0000 1F92 push __zero_reg__
		14	22 0002 0F92 push r0
		15	23 0004 0FB6 in r0,__SREG__
		16	24 0006 0F92 push r0
		17	25 0008 1124 clr __zero_reg__
		18	26 /* prologue: Signal */
		19	27 /* frame size = 0 */
		20	28 /* epilogue start */
		21	29 .LM2:
		22	30 000a 0F90 pop r0
		23	31 000c 0FBE out __SREG__,r0
		24	32 000e 0F90 pop r0
		25	33 0010 1F90 pop __zero_reg__
		26	34 0012 1895 reti
		27	35 .LFE3:
		28	37 .global SendUart
		29	39 SendUart:
		30	40 .LFB4:
		31	41 .LM3:
		32	42 /* prologue: function */
		33	43 /* frame size = 0 */
		34	44 .LM4:
		35	45 0014 5E9B sbis 43-32,6
		36	46 0016 00C0 rjmp .L8
		37	47 .LM5:
		38	48 0018 8091 0000 lds r24,UebertragungAbgeschlossen
		39	49 001c 8823 tst r24
		40	50 001e 01F4 brne .L5
		41	51 .LM6:
		42	52 0020 8091 0000 lds r24,ptr.1846
		43	53 0024 9091 0000 lds r25,(ptr.1846)+1
		44	54 0028 0196 adiw r24,1
		45	55 002a 9093 0000 sts (ptr.1846)+1,r25
		46	56 002e 8093 0000 sts ptr.1846,r24
		47	57 .LM7:
		48	58 0032 FC01 movw r30,r24
		49	59 0034 E050 subi r30,lo8(-(SendeBuffer))
		50	60 0036 F040 sbci r31,hi8(-(SendeBuffer))
		51	61 0038 E081 ld r30,Z
		52	62 .LVL0:
		53	63 .LM8:
		54	64 003a ED30 cpi r30,lo8(13)
		55	65 003c 01F0 breq .L6
		56	66 003e 8436 cpi r24,100
		57	67 0040 9105 cpc r25,__zero_reg__
		58	68 0042 01F4 brne .L7
		59	69 .L6:
		60	70 .LM9:
		61	71 0044 1092 0000 sts (ptr.1846)+1,__zero_reg__
		62	72 0048 1092 0000 sts ptr.1846,__zero_reg__
		63	73 .LM10:
		64	74 004c 81E0 ldi r24,lo8(1)
		65	75 004e 8093 0000 sts UebertragungAbgeschlossen,r24
		66	76 .L7:
		67	77 .LM11:
		68	78 0052 589A sbi 43-32,0
		69	79 .LM12:
		70	80 0054 ECB9 out 44-32,r30
		71	81 0056 0895 ret
		72	82 .LVL1:
		73	83 .L5:
		74	84 .LM13:
		75	85 0058 1092 0000 sts (ptr.1846)+1,__zero_reg__
		76	86 005c 1092 0000 sts ptr.1846,__zero_reg__
		77	87 .L8:
		78	88 0060 0895 ret
		79	89 .LFE4:
		80	91 .global Decode64
		81	93 Decode64:
		82	94 .LFB5:
		83	95 .LM14:
		84	96 .LVL2:
		85	97 0062 1F93 push r17
		86	98 0064 CF93 push r28
		87	99 0066 DF93 push r29
		88	100 /* prologue: function */
		89	101 /* frame size = 0 */
		90	102 0068 EC01 movw r28,r24
		91	103 .LM15:
		92	104 006a 70E0 ldi r23,lo8(0)
		93	105 .LVL3:
		94	106 .LM16:
		95	107 006c A22F mov r26,r18
		96	108 006e B0E0 ldi r27,lo8(0)
		97	109 0070 1197 sbiw r26,1
		98	110 0072 00C0 rjmp .L10
		99	111 .LVL4:
		100	112 .L12:
		101	113 .LM17:
		102	114 0074 E42F mov r30,r20
		103	115 0076 F0E0 ldi r31,lo8(0)
		104	116 0078 E050 subi r30,lo8(-(RxdBuffer))
		105	117 007a F040 sbci r31,hi8(-(RxdBuffer))
		106	118 007c 3081 ld r19,Z
		107	119 .LM18:
		108	120 007e 4F5F subi r20,lo8(-(1))
		109	121 0080 E42F mov r30,r20
		110	122 0082 F0E0 ldi r31,lo8(0)
		111	123 0084 E050 subi r30,lo8(-(RxdBuffer))
		112	124 0086 F040 sbci r31,hi8(-(RxdBuffer))
		113	125 0088 5081 ld r21,Z
		114	126 .LVL5:
		115	127 .LM19:
		116	128 008a 4F5F subi r20,lo8(-(1))
		117	129 008c E42F mov r30,r20
		118	130 008e F0E0 ldi r31,lo8(0)
		119	131 0090 E050 subi r30,lo8(-(RxdBuffer))
		120	132 0092 F040 sbci r31,hi8(-(RxdBuffer))
		121	133 0094 1081 ld r17,Z
		122	134 .LM20:
		123	135 0096 4F5F subi r20,lo8(-(1))
		124	136 0098 E42F mov r30,r20
		125	137 009a F0E0 ldi r31,lo8(0)
		126	138 009c E050 subi r30,lo8(-(RxdBuffer))
		127	139 009e F040 sbci r31,hi8(-(RxdBuffer))
		128	140 00a0 2081 ld r18,Z
		129	141 .LVL6:
		130	142 00a2 4F5F subi r20,lo8(-(1))
		131	143 .LM21:
		132	144 00a4 842F mov r24,r20
		133	145 00a6 90E0 ldi r25,lo8(0)
		134	146 .LVL7:
		135	147 00a8 8A17 cp r24,r26
		136	148 00aa 9B07 cpc r25,r27
		137	149 00ac 04F4 brge .L13
		138	150 .LVL8:
		139	151 .LM22:
		140	152 00ae 5D53 subi r21,lo8(-(-61))
		141	153 .LVL9:
		142	154 .LM23:
		143	155 00b0 FE01 movw r30,r28
		144	156 00b2 E70F add r30,r23
		145	157 00b4 F11D adc r31,__zero_reg__
		146	158 00b6 852F mov r24,r21
		147	159 .LVL10:
		148	160 00b8 8295 swap r24
		149	161 00ba 8F70 andi r24,lo8(15)
		150	162 00bc 3D53 subi r19,lo8(-(-61))
		151	163 00be 330F lsl r19
		152	164 00c0 330F lsl r19
		153	165 00c2 382B or r19,r24
		154	166 00c4 3083 st Z,r19
		155	167 .LM24:
		156	168 00c6 6130 cpi r22,lo8(1)
		157	169 00c8 01F0 breq .L13
		158	170 .LM25:
		159	171 00ca 912F mov r25,r17
		160	172 .LVL11:
		161	173 00cc 9D53 subi r25,lo8(-(-61))
		162	174 .LM26:
		163	175 00ce 7F5F subi r23,lo8(-(1))
		164	176 00d0 FE01 movw r30,r28
		165	177 00d2 E70F add r30,r23
		166	178 00d4 F11D adc r31,__zero_reg__
		167	179 00d6 7150 subi r23,lo8(-(-1))
		168	180 00d8 5295 swap r21
		169	181 00da 507F andi r21,lo8(-16)
		170	182 00dc 892F mov r24,r25
		171	183 00de 8695 lsr r24
		172	184 00e0 8695 lsr r24
		173	185 00e2 582B or r21,r24
		174	186 00e4 5083 st Z,r21
		175	187 .LM27:
		176	188 00e6 6230 cpi r22,lo8(2)
		177	189 00e8 01F0 breq .L13
		178	190 00ea 6350 subi r22,lo8(-(-3))
		179	191 .LVL12:
		180	192 00ec 7E5F subi r23,lo8(-(2))
		181	193 00ee FE01 movw r30,r28
		182	194 00f0 E70F add r30,r23
		183	195 00f2 F11D adc r31,__zero_reg__
		184	196 00f4 9295 swap r25
		185	197 00f6 990F lsl r25
		186	198 00f8 990F lsl r25
		187	199 00fa 907C andi r25,lo8(-64)
		188	200 00fc 2D53 subi r18,lo8(-(-61))
		189	201 00fe 922B or r25,r18
		190	202 0100 9083 st Z,r25
		191	203 0102 7F5F subi r23,lo8(-(1))
		192	204 .LVL13:
		193	205 .L10:
		194	206 .LM28:
		195	207 0104 6623 tst r22
		196	208 0106 01F0 breq .+2
		197	209 0108 00C0 rjmp .L12
		198	210 .LVL14:
		199	211 .L13:
		200	212 /* epilogue start */
		201	213 .LM29:
		202	214 010a DF91 pop r29
		203	215 010c CF91 pop r28
		204	216 .LVL15:
		205	217 010e 1F91 pop r17
		206	218 0110 0895 ret
		207	219 .LFE5:
		208	221 .global AddCRC
		209	223 AddCRC:
		210	224 .LFB7:
		211	225 .LM30:
		212	226 .LVL16:
		213	227 /* prologue: function */
		214	228 /* frame size = 0 */
		215	229 0112 DC01 movw r26,r24
		216	230 .LM31:
		217	231 0114 20E0 ldi r18,lo8(0)
		218	232 0116 30E0 ldi r19,hi8(0)
		219	233 .LVL17:
		220	234 0118 40E0 ldi r20,lo8(0)
		221	235 011a 50E0 ldi r21,hi8(0)
		222	236 .LVL18:
		223	237 011c 00C0 rjmp .L15
		224	238 .LVL19:
		225	239 .L16:
		226	240 .LM32:
		227	241 011e FA01 movw r30,r20
		228	242 0120 E050 subi r30,lo8(-(SendeBuffer))
		229	243 0122 F040 sbci r31,hi8(-(SendeBuffer))
		230	244 0124 8081 ld r24,Z
		231	245 0126 280F add r18,r24
		232	246 0128 311D adc r19,__zero_reg__
		233	247 .LM33:
		234	248 012a 4F5F subi r20,lo8(-(1))
		235	249 012c 5F4F sbci r21,hi8(-(1))
		236	250 .LVL20:
		237	251 .L15:
		238	252 012e 4A17 cp r20,r26
		239	253 0130 5B07 cpc r21,r27
		240	254 0132 00F0 brlo .L16
		241	255 .LM34:
		242	256 0134 3F70 andi r19,hi8(4095)
		243	257 .LVL21:
		244	258 .LM35:
		245	259 0136 C901 movw r24,r18
		246	260 0138 36E0 ldi r19,6
		247	261 013a 9695 1: lsr r25
		248	262 013c 8795 ror r24
		249	263 013e 3A95 dec r19
		250	264 0140 01F4 brne 1b
		251	265 0142 835C subi r24,lo8(-(61))
		252	266 0144 FD01 movw r30,r26
		253	267 0146 E050 subi r30,lo8(-(SendeBuffer))
		254	268 0148 F040 sbci r31,hi8(-(SendeBuffer))
		255	269 014a 8083 st Z,r24
		256	270 014c 1196 adiw r26,1
		257	271 .LVL22:
		258	272 .LM36:
		259	273 014e 2F73 andi r18,lo8(63)
		260	274 .LVL23:
		261	275 0150 235C subi r18,lo8(-(61))
		262	276 0152 FD01 movw r30,r26
		263	277 0154 E050 subi r30,lo8(-(SendeBuffer))
		264	278 0156 F040 sbci r31,hi8(-(SendeBuffer))
		265	279 0158 2083 st Z,r18
		266	280 .LM37:
		267	281 015a A050 subi r26,lo8(-(SendeBuffer+1))
		268	282 015c B040 sbci r27,hi8(-(SendeBuffer+1))
		269	283 015e 8DE0 ldi r24,lo8(13)
		270	284 0160 8C93 st X,r24
		271	285 .LM38:
		272	286 0162 1092 0000 sts UebertragungAbgeschlossen,__zero_reg__
		273	287 .LM39:
		274	288 0166 8091 0000 lds r24,SendeBuffer
		275	289 016a 8CB9 out 44-32,r24
		276	290 /* epilogue start */
		277	291 .LM40:
		278	292 016c 0895 ret
		279	293 .LFE7:
		280	295 .global SendOutData
		281	297 SendOutData:
		282	298 .LFB8:
		283	299 .LM41:
		284	300 .LVL24:
		285	301 016e CF93 push r28
		286	302 0170 DF93 push r29
		287	303 /* prologue: function */
		288	304 /* frame size = 0 */
		289	305 0172 EA01 movw r28,r20
		290	306 0174 B22F mov r27,r18
		291	307 .LM42:
		292	308 0176 93E2 ldi r25,lo8(35)
		293	309 0178 9093 0000 sts SendeBuffer,r25
		294	310 .LM43:
		295	311 017c 6093 0000 sts SendeBuffer+1,r22
		296	312 .LM44:
		297	313 0180 8093 0000 sts SendeBuffer+2,r24
		298	314 0184 63E0 ldi r22,lo8(3)
		299	315 0186 70E0 ldi r23,hi8(3)
		300	316 .LVL25:
		301	317 0188 A0E0 ldi r26,lo8(0)
		302	318 .LVL26:
		303	319 018a 00C0 rjmp .L19
		304	320 .LVL27:
		305	321 .L23:
		306	322 .LM45:
		307	323 018c FE01 movw r30,r28
		308	324 018e EA0F add r30,r26
		309	325 0190 F11D adc r31,__zero_reg__
		310	326 0192 9081 ld r25,Z
		311	327 .LVL28:
		312	328 0194 AF5F subi r26,lo8(-(1))
		313	329 0196 B150 subi r27,lo8(-(-1))
		314	330 .LM46:
		315	331 0198 01F4 brne .L20
		316	332 019a 30E0 ldi r19,lo8(0)
		317	333 019c 40E0 ldi r20,lo8(0)
		318	334 .LVL29:
		319	335 019e 00C0 rjmp .L21
		320	336 .LVL30:
		321	337 .L20:
		322	338 01a0 FE01 movw r30,r28
		323	339 01a2 EA0F add r30,r26
		324	340 01a4 F11D adc r31,__zero_reg__
		325	341 01a6 4081 ld r20,Z
		326	342 .LVL31:
		327	343 01a8 AF5F subi r26,lo8(-(1))
		328	344 01aa B150 subi r27,lo8(-(-1))
		329	345 .LM47:
		330	346 01ac 01F4 brne .L22
		331	347 01ae 30E0 ldi r19,lo8(0)
		332	348 01b0 00C0 rjmp .L21
		333	349 .L22:
		334	350 01b2 FE01 movw r30,r28
		335	351 01b4 EA0F add r30,r26
		336	352 01b6 F11D adc r31,__zero_reg__
		337	353 01b8 3081 ld r19,Z
		338	354 01ba AF5F subi r26,lo8(-(1))
		339	355 01bc B150 subi r27,lo8(-(-1))
		340	356 .L21:
		341	357 .LM48:
		342	358 01be 892F mov r24,r25
		343	359 .LVL32:
		344	360 01c0 8695 lsr r24
		345	361 01c2 8695 lsr r24
		346	362 01c4 835C subi r24,lo8(-(61))
		347	363 01c6 FB01 movw r30,r22
		348	364 01c8 E050 subi r30,lo8(-(SendeBuffer))
		349	365 01ca F040 sbci r31,hi8(-(SendeBuffer))
		350	366 01cc 8083 st Z,r24
		351	367 .LM49:
		352	368 01ce 242F mov r18,r20
		353	369 01d0 2295 swap r18
		354	370 01d2 2F70 andi r18,lo8(15)
		355	371 01d4 892F mov r24,r25
		356	372 01d6 90E0 ldi r25,lo8(0)
		357	373 .LVL33:
		358	374 01d8 8370 andi r24,lo8(3)
		359	375 01da 9070 andi r25,hi8(3)
		360	376 .LVL34:
		361	377 01dc 54E0 ldi r21,4
		362	378 01de 880F 1: lsl r24
		363	379 01e0 991F rol r25
		364	380 01e2 5A95 dec r21
		365	381 01e4 01F4 brne 1b
		366	382 .LVL35:
		367	383 01e6 282B or r18,r24
		368	384 01e8 235C subi r18,lo8(-(61))
		369	385 01ea FB01 movw r30,r22
		370	386 01ec E050 subi r30,lo8(-(SendeBuffer+1))
		371	387 01ee F040 sbci r31,hi8(-(SendeBuffer+1))
		372	388 01f0 2083 st Z,r18
		373	389 .LM50:
		374	390 01f2 842F mov r24,r20
		375	391 .LVL36:
		376	392 01f4 90E0 ldi r25,lo8(0)
		377	393 .LVL37:
		378	394 01f6 8F70 andi r24,lo8(15)
		379	395 01f8 9070 andi r25,hi8(15)
		380	396 .LVL38:
		381	397 01fa 880F lsl r24
		382	398 01fc 991F rol r25
		383	399 01fe 880F lsl r24
		384	400 0200 991F rol r25
		385	401 .LVL39:
		386	402 0202 232F mov r18,r19
		387	403 0204 2295 swap r18
		388	404 0206 2695 lsr r18
		389	405 0208 2695 lsr r18
		390	406 020a 2370 andi r18,lo8(3)
		391	407 020c 282B or r18,r24
		392	408 020e 235C subi r18,lo8(-(61))
		393	409 0210 FB01 movw r30,r22
		394	410 0212 E050 subi r30,lo8(-(SendeBuffer+2))
		395	411 0214 F040 sbci r31,hi8(-(SendeBuffer+2))
		396	412 0216 2083 st Z,r18
		397	413 .LM51:
		398	414 0218 3F73 andi r19,lo8(63)
		399	415 021a 335C subi r19,lo8(-(61))
		400	416 021c FB01 movw r30,r22
		401	417 021e E050 subi r30,lo8(-(SendeBuffer+3))
		402	418 0220 F040 sbci r31,hi8(-(SendeBuffer+3))
		403	419 0222 3083 st Z,r19
		404	420 0224 6C5F subi r22,lo8(-(4))
		405	421 0226 7F4F sbci r23,hi8(-(4))
		406	422 .LVL40:
		407	423 .L19:
		408	424 .LM52:
		409	425 0228 BB23 tst r27
		410	426 022a 01F0 breq .+2
		411	427 022c 00C0 rjmp .L23
		412	428 .LM53:
		413	429 022e CB01 movw r24,r22
		414	430 .LVL41:
		415	431 0230 00D0 rcall AddCRC
		416	432 .LVL42:
		417	433 /* epilogue start */
		418	434 .LM54:
		419	435 0232 DF91 pop r29
		420	436 0234 CF91 pop r28
		421	437 .LVL43:
		422	438 0236 0895 ret
		423	439 .LFE8:
		424	441 .global uart_putchar
		425	443 uart_putchar:
		426	444 .LFB9:
		427	445 .LM55:
		428	446 .LVL44:
		429	447 0238 1F93 push r17
		430	448 /* prologue: function */
		431	449 /* frame size = 0 */
		432	450 023a 182F mov r17,r24
		433	451 .LM56:
		434	452 023c 8A30 cpi r24,lo8(10)
		435	453 023e 01F4 brne .L28
		436	454 .LM57:
		437	455 0240 8DE0 ldi r24,lo8(13)
		438	456 .LVL45:
		439	457 0242 00D0 rcall uart_putchar
		440	458 .LVL46:
		441	459 .L28:
		442	460 .LM58:
		443	461 0244 5D9B sbis 43-32,5
		444	462 0246 00C0 rjmp .L28
		445	463 .LM59:
		446	464 0248 1CB9 out 44-32,r17
		447	465 .LM60:
		448	466 024a 80E0 ldi r24,lo8(0)
		449	467 024c 90E0 ldi r25,hi8(0)
		450	468 /* epilogue start */
		451	469 024e 1F91 pop r17
		452	470 .LVL47:
		453	471 0250 0895 ret
		454	472 .LFE9:
		455	474 .global __vector_11
		456	476 __vector_11:
		457	477 .LFB6:
		458	478 .LM61:
		459	479 0252 1F92 push __zero_reg__
		460	480 0254 0F92 push r0
		461	481 0256 0FB6 in r0,__SREG__
		462	482 0258 0F92 push r0
		463	483 025a 1124 clr __zero_reg__
		464	484 025c 2F93 push r18
		465	485 025e 3F93 push r19
		466	486 0260 4F93 push r20
		467	487 0262 5F93 push r21
		468	488 0264 6F93 push r22
		469	489 0266 7F93 push r23
		470	490 0268 8F93 push r24
		471	491 026a 9F93 push r25
		472	492 026c AF93 push r26
		473	493 026e BF93 push r27
		474	494 0270 CF93 push r28
		475	495 0272 DF93 push r29
		476	496 0274 EF93 push r30
		477	497 0276 FF93 push r31
		478	498 /* prologue: Signal */
		479	499 /* frame size = 0 */
		480	500 .LM62:
		481	501 0278 8CB1 in r24,44-32
		482	502 027a 8093 0000 sts SioTmp,r24
		483	503 .LM63:
		484	504 027e 4091 0000 lds r20,buf_ptr.1914
		485	505 0282 4436 cpi r20,lo8(100)
		486	506 0284 00F0 brlo .L31
		487	507 0286 1092 0000 sts UartState.1915,__zero_reg__
		488	508 .L31:
		489	509 .LM64:
		490	510 028a 5091 0000 lds r21,SioTmp
		491	511 028e 5D30 cpi r21,lo8(13)
		492	512 0290 01F0 breq .+2
		493	513 0292 00C0 rjmp .L32
		494	514 0294 8091 0000 lds r24,UartState.1915
		495	515 0298 8230 cpi r24,lo8(2)
		496	516 029a 01F0 breq .+2
		497	517 029c 00C0 rjmp .L32
		498	518 .LM65:
		499	519 029e 1092 0000 sts UartState.1915,__zero_reg__
		500	520 .LM66:
		501	521 02a2 A42F mov r26,r20
		502	522 02a4 B0E0 ldi r27,lo8(0)
		503	523 02a6 FD01 movw r30,r26
		504	524 02a8 E050 subi r30,lo8(-(RxdBuffer-2))
		505	525 02aa F040 sbci r31,hi8(-(RxdBuffer-2))
		506	526 02ac 3081 ld r19,Z
		507	527 .LM67:
		508	528 02ae ED01 movw r28,r26
		509	529 02b0 C050 subi r28,lo8(-(RxdBuffer-1))
		510	530 02b2 D040 sbci r29,hi8(-(RxdBuffer-1))
		511	531 02b4 2881 ld r18,Y
		512	532 .LM68:
		513	533 02b6 8091 0000 lds r24,crc.1911
		514	534 02ba 9091 0000 lds r25,(crc.1911)+1
		515	535 02be 831B sub r24,r19
		516	536 02c0 9109 sbc r25,__zero_reg__
		517	537 02c2 821B sub r24,r18
		518	538 02c4 9109 sbc r25,__zero_reg__
		519	539 02c6 9F70 andi r25,hi8(4095)
		520	540 02c8 9093 0000 sts (crc.1911)+1,r25
		521	541 02cc 8093 0000 sts crc.1911,r24
		522	542 .LM69:
		523	543 02d0 9C01 movw r18,r24
		524	544 02d2 66E0 ldi r22,6
		525	545 02d4 3695 1: lsr r19
		526	546 02d6 2795 ror r18
		527	547 02d8 6A95 dec r22
		528	548 02da 01F4 brne 1b
		529	549 02dc 235C subi r18,lo8(-(61))
		530	550 02de 2093 0000 sts crc1.1912,r18
		531	551 .LM70:
		532	552 02e2 982F mov r25,r24
		533	553 02e4 9F73 andi r25,lo8(63)
		534	554 02e6 935C subi r25,lo8(-(61))
		535	555 02e8 9093 0000 sts crc2.1913,r25
		536	556 .LM71:
		537	557 02ec 8081 ld r24,Z
		538	558 02ee 2817 cp r18,r24
		539	559 02f0 01F0 breq .+2
		540	560 02f2 00C0 rjmp .L42
		541	561 02f4 8881 ld r24,Y
		542	562 02f6 9817 cp r25,r24
		543	563 02f8 01F0 breq .+2
		544	564 02fa 00C0 rjmp .L42
		545	565 .LM72:
		546	566 02fc 4093 0000 sts AnzahlEmpfangsBytes,r20
		547	567 .LM73:
		548	568 0300 A050 subi r26,lo8(-(RxdBuffer))
		549	569 0302 B040 sbci r27,hi8(-(RxdBuffer))
		550	570 0304 5C93 st X,r21
		551	571 .LM74:
		552	572 0306 8091 0000 lds r24,RxdBuffer+2
		553	573 030a 8235 cpi r24,lo8(82)
		554	574 030c 01F4 brne .L34
		555	575 030e 2CE0 ldi r18,lo8(12)
		556	576 0310 88E1 ldi r24,lo8(24)
		557	577 0312 90E0 ldi r25,hi8(24)
		558	578 /* #APP */
		559	579 ; 133 "uart.c" 1
		560	580 0314 0FB6 in __tmp_reg__,__SREG__
		561	581 0316 F894 cli
		562	582 0318 A895 wdr
		563	583 031a 81BD out 33,r24
		564	584 031c 0FBE out __SREG__,__tmp_reg__
		565	585 031e 21BD out 33,r18
		566	586 ; 0 "" 2
		567	587 /* #NOAPP */
		568	588 .L34:
		569	589 .LM75:
		570	590 0320 8091 0000 lds r24,RxdBuffer+2
		571	591 0324 00D0 rcall uart_putchar
		572	592 .LM76:
		573	593 0326 8091 0000 lds r24,RxdBuffer+2
		574	594 032a 8437 cpi r24,lo8(116)
		575	595 032c 01F0 breq .+2
		576	596 032e 00C0 rjmp .L42
		577	597 .LM77:
		578	598 0330 2091 0000 lds r18,AnzahlEmpfangsBytes
		579	599 0334 80E0 ldi r24,lo8(MotorTest)
		580	600 0336 90E0 ldi r25,hi8(MotorTest)
		581	601 0338 66E0 ldi r22,lo8(6)
		582	602 033a 43E0 ldi r20,lo8(3)
		583	603 033c 00D0 rcall Decode64
		584	604 .LM78:
		585	605 033e E091 0000 lds r30,MotorAdresse
		586	606 0342 F0E0 ldi r31,lo8(0)
		587	607 0344 E050 subi r30,lo8(-(MotorTest-1))
		588	608 0346 F040 sbci r31,hi8(-(MotorTest-1))
		589	609 0348 8081 ld r24,Z
		590	610 034a 8093 0000 sts SIO_Sollwert,r24
		591	611 .LM79:
		592	612 034e 84EF ldi r24,lo8(500)
		593	613 0350 91E0 ldi r25,hi8(500)
		594	614 0352 9093 0000 sts (SIO_Timeout)+1,r25
		595	615 0356 8093 0000 sts SIO_Timeout,r24
		596	616 035a 00C0 rjmp .L42
		597	617 .L32:
		598	618 .LM80:
		599	619 035c 8091 0000 lds r24,UartState.1915
		600	620 0360 8130 cpi r24,lo8(1)
		601	621 0362 01F0 breq .L37
		602	622 0364 8130 cpi r24,lo8(1)
		603	623 0366 00F0 brlo .L36
		604	624 0368 8230 cpi r24,lo8(2)
		605	625 036a 01F0 breq .+2
		606	626 036c 00C0 rjmp .L43
		607	627 036e 00C0 rjmp .L45
		608	628 .L36:
		609	629 .LM81:
		610	630 0370 8091 0000 lds r24,SioTmp
		611	631 0374 8332 cpi r24,lo8(35)
		612	632 0376 01F4 brne .L39
		613	633 0378 8091 0000 lds r24,NeuerDatensatzEmpfangen
		614	634 037c 8823 tst r24
		615	635 037e 01F4 brne .L39
		616	636 0380 81E0 ldi r24,lo8(1)
		617	637 0382 8093 0000 sts UartState.1915,r24
		618	638 .L39:
		619	639 .LM82:
		620	640 0386 8091 0000 lds r24,SioTmp
		621	641 038a 8093 0000 sts RxdBuffer,r24
		622	642 038e 81E0 ldi r24,lo8(1)
		623	643 0390 8093 0000 sts buf_ptr.1914,r24
		624	644 .LM83:
		625	645 0394 8091 0000 lds r24,SioTmp
		626	646 0398 8093 0000 sts crc.1911,r24
		627	647 039c 1092 0000 sts crc.1911+1,__zero_reg__
		628	648 03a0 00C0 rjmp .L42
		629	649 .L37:
		630	650 .LM84:
		631	651 03a2 82E0 ldi r24,lo8(2)
		632	652 03a4 8093 0000 sts UartState.1915,r24
		633	653 .LM85:
		634	654 03a8 E42F mov r30,r20
		635	655 03aa F0E0 ldi r31,lo8(0)
		636	656 03ac 8091 0000 lds r24,SioTmp
		637	657 03b0 E050 subi r30,lo8(-(RxdBuffer))
		638	658 03b2 F040 sbci r31,hi8(-(RxdBuffer))
		639	659 03b4 8083 st Z,r24
		640	660 03b6 00C0 rjmp .L44
		641	661 .L45:
		642	662 .LM86:
		643	663 03b8 E42F mov r30,r20
		644	664 03ba F0E0 ldi r31,lo8(0)
		645	665 03bc 8091 0000 lds r24,SioTmp
		646	666 03c0 E050 subi r30,lo8(-(RxdBuffer))
		647	667 03c2 F040 sbci r31,hi8(-(RxdBuffer))
		648	668 03c4 8083 st Z,r24
		649	669 .LM87:
		650	670 03c6 4436 cpi r20,lo8(100)
		651	671 03c8 00F4 brsh .L40
		652	672 .L44:
		653	673 03ca 4F5F subi r20,lo8(-(1))
		654	674 03cc 4093 0000 sts buf_ptr.1914,r20
		655	675 03d0 00C0 rjmp .L41
		656	676 .L40:
		657	677 .LM88:
		658	678 03d2 1092 0000 sts UartState.1915,__zero_reg__
		659	679 .L41:
		660	680 .LM89:
		661	681 03d6 2091 0000 lds r18,SioTmp
		662	682 03da 8091 0000 lds r24,crc.1911
		663	683 03de 9091 0000 lds r25,(crc.1911)+1
		664	684 03e2 820F add r24,r18
		665	685 03e4 911D adc r25,__zero_reg__
		666	686 03e6 9093 0000 sts (crc.1911)+1,r25
		667	687 03ea 8093 0000 sts crc.1911,r24
		668	688 03ee 00C0 rjmp .L42
		669	689 .L43:
		670	690 .LM90:
		671	691 03f0 1092 0000 sts UartState.1915,__zero_reg__
		672	692 .L42:
		673	693 /* epilogue start */
		674	694 .LM91:
		675	695 03f4 FF91 pop r31
		676	696 03f6 EF91 pop r30
		677	697 03f8 DF91 pop r29
		678	698 03fa CF91 pop r28
		679	699 03fc BF91 pop r27
		680	700 03fe AF91 pop r26
		681	701 0400 9F91 pop r25
		682	702 0402 8F91 pop r24
		683	703 0404 7F91 pop r23
		684	704 0406 6F91 pop r22
		685	705 0408 5F91 pop r21
		686	706 040a 4F91 pop r20
		687	707 040c 3F91 pop r19
		688	708 040e 2F91 pop r18
		689	709 0410 0F90 pop r0
		690	710 0412 0FBE out __SREG__,r0
		691	711 0414 0F90 pop r0
		692	712 0416 1F90 pop __zero_reg__
		693	713 0418 1895 reti
		694	714 .LFE6:
		695	716 .global WriteProgramData
		696	718 WriteProgramData:
		697	719 .LFB10:
		698	720 .LM92:
		699	721 .LVL48:
		700	722 /* prologue: function */
		701	723 /* frame size = 0 */
		702	724 /* epilogue start */
		703	725 .LM93:
		704	726 041a 0895 ret
		705	727 .LFE10:
		706	729 .global DatenUebertragung
		707	731 DatenUebertragung:
		708	732 .LFB12:
		709	733 .LM94:
		710	734 /* prologue: function */
		711	735 /* frame size = 0 */
		712	736 .LM95:
		713	737 041c 8091 0000 lds r24,Debug_Timer
		714	738 0420 9091 0000 lds r25,(Debug_Timer)+1
		715	739 0424 00D0 rcall CheckDelay
		716	740 0426 8823 tst r24
		717	741 0428 01F0 breq .L50
		718	742 042a 8091 0000 lds r24,UebertragungAbgeschlossen
		719	743 042e 8823 tst r24
		720	744 0430 01F0 breq .L50
		721	745 .LM96:
		722	746 0432 84E4 ldi r24,lo8(68)
		723	747 0434 6091 0000 lds r22,MeineSlaveAdresse
		724	748 0438 40E0 ldi r20,lo8(DebugOut)
		725	749 043a 50E0 ldi r21,hi8(DebugOut)
		726	750 043c 22E1 ldi r18,lo8(18)
		727	751 043e 00D0 rcall SendOutData
		728	752 .LM97:
		729	753 0440 82E3 ldi r24,lo8(50)
		730	754 0442 90E0 ldi r25,hi8(50)
		731	755 0444 00D0 rcall SetDelay
		732	756 0446 9093 0000 sts (Debug_Timer)+1,r25
		733	757 044a 8093 0000 sts Debug_Timer,r24
		734	758 .L50:
		735	759 044e 0895 ret
		736	760 .LFE12:
		737	762 .global UART_Init
		738	764 UART_Init:
		739	765 .LFB11:
		740	766 .LM98:
		741	767 /* prologue: function */
		742	768 /* frame size = 0 */
		743	769 .LM99:
		744	770 0450 88E1 ldi r24,lo8(24)
		745	771 0452 8AB9 out 42-32,r24
		746	772 .LM100:
		747	773 0454 599A sbi 43-32,1
		748	774 .LM101:
		749	775 0456 579A sbi 42-32,7
		750	776 .LM102:
		751	777 0458 80E1 ldi r24,lo8(16)
		752	778 045a 89B9 out 41-32,r24
		753	779 .LM103:
		754	780 045c 80E0 ldi r24,lo8(gs(uart_putchar))
		755	781 045e 90E0 ldi r25,hi8(gs(uart_putchar))
		756	782 0460 60E0 ldi r22,lo8(0)
		757	783 0462 70E0 ldi r23,hi8(0)
		758	784 0464 00D0 rcall fdevopen
		759	785 .LM104:
		760	786 0466 88EC ldi r24,lo8(200)
		761	787 0468 90E0 ldi r25,hi8(200)
		762	788 046a 00D0 rcall SetDelay
		763	789 046c 9093 0000 sts (Debug_Timer)+1,r25
		764	790 0470 8093 0000 sts Debug_Timer,r24
		765	791 .LM105:
		766	792 0474 8AE0 ldi r24,lo8(10)
		767	793 0476 00D0 rcall uart_putchar
		768	794 0478 82E4 ldi r24,lo8(66)
		769	795 047a 00D0 rcall uart_putchar
		770	796 047c 8CE4 ldi r24,lo8(76)
		771	797 047e 00D0 rcall uart_putchar
		772	798 0480 8AE3 ldi r24,lo8(58)
		773	799 0482 00D0 rcall uart_putchar
		774	800 .LM106:
		775	801 0484 86E5 ldi r24,lo8(86)
		776	802 0486 00D0 rcall uart_putchar
		777	803 0488 80E3 ldi r24,lo8(48)
		778	804 048a 00D0 rcall uart_putchar
		779	805 048c 8EE2 ldi r24,lo8(46)
		780	806 048e 00D0 rcall uart_putchar
		781	807 0490 84E3 ldi r24,lo8(52)
		782	808 0492 00D0 rcall uart_putchar
		783	809 0494 81E3 ldi r24,lo8(49)
		784	810 0496 00D0 rcall uart_putchar
		785	811 .LM107:
		786	812 0498 8AE0 ldi r24,lo8(10)
		787	813 049a 00D0 rcall uart_putchar
		788	814 049c 88E4 ldi r24,lo8(72)
		789	815 049e 00D0 rcall uart_putchar
		790	816 04a0 87E5 ldi r24,lo8(87)
		791	817 04a2 00D0 rcall uart_putchar
		792	818 04a4 8AE3 ldi r24,lo8(58)
		793	819 04a6 00D0 rcall uart_putchar
		794	820 04a8 81E3 ldi r24,lo8(49)
		795	821 04aa 00D0 rcall uart_putchar
		796	822 04ac 8EE2 ldi r24,lo8(46)
		797	823 04ae 00D0 rcall uart_putchar
		798	824 04b0 8091 0000 lds r24,HwVersion
		799	825 04b4 8A5D subi r24,lo8(-(38))
		800	826 04b6 00D0 rcall uart_putchar
		801	827 .LM108:
		802	828 04b8 8AE0 ldi r24,lo8(10)
		803	829 04ba 00D0 rcall uart_putchar
		804	830 04bc 81E4 ldi r24,lo8(65)
		805	831 04be 00D0 rcall uart_putchar
		806	832 04c0 84E4 ldi r24,lo8(68)
		807	833 04c2 00D0 rcall uart_putchar
		808	834 04c4 82E5 ldi r24,lo8(82)
		809	835 04c6 00D0 rcall uart_putchar
		810	836 04c8 8AE3 ldi r24,lo8(58)
		811	837 04ca 00D0 rcall uart_putchar
		812	838 04cc 8091 0000 lds r24,MotorAdresse
		813	839 04d0 805D subi r24,lo8(-(48))
		814	840 04d2 00D0 rcall uart_putchar
		815	841 /* epilogue start */
		816	842 .LM109:
		817	843 04d4 0895 ret
		818	844 .LFE11:
		819	846 .global SIO_Sollwert
		820	847 .global SIO_Sollwert
		821	848 .section .bss
		822	851 SIO_Sollwert:
		823	852 0000 00 .skip 1,0
		824	853 .global SioTmp
		825	854 .global SioTmp
		826	857 SioTmp:
		827	858 0001 00 .skip 1,0
		828	859 .global NeuerDatensatzEmpfangen
		829	860 .global NeuerDatensatzEmpfangen
		830	863 NeuerDatensatzEmpfangen:
		831	864 0002 00 .skip 1,0
		832	865 .global UebertragungAbgeschlossen
		833	866 .data
		834	869 UebertragungAbgeschlossen:
		835	870 0000 01 .byte 1
		836	871 .global MotorTest
		837	872 .global MotorTest
		838	873 .section .bss
		839	876 MotorTest:
		840	877 0003 0000 0000 .skip 6,0
		841	877 0000
		842	878 .global AnzahlEmpfangsBytes
		843	879 .global AnzahlEmpfangsBytes
		844	882 AnzahlEmpfangsBytes:
		845	883 0009 00 .skip 1,0
		846	884 .lcomm UartState.1915,1
		847	885 .lcomm buf_ptr.1914,1
		848	886 .lcomm crc2.1913,1
		849	887 .lcomm crc1.1912,1
		850	888 .lcomm crc.1911,2
		851	889 .lcomm ptr.1846,2
		852	890 .comm MeineSlaveAdresse,1,1
		853	891 .comm Debug_Timer,2,1
		854	892 .comm DebugOut,18,1
		855	893 .comm SendeBuffer,100,1
		856	894 .comm RxdBuffer,100,1
		857	991 .Letext0:
		858	DEFINED SYMBOLS
		859	ABS:00000000 uart.c
		860	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:2 ABS:0000003f __SREG__
		861	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:3 ABS:0000003e __SP_H__
		862	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:4 ABS:0000003d __SP_L__
		863	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:5 ABS:00000034 __CCP__
		864	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:6 ABS:00000000 __tmp_reg__
		865	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:7 ABS:00000001 __zero_reg__
		866	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:18 .text:00000000 __vector_13
		867	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:39 .text:00000014 SendUart
		868	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:869 .data:00000000 UebertragungAbgeschlossen
		869	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:888 .bss:00000010 ptr.1846
		870	COM:00000064 SendeBuffer
		871	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:93 .text:00000062 Decode64
		872	COM:00000064 RxdBuffer
		873	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:223 .text:00000112 AddCRC
		874	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:297 .text:0000016e SendOutData
		875	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:443 .text:00000238 uart_putchar
		876	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:476 .text:00000252 __vector_11
		877	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:857 .bss:00000001 SioTmp
		878	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:884 .bss:0000000b buf_ptr.1914
		879	.bss:0000000a UartState.1915
		880	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:887 .bss:0000000e crc.1911
		881	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:886 .bss:0000000d crc1.1912
		882	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:885 .bss:0000000c crc2.1913
		883	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:882 .bss:00000009 AnzahlEmpfangsBytes
		884	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:876 .bss:00000003 MotorTest
		885	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:851 .bss:00000000 SIO_Sollwert
		886	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:863 .bss:00000002 NeuerDatensatzEmpfangen
		887	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:718 .text:0000041a WriteProgramData
		888	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:731 .text:0000041c DatenUebertragung
		889	COM:00000002 Debug_Timer
		890	COM:00000001 MeineSlaveAdresse
		891	COM:00000012 DebugOut
		892	C:\DOCUME~1\ADMINI~1\LOCALS~1\Temp/ccND1o1s.s:764 .text:00000450 UART_Init
		893
		894	UNDEFINED SYMBOLS
		895	MotorAdresse
		896	SIO_Timeout
		897	CheckDelay
		898	SetDelay
		899	fdevopen
		900	HwVersion
		901	__do_copy_data
		902	__do_clear_bss

Subversion Repositories BL-Ctrl

(root)/branches/V0.41-Hexa/uart.lst - Rev 116