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196 | killagreg | 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** |
1 | ingob | 2 | * File Name : 91x_dma.c |
3 | * Author : MCD Application Team |
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196 | killagreg | 4 | * Version : V2.1 |
5 | * Date : 12/22/2008 |
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6 | * Description : This file provides all the DMA firmware functions |
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1 | ingob | 7 | * needed to access all DMA registers. |
8 | ******************************************************************************** |
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9 | * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
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11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
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12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
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13 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
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14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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15 | *******************************************************************************/ |
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16 | |||
17 | /* Includes ------------------------------------------------------------------*/ |
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18 | |||
19 | # include"91x_dma.h" |
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20 | # include"91x_scu.h" |
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21 | |||
22 | /* Private typedef -----------------------------------------------------------*/ |
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23 | /* Private define ------------------------------------------------------------*/ |
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24 | /* Private macro -------------------------------------------------------------*/ |
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25 | /* Private variables ---------------------------------------------------------*/ |
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26 | |||
27 | |||
28 | /* DMA Masks "used" only in this module */ |
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29 | |||
196 | killagreg | 30 | #define DMA_Width_DES_MASK 0xFF1FFFFF |
31 | #define DMA_Width_SRC_MASK 0xFFE3FFFF |
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32 | #define DMA_Bst_DES_MASK 0xFFFC7FFF |
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1 | ingob | 33 | #define DMA_Bst_SRC_MASK 0xFFFF8FFF |
196 | killagreg | 34 | #define DMA_FlowCntrl_Mask 0xFFFFC7FF |
35 | #define DMA_TrsfSisze_Mask 0xFFFFF000 |
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1 | ingob | 36 | #define SRC_Mask 0xFFFFFFE1 |
37 | #define DES_Mask 0xFFFFFC3F |
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38 | #define DMA_TCIE 0x80000000 |
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39 | #define DMA_ChannelDESInc 0x08000000 |
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40 | #define DMA_ChannelSRCInc 0x04000000 |
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41 | #define DMA_BufferChannel 0x20000000 |
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42 | #define DMA_HaltChannel 0x00040000 |
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43 | #define DMA_LockChannel 0x00010000 |
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44 | #define DMA_CacheChannel 0x40000000 |
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45 | #define DMA_ChannelActive 0x00020000 |
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46 | #define DMA_Enable 0x00000001 |
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47 | #define DMA_ChannelEnable 0x00000001 |
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48 | |||
196 | killagreg | 49 | /*LLI Masks used for linked list's control word stucture*/ |
1 | ingob | 50 | |
196 | killagreg | 51 | #define DMA_SrcIncrement_MASK 0xFBFFFFFF |
52 | #define DMA_DesIncrement_MASK 0xF7FFFFFF |
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53 | #define DMA_CacheableAccess_MASK 0xEFFFFFFF |
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54 | #define DMA_BufferableAccess_MASK 0xDFFFFFFF |
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55 | #define DMA_PrivilegedAccess_MASK 0xBFFFFFFF |
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56 | #define DMA_TCInterrupt_MASK 0x7FFFFFFF |
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57 | |||
1 | ingob | 58 | |
59 | |||
60 | /* Private function prototypes -----------------------------------------------*/ |
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61 | /* Private functions ---------------------------------------------------------*/ |
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62 | |||
63 | /******************************************************************************* |
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64 | * Function Name : DMA_ITMaskConfig |
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65 | * Description : Enables or disables the specified DMA_Channelx Mask interrupt. |
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66 | * Input : |
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67 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
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68 | * -DMA_ITMask: specifies the DMA interrupt mask source to be enabled or disabled. |
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69 | * This parameter can be: |
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70 | * - DMA_ITMask_IE (Interrupt error mask). |
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71 | * - DMA_ITMask_ITC (Terminal count interrupt mask). |
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72 | * - DMA_ITMask_ALL ( All interrupts mask) |
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73 | * |
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74 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
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75 | * This parameter can be: ENABLE or DISABLE. |
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76 | * Output : None. |
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77 | * Return : None. |
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78 | *******************************************************************************/ |
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79 | |||
80 | |||
81 | void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask , FunctionalState NewState) |
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82 | |||
83 | { |
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84 | if (NewState==ENABLE) /* Mask the Interrupt */ |
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85 | { |
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86 | DMA_Channelx-> CCNF |= DMA_ITMask ; |
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87 | } |
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88 | |||
89 | else /* Disable the Interrupt Mask*/ |
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90 | { |
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91 | DMA_Channelx-> CCNF &= ~ DMA_ITMask ; |
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92 | } |
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93 | } |
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94 | |||
95 | |||
96 | |||
97 | |||
98 | |||
99 | /******************************************************************************* |
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100 | * Function Name : DMA_ITConfig |
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101 | * Description : Enables or disables the DMA_Channelx Terminal Count interrupt. |
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102 | * Input : |
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103 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
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104 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
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105 | * This parameter can be: ENABLE or DISABLE. |
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106 | * Output : None. |
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107 | * Return : None. |
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108 | *******************************************************************************/ |
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109 | |||
110 | |||
111 | void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
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112 | |||
113 | { |
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114 | if (NewState==ENABLE) /* Enable the Terminal Count Interrupt */ |
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115 | { |
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116 | DMA_Channelx->CC |= DMA_TCIE ; |
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117 | } |
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118 | |||
119 | else /* Disable the Terminal Count Interrupt */ |
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120 | { |
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121 | DMA_Channelx-> CC &= ~ DMA_TCIE ; |
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122 | } |
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123 | } |
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124 | |||
125 | |||
126 | /******************************************************************************** |
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127 | * Function Name : DMA_SyncConfig |
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128 | * Description : Enables or disables synchronization logic for the corresponding DMA Request Signal. |
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129 | * Input : |
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130 | * -SRCReq:specifies the DMA Request Source. |
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131 | * This parameter can be: |
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132 | * -DMA_USB_RX_Mask |
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133 | * -DMA_USB_TX_Mask |
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134 | * -DMA_TIM0_Mask |
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135 | * -DMA_TIM1_Mask |
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136 | * -DMA_UART0_RX_Mask |
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137 | * -DMA_UART0_TX_Mask |
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138 | * -DMA_UART1_RX_Mask |
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139 | * -DMA_UART1_TX_Mask |
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140 | * -DMA_External_Req0_Mask |
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141 | * -DMA_External_Req1_Mask |
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142 | * -DMA_I2C0_Mask |
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143 | * -DMA_I2C1_Mask |
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144 | * -DMA_SSP0_RX_Mask |
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145 | * -DMA_SSP0_TX_Mask |
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146 | * -DMA_SSP1_RX_Mask |
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147 | * -DMA_SSP1_TX_Mask |
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148 | * |
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149 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
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150 | * This parameter can be: ENABLE or DISABLE. |
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151 | * Output : None. |
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152 | * Return : None. |
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153 | *******************************************************************************/ |
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154 | |||
155 | |||
156 | void DMA_SyncConfig(u16 SRCReq, FunctionalState NewState) |
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157 | |||
158 | { |
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159 | if (NewState==ENABLE) /* Enable the synchronization logic for the corresponding DMA Request Signal */ |
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160 | { |
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161 | |||
162 | DMA->SYNR &= ~ SRCReq ; |
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163 | |||
164 | } |
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165 | |||
166 | else /* Disable the synchronization logic for the corresponding DMA Request Signal. */ |
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167 | { |
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168 | DMA->SYNR |= SRCReq ; |
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169 | |||
170 | } |
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171 | } |
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172 | |||
173 | |||
174 | /******************************************************************************** |
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175 | * Function Name : DMA_SetSReq |
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176 | * Description : Set the DMA to generate a Single transfer request for the corresponding DMA Request Source. |
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177 | * Input : |
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178 | * -SRCReq:specifies the DMA Request Source. |
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179 | * This parameter can be: |
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180 | * -DMA_USB_RX_Mask |
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181 | * -DMA_USB_TX_Mask |
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182 | * -DMA_TIM0_Mask |
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183 | * -DMA_TIM1_Mask |
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184 | * -DMA_UART0_RX_Mask |
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185 | * -DMA_UART0_TX_Mask |
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186 | * -DMA_UART1_RX_Mask |
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187 | * -DMA_UART1_TX_Mask |
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188 | * -DMA_External_Req0_Mask |
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189 | * -DMA_External_Req1_Mask |
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190 | * -DMA_I2C0_Mask |
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191 | * -DMA_I2C1_Mask |
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192 | * -DMA_SSP0_RX_Mask |
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193 | * -DMA_SSP0_TX_Mask |
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194 | * -DMA_SSP1_RX_Mask |
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195 | * -DMA_SSP1_TX_Mask |
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196 | * |
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197 | * Output : None. |
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198 | * Return : None. |
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199 | *******************************************************************************/ |
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200 | |||
201 | |||
202 | void DMA_SetSReq(u16 SRCReq) |
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203 | |||
204 | { /* Set the DMA to generate a Single transfer request for the corresponding DMA Request Source */ |
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205 | DMA->SSRR |= SRCReq ; |
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206 | } |
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207 | |||
208 | |||
209 | |||
210 | |||
211 | /******************************************************************************** |
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212 | * Function Name : DMA_SetLSReq |
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213 | * Description : Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source. |
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214 | * Input : |
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215 | * -SRCReq:specifies the DMA Request Source. |
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216 | * This parameter can be: |
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217 | * -DMA_USB_RX_Mask |
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218 | * -DMA_USB_TX_Mask |
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219 | * -DMA_TIM0_Mask |
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220 | * -DMA_TIM1_Mask |
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221 | * -DMA_UART0_RX_Mask |
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222 | * -DMA_UART0_TX_Mask |
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223 | * -DMA_UART1_RX_Mask |
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224 | * -DMA_UART1_TX_Mask |
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225 | * -DMA_External_Req0_Mask |
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226 | * -DMA_External_Req1_Mask |
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227 | * -DMA_I2C0_Mask |
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228 | * -DMA_I2C1_Mask |
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229 | * -DMA_SSP0_RX_Mask |
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230 | * -DMA_SSP0_TX_Mask |
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231 | * -DMA_SSP1_RX_Mask |
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232 | * -DMA_SSP1_TX_Mask |
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233 | * Output : None. |
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234 | * Return : None. |
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235 | *******************************************************************************/ |
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236 | |||
237 | void DMA_SetLSReq(u16 SRCReq ) |
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238 | { /* Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source */ |
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239 | DMA->SLSRR |= SRCReq ; |
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240 | } |
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241 | |||
242 | |||
243 | /******************************************************************************** |
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244 | * Function Name : DMA_SetBReq |
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245 | * Description : Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source. |
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246 | * Input : |
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247 | * -SRCReq:specifies the DMA Request Source. |
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248 | * This parameter can be: |
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249 | * -DMA_USB_RX_Mask |
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250 | * -DMA_USB_TX_Mask |
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251 | * -DMA_TIM0_Mask |
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252 | * -DMA_TIM1_Mask |
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253 | * -DMA_UART0_RX_Mask |
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254 | * -DMA_UART0_TX_Mask |
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255 | * -DMA_UART1_RX_Mask |
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256 | * -DMA_UART1_TX_Mask |
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257 | * -DMA_External_Req0_Mask |
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258 | * -DMA_External_Req1_Mask |
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259 | * -DMA_I2C0_Mask |
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260 | * -DMA_I2C1_Mask |
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261 | * -DMA_SSP0_RX_Mask |
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262 | * -DMA_SSP0_TX_Mask |
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263 | * -DMA_SSP1_RX_Mask |
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264 | * -DMA_SSP1_TX_Mask |
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265 | * Output : None. |
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266 | * Return : None. |
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267 | *******************************************************************************/ |
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268 | |||
269 | |||
270 | void DMA_SetBReq(u16 SRCReq) |
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271 | |||
272 | { /* Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source */ |
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273 | DMA->SBRR |= SRCReq ; |
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274 | } |
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275 | |||
276 | |||
277 | |||
278 | /******************************************************************************** |
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279 | * Function Name : DMA_SetLBReq |
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280 | * Description : Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source. |
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281 | * Input : |
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282 | * -SRCReq:specifies the DMA Request Source. |
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283 | * This parameter can be: |
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284 | * -DMA_USB_RX_Mask |
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285 | * -DMA_USB_TX_Mask |
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286 | * -DMA_TIM0_Mask |
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287 | * -DMA_TIM1_Mask |
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288 | * -DMA_UART0_RX_Mask |
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289 | * -DMA_UART0_TX_Mask |
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290 | * -DMA_UART1_RX_Mask |
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291 | * -DMA_UART1_TX_Mask |
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292 | * -DMA_External_Req0_Mask |
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293 | * -DMA_External_Req1_Mask |
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294 | * -DMA_I2C0_Mask |
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295 | * -DMA_I2C1_Mask |
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296 | * -DMA_SSP0_RX_Mask |
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297 | * -DMA_SSP0_TX_Mask |
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298 | * -DMA_SSP1_RX_Mask |
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299 | * -DMA_SSP1_TX_Mask |
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300 | * Output : None. |
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301 | * Return : None. |
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302 | *******************************************************************************/ |
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303 | |||
304 | |||
305 | void DMA_SetLBReq(u16 SRCReq) |
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306 | |||
307 | { /* Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source */ |
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308 | DMA->SLBRR |= SRCReq ; |
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309 | } |
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310 | |||
311 | |||
312 | /******************************************************************************** |
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313 | * Function Name : DMA_GetSReq |
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314 | * Description : Check for a specific source if it request a Single transfer . |
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315 | * Input : |
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316 | * Input : |
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317 | * -SRCReq:specifies the DMA Request Source. |
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318 | * This parameter can be: |
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319 | * -DMA_USB_RX_Mask |
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320 | * -DMA_USB_TX_Mask |
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321 | * -DMA_TIM0_Mask |
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322 | * -DMA_TIM1_Mask |
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323 | * -DMA_UART0_RX_Mask |
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324 | * -DMA_UART0_TX_Mask |
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325 | * -DMA_UART1_RX_Mask |
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326 | * -DMA_UART1_TX_Mask |
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327 | * -DMA_External_Req0_Mask |
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328 | * -DMA_External_Req1_Mask |
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329 | * -DMA_I2C0_Mask |
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330 | * -DMA_I2C1_Mask |
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331 | * -DMA_SSP0_RX_Mask |
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332 | * -DMA_SSP0_TX_Mask |
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333 | * -DMA_SSP1_RX_Mask |
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334 | * -DMA_SSP1_TX_Mask |
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335 | * Output : None. |
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336 | * Return : SET or RESET. |
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337 | *******************************************************************************/ |
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338 | |||
339 | |||
340 | FlagStatus DMA_GetSReq(u16 SRCReq) |
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341 | |||
342 | { /* Check for a specific source if it request a Single transfer . */ |
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343 | if ( (DMA->SSRR & SRCReq )!= RESET ) |
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344 | { |
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345 | return SET; |
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346 | } |
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347 | |||
348 | else |
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349 | { |
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350 | return RESET; |
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351 | } |
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352 | } |
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353 | |||
354 | |||
355 | /******************************************************************************** |
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356 | * Function Name : DMA_GetLSReq |
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357 | * Description : Check for a specific source if it request a Last Single transfer . |
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358 | * Input : |
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359 | * -SRCReq:specifies the DMA Request Source. |
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360 | * This parameter can be: |
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361 | * -DMA_USB_RX_Mask |
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362 | * -DMA_USB_TX_Mask |
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363 | * -DMA_TIM0_Mask |
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364 | * -DMA_TIM1_Mask |
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365 | * -DMA_UART0_RX_Mask |
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366 | * -DMA_UART0_TX_Mask |
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367 | * -DMA_UART1_RX_Mask |
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368 | * -DMA_UART1_TX_Mask |
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369 | * -DMA_External_Req0_Mask |
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370 | * -DMA_External_Req1_Mask |
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371 | * -DMA_I2C0_Mask |
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372 | * -DMA_I2C1_Mask |
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373 | * -DMA_SSP0_RX_Mask |
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374 | * -DMA_SSP0_TX_Mask |
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375 | * -DMA_SSP1_RX_Mask |
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376 | * -DMA_SSP1_TX_Mask |
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377 | * Output : None. |
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378 | * Return : SET or RESET. |
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379 | *******************************************************************************/ |
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380 | |||
381 | |||
382 | FlagStatus DMA_GetLSReq(u16 SRCReq) |
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383 | |||
384 | { /* Check for a specific source if it request a Last Single transfer . */ |
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385 | if ( (DMA->SLSRR & SRCReq)!= RESET ) |
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386 | { |
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387 | return SET; |
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388 | } |
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389 | |||
390 | else |
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391 | { |
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392 | return RESET; |
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393 | } |
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394 | } |
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395 | |||
396 | /******************************************************************************** |
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397 | * Function Name : DMA_GetBReq |
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398 | * Description : Check for a specific source if it request a Burst transfer . |
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399 | * Input : |
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400 | * -SRCReq:specifies the DMA Request Source. |
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401 | * This parameter can be: |
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402 | * -DMA_USB_RX_Mask |
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403 | * -DMA_USB_TX_Mask |
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404 | * -DMA_TIM0_Mask |
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405 | * -DMA_TIM1_Mask |
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406 | * -DMA_UART0_RX_Mask |
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407 | * -DMA_UART0_TX_Mask |
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408 | * -DMA_UART1_RX_Mask |
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409 | * -DMA_UART1_TX_Mask |
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410 | * -DMA_External_Req0_Mask |
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411 | * -DMA_External_Req1_Mask |
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412 | * -DMA_I2C0_Mask |
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413 | * -DMA_I2C1_Mask |
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414 | * -DMA_SSP0_RX_Mask |
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415 | * -DMA_SSP0_TX_Mask |
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416 | * -DMA_SSP1_RX_Mask |
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417 | * -DMA_SSP1_TX_Mask |
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418 | * Output : None. |
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419 | * Return : SET or RESET. |
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420 | *******************************************************************************/ |
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421 | |||
422 | |||
423 | FlagStatus DMA_GetBReq(u16 SRCReq) |
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424 | |||
425 | { /* Check for a specific source if it request a Burst transfer . */ |
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426 | if (( DMA->SBRR & SRCReq ) != RESET ) |
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427 | { |
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428 | return SET; |
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429 | } |
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430 | |||
431 | else |
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432 | { |
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433 | return RESET; |
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434 | } |
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435 | } |
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436 | |||
437 | /******************************************************************************** |
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438 | * Function Name : DMA_GetLSReq |
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439 | * Description : Check for a specific source if it request a Last Burst transfer . |
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440 | * Input : |
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441 | * Input : |
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442 | * - SRCReq:specifies the DMA Request Source. |
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443 | * This parameter can be: |
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444 | * -DMA_USB_RX_Mask |
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445 | * -DMA_USB_TX_Mask |
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446 | * -DMA_TIM0_Mask |
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447 | * -DMA_TIM1_Mask |
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448 | * -DMA_UART0_RX_Mask |
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449 | * -DMA_UART0_TX_Mask |
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450 | * -DMA_UART1_RX_Mask |
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451 | * -DMA_UART1_TX_Mask |
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452 | * -DMA_External_Req0_Mask |
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453 | * -DMA_External_Req1_Mask |
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454 | * -DMA_I2C0_Mask |
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455 | * -DMA_I2C1_Mask |
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456 | * -DMA_SSP0_RX_Mask |
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457 | * -DMA_SSP0_TX_Mask |
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458 | * -DMA_SSP1_RX_Mask |
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459 | * -DMA_SSP1_TX_Mask |
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460 | * Output : None. |
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461 | * Return : SET or RESET. |
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462 | *******************************************************************************/ |
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463 | |||
464 | |||
465 | FlagStatus DMA_GetLBReq(u16 SRCReq) |
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466 | |||
467 | { /* Check for a specific source if it request a Last Burst transfer . */ |
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468 | if ( ( DMA->SLBRR & SRCReq ) != RESET ) |
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469 | { |
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470 | return SET; |
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471 | } |
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472 | |||
473 | else |
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474 | { |
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475 | return RESET; |
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476 | } |
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477 | } |
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478 | |||
479 | |||
480 | |||
481 | /******************************************************************************* |
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482 | * Function Name : DMA_ChannelHalt |
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483 | * Description : Enables DMA requests or ignore extra source DMA requests for |
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484 | the specified channel. |
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485 | * Input : |
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486 | -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
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487 | -NewState: new state of the specified DMA_Channelx mask interrupt. |
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488 | This parameter can be: ENABLE or DISABLE. |
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489 | * Output : None. |
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490 | * Return : None. |
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491 | *******************************************************************************/ |
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492 | |||
493 | |||
494 | void DMA_ChannelHalt(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
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495 | |||
496 | { |
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497 | if (NewState==ENABLE) /* Enables DMA requests */ |
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498 | |||
499 | { |
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500 | DMA_Channelx->CCNF |= DMA_HaltChannel ; |
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501 | } |
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502 | |||
503 | else /* Ignore extra source DMA request */ |
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504 | { |
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505 | DMA_Channelx->CCNF &= ~ DMA_HaltChannel ; |
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506 | } |
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507 | } |
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508 | |||
509 | |||
510 | /******************************************************************************* |
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511 | * Function Name : DMA_ChannelLockTrsf |
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512 | * Description : Enables or disables the Locked Transfers Feature for the specified DMA_Channelx |
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513 | * Input : |
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514 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
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515 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
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516 | * This parameter can be: ENABLE or DISABLE. |
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517 | * Output : None. |
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518 | * Return : None. |
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519 | *******************************************************************************/ |
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520 | |||
521 | |||
522 | void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
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523 | |||
524 | { |
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525 | if (NewState==ENABLE) /* Locked transfers enabled on channel x */ |
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526 | |||
527 | { |
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528 | DMA_Channelx->CCNF |= DMA_LockChannel ; |
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529 | } |
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530 | |||
531 | else /* Locked transfers disabled on channel xt */ |
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532 | { |
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533 | DMA_Channelx->CCNF &= ~ DMA_LockChannel; |
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534 | } |
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535 | } |
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536 | |||
537 | |||
538 | /******************************************************************************* |
||
539 | * Function Name : DMA_ChannelCache |
||
540 | * Description : Enables or disables the cacheability Feature for the specified DMA_Channelx |
||
541 | * Input : |
||
542 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
||
543 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
||
544 | * This parameter can be: ENABLE or DISABLE. |
||
545 | * Output : None. |
||
546 | * Return : None. |
||
547 | *******************************************************************************/ |
||
548 | |||
549 | |||
550 | void DMA_ChannelCache (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
||
551 | |||
552 | { |
||
553 | if (NewState==ENABLE) /* Cacheability Feature enabled on channelx */ |
||
554 | |||
555 | { |
||
556 | DMA_Channelx->CC |= DMA_CacheChannel ; |
||
557 | } |
||
558 | |||
559 | else /* Cacheability Feature disabled on channelx */ |
||
560 | { |
||
561 | DMA_Channelx->CC &= ~ DMA_CacheChannel ; |
||
562 | } |
||
563 | } |
||
564 | |||
565 | |||
566 | /******************************************************************************* |
||
567 | * Function Name : DMA_ChannelBuffering |
||
568 | * Description : Enables or disables the Buffering Feature for the specified DMA_Channelx |
||
569 | * Input : |
||
570 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
||
571 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
||
572 | * This parameter can be: ENABLE or DISABLE. |
||
573 | * Output : None. |
||
574 | * Return : None. |
||
575 | *******************************************************************************/ |
||
576 | |||
577 | |||
578 | void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
||
579 | |||
580 | { |
||
581 | if (NewState==ENABLE) /* Cacheability Feature enabled on channel x */ |
||
582 | |||
583 | { |
||
584 | DMA_Channelx->CC |= DMA_BufferChannel ; |
||
585 | } |
||
586 | |||
587 | else /* Cacheability Feature disabled on channel xt */ |
||
588 | { |
||
589 | DMA_Channelx->CC &= ~ DMA_BufferChannel ; |
||
590 | } |
||
591 | } |
||
592 | |||
593 | /******************************************************************************* |
||
594 | * Function Name : MA_ChannelProt0Mod |
||
595 | * Description : Sets The User or Privileged mode for the specified DMA_Channelx |
||
596 | * Input : |
||
597 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
||
598 | * -Prot0Mode: Specifies the Privileged mode Or the User mode. |
||
599 | * This parameter can be: |
||
600 | * - DMA_PrevilegedMode |
||
601 | * - DMA_UserMode |
||
602 | * |
||
603 | * |
||
604 | * Output : None. |
||
605 | * Return : None. |
||
606 | *******************************************************************************/ |
||
607 | |||
608 | |||
609 | void DMA_ChannelProt0Mode (DMA_Channel_TypeDef * DMA_Channelx, u32 Prot0Mode) |
||
610 | |||
611 | { |
||
612 | if (Prot0Mode==DMA_PrevilegedMode) /* Privileged mode */ |
||
613 | { |
||
614 | DMA_Channelx->CC |= DMA_PrevilegedMode ; |
||
615 | } |
||
616 | |||
617 | else /* User mode */ |
||
618 | { |
||
619 | DMA_Channelx->CC &= DMA_UserMode ; |
||
620 | } |
||
621 | } |
||
622 | |||
623 | |||
624 | |||
625 | |||
626 | |||
627 | /******************************************************************************* |
||
628 | * Function Name : DMA_ChannelSRCIncConfig |
||
629 | * Description : Enables or disables the Source address incrementation after each transfer for |
||
630 | * the specified DMA_Channelx |
||
631 | * Input : |
||
632 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
||
633 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
||
634 | * This parameter can be: ENABLE or DISABLE. |
||
635 | * Output : None. |
||
636 | * Return : None. |
||
637 | *******************************************************************************/ |
||
638 | |||
639 | |||
640 | void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
||
641 | |||
642 | { |
||
643 | if (NewState==ENABLE) /* The Source address is incremented after each transfer */ |
||
644 | |||
645 | { |
||
646 | DMA_Channelx->CC |= DMA_ChannelSRCInc ; |
||
647 | } |
||
648 | |||
649 | else /* The Source address is not incremented after each Transfer */ |
||
650 | { |
||
651 | DMA_Channelx->CC &= ~ DMA_ChannelSRCInc ; |
||
652 | } |
||
653 | } |
||
654 | |||
655 | |||
656 | /******************************************************************************* |
||
657 | * Function Name : DMA_ChannelDESIncConfig |
||
658 | * Description : Enables or disables the Destination address incrementation after each transfer for |
||
659 | * the specified DMA_Channelx |
||
660 | * Input : |
||
661 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
||
662 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
||
663 | * This parameter can be: ENABLE or DISABLE. |
||
664 | * Output : None. |
||
665 | * Return : None. |
||
666 | *******************************************************************************/ |
||
667 | |||
668 | |||
669 | void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState) |
||
670 | |||
671 | { |
||
672 | if (NewState==ENABLE) /* The Destination address is incremented after each transfer */ |
||
673 | |||
674 | { |
||
675 | DMA_Channelx->CC |= DMA_ChannelDESInc ; |
||
676 | } |
||
677 | |||
678 | else /* The Destination address is not incremented after each Transfer */ |
||
679 | { |
||
680 | DMA_Channelx->CC &= ~ DMA_ChannelDESInc ; |
||
681 | } |
||
682 | } |
||
683 | |||
684 | |||
685 | |||
686 | /******************************************************************************** |
||
687 | * Function Name : DMA_GetChannelStatus |
||
688 | * Description : Checks the status of DMA channelx ( Enabled or Disabled). |
||
689 | * - ChannelIndx:specifies the DMA Channel to be checked. |
||
690 | * This parameter can be: |
||
691 | * - Channel0 |
||
692 | * - Channel1 |
||
693 | * - Channel2 |
||
694 | * - Channel3 |
||
695 | * - Channel4 |
||
696 | * - Channel5 |
||
697 | * - Channel6 |
||
698 | * - Channel7 |
||
699 | * Output : None. |
||
700 | * |
||
701 | * Return : SET or RESET. |
||
702 | *******************************************************************************/ |
||
703 | |||
704 | |||
705 | FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ) |
||
706 | |||
707 | { |
||
708 | |||
709 | if ( ( DMA->ENCSR & (1 << ChannelIndx )) != RESET ) |
||
710 | { |
||
711 | return SET; /* Channelx Enabled */ |
||
712 | } |
||
713 | |||
714 | else |
||
715 | |||
716 | { |
||
717 | |||
718 | return RESET; /* Channelx Disabled */ |
||
719 | |||
720 | } |
||
721 | |||
722 | } |
||
723 | |||
724 | |||
725 | |||
726 | /******************************************************************************** |
||
727 | * Function Name : DMA_GetITStatus |
||
728 | * Description : Checks the status of Terminal Count and Error interrupts request after and before Masking. |
||
729 | * Input : |
||
730 | * - ChannelIndx:specifies the DMA Channel to be checked. |
||
731 | * This parameter can be: |
||
732 | * - Channel0 |
||
733 | * - Channel1 |
||
734 | * - Channel2 |
||
735 | * - Channel3 |
||
736 | * - Channel4 |
||
737 | * - Channel5 |
||
738 | * - Channel6 |
||
739 | * - Channel7 |
||
740 | * |
||
741 | *. - DMA_ITReq: specifies the DMA interrupt request status to be checked. |
||
742 | * This parameter can be: |
||
743 | * |
||
744 | * - DMA_IS |
||
745 | * - DMA_TCS |
||
746 | * - DMA_ES |
||
747 | * - DMA_TCRS |
||
748 | * - DMA_ERS. |
||
749 | * |
||
750 | * Output : None. |
||
751 | * |
||
752 | * Return : SET or RESET. |
||
753 | *******************************************************************************/ |
||
754 | |||
755 | |||
756 | ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq) |
||
757 | |||
758 | { |
||
759 | u32 DMAReg = 0; |
||
760 | |||
761 | switch(DMA_ITReq) |
||
762 | |||
763 | { |
||
764 | |||
765 | case (DMA_IS): /*The status of the interrupts after masking : logical or of all Interrupts after Masking*/ |
||
766 | DMAReg = DMA->ISR; |
||
767 | break; |
||
768 | |||
769 | |||
770 | |||
771 | case (DMA_TCS): /* The status of the Terminal count request after masking */ |
||
772 | DMAReg = DMA->TCISR; |
||
773 | break; |
||
774 | |||
775 | |||
776 | case (DMA_ES): /* The status of the error request after masking */ |
||
777 | DMAReg = DMA->EISR; |
||
778 | break; |
||
779 | |||
780 | |||
781 | case (DMA_TCRS): /* Indicates if the DMA channel is requesting a transfer complete (terminal count Interrupt) prior to masking or Not. */ |
||
782 | DMAReg = DMA->TCRISR; |
||
783 | break; |
||
784 | |||
785 | case (DMA_ERS): /* Indicates if the DMA channel is requesting an Error Interrupt prior to masking or Not. */ |
||
786 | DMAReg = DMA->ERISR; |
||
787 | break; |
||
788 | |||
789 | |||
790 | } |
||
791 | |||
792 | if((DMAReg &(1 << ChannelIndx )) != RESET ) |
||
793 | |||
794 | { |
||
795 | return SET; |
||
796 | } |
||
797 | |||
798 | else |
||
799 | |||
800 | { |
||
801 | |||
802 | return RESET; |
||
803 | |||
804 | |||
805 | } |
||
806 | |||
807 | } |
||
808 | |||
809 | |||
810 | /******************************************************************************** |
||
811 | * Function Name : DMA_ClearIT |
||
812 | * Description : Clears The Interrupt pending bits for termnal count or Error interrupts for a specified DMA Channel. |
||
813 | * - ChannelIndx:specifies the DMA Channel to be checked. |
||
814 | * This parameter can be: |
||
815 | * - Channel0 |
||
816 | * - Channel1 |
||
817 | * - Channel2 |
||
818 | * - Channel3 |
||
819 | * - Channel4 |
||
820 | * - Channel5 |
||
821 | * - Channel6 |
||
822 | * - Channel7 |
||
823 | * - DMA_ITClr : Specifies the DMA interrupt pending to be cleared. |
||
824 | *. This parameter can be: |
||
825 | * - DMA_TCC |
||
826 | * - DMA_EC. |
||
827 | * |
||
828 | * Output : None. |
||
829 | |||
830 | * Return : SET or RESET. |
||
831 | *******************************************************************************/ |
||
832 | |||
833 | |||
834 | void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr) |
||
835 | |||
836 | { |
||
837 | |||
838 | |||
839 | switch(DMA_ITClr) |
||
840 | |||
841 | { |
||
842 | |||
843 | case (DMA_TCC): /* Clear The status of the Terminal count interrupt on the corresponding channel.*/ |
||
844 | DMA->TCICR |=(1 << ChannelIndx ); |
||
845 | break; |
||
846 | |||
847 | |||
848 | |||
849 | case (DMA_EC): /* Clear The status of the error interrupt on the corresponding channel.*/ |
||
850 | DMA->EICR |=(1 << ChannelIndx ); |
||
851 | break; |
||
852 | |||
853 | |||
854 | |||
855 | } |
||
856 | |||
857 | |||
858 | |||
859 | } |
||
860 | |||
861 | |||
862 | /******************************************************************************* |
||
863 | * Function Name : DMA_Cmd(FunctionalState NewState) |
||
864 | * Description : Enables or disables the DMA peripheral. |
||
865 | * |
||
866 | * Input : |
||
867 | * -NewState: new state of the DMA. |
||
868 | * This parameter can be: ENABLE or DISABLE. |
||
869 | * Output : None. |
||
870 | * Return : None. |
||
871 | *******************************************************************************/ |
||
872 | |||
873 | |||
874 | void DMA_Cmd(FunctionalState NewState) |
||
875 | |||
876 | { |
||
877 | if (NewState==ENABLE) /* ENABLE the DMA peripheral */ |
||
878 | |||
879 | { |
||
880 | DMA-> CNFR |= DMA_Enable ; |
||
881 | } |
||
882 | |||
883 | else /* DISABLE the DMA peripheral */ |
||
884 | { |
||
885 | DMA-> CNFR &= ~ DMA_Enable ; |
||
886 | } |
||
887 | } |
||
888 | |||
889 | |||
890 | |||
891 | /******************************************************************************* |
||
892 | * Function Name : DMA_ChannelCmd |
||
893 | * Description : Enables or disables the specified DMA_Channelx |
||
894 | * |
||
895 | * Input : |
||
896 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
||
897 | * -NewState: new state of the specified DMA_Channelx mask interrupt. |
||
898 | * This parameter can be: ENABLE or DISABLE. |
||
899 | * Output : None. |
||
900 | * Return : None. |
||
901 | *******************************************************************************/ |
||
902 | |||
903 | |||
904 | void DMA_ChannelCmd (DMA_Channel_TypeDef *DMA_Channelx,FunctionalState NewState) |
||
905 | |||
906 | { |
||
907 | if (NewState==ENABLE) /* Enable The Channelx */ |
||
908 | |||
909 | { |
||
910 | DMA_Channelx->CCNF |= DMA_ChannelEnable ; |
||
911 | } |
||
912 | |||
913 | else /* Disable The Channelx */ |
||
914 | { |
||
915 | DMA_Channelx-> CCNF &= ~ DMA_ChannelEnable ; |
||
916 | } |
||
917 | } |
||
918 | |||
919 | |||
920 | |||
921 | /******************************************************************************** |
||
922 | * Function Name : DMA_GetChannelActiveStatus |
||
923 | * Description : Checks The DMA_Channelx FIFO if it has data or not. |
||
924 | * Input : |
||
925 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
||
926 | * |
||
927 | * |
||
928 | * Output : None. |
||
929 | * |
||
930 | * Return : SET or RESET. |
||
931 | *******************************************************************************/ |
||
932 | |||
933 | |||
934 | FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx ) |
||
935 | |||
936 | { |
||
937 | |||
938 | if ( ( DMA_Channelx->CCNF & DMA_ChannelActive) != RESET ) |
||
939 | { |
||
940 | return SET; /* The DMA_Channelx FIFO has data */ |
||
941 | } |
||
942 | |||
943 | else |
||
944 | |||
945 | { |
||
946 | |||
947 | return RESET; /* No data in the DMA_Channelx FIFO */ |
||
948 | |||
949 | |||
950 | } |
||
951 | |||
952 | } |
||
953 | |||
954 | |||
955 | /******************************************************************************** |
||
956 | * Function Name : DMA_DeInit |
||
957 | * Description : Initializes the DMA peripheral registers to their default reset values. |
||
958 | * |
||
959 | * |
||
960 | * Input : None |
||
961 | * |
||
962 | * Output : None. |
||
963 | * |
||
964 | * Called Functions: |
||
965 | * |
||
966 | * - SCU_AHBPeriphReset: Function defined in the System clock Unit "scu.c". |
||
967 | * |
||
968 | * |
||
969 | * Return : None |
||
970 | *******************************************************************************/ |
||
971 | |||
972 | |||
973 | void DMA_DeInit(void) |
||
974 | |||
975 | { |
||
976 | |||
977 | SCU_AHBPeriphReset(__DMA, ENABLE); /*DMA peripheral is under Reset " Reset on"*/ |
||
978 | SCU_AHBPeriphReset(__DMA, DISABLE); /*DMA peripheral Reset off*/ |
||
979 | } |
||
980 | |||
981 | |||
982 | |||
983 | /******************************************************************************** |
||
984 | * Function Name : DMA_StructInit |
||
985 | * Description : Fills each DMA_InitStruct member with its reset value. |
||
986 | * Input : |
||
987 | * -DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will be initialized. |
||
988 | * |
||
989 | * Output : None. |
||
990 | * |
||
991 | * Return : None |
||
992 | *******************************************************************************/ |
||
993 | |||
994 | |||
995 | void DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct) |
||
996 | |||
997 | { |
||
998 | |||
999 | /* Initialize The current source address */ |
||
1000 | DMA_InitStruct-> DMA_Channel_SrcAdd =0x0000000; |
||
1001 | |||
1002 | |||
1003 | /* Initialize The current Destination address */ |
||
1004 | DMA_InitStruct->DMA_Channel_DesAdd=0x00000000; |
||
1005 | |||
1006 | |||
1007 | |||
1008 | /* Initialize The Linked List Items */ |
||
1009 | DMA_InitStruct->DMA_Channel_LLstItm=0x00000000 ; |
||
1010 | |||
1011 | |||
1012 | |||
1013 | /* Initialize The Destination width */ |
||
1014 | DMA_InitStruct->DMA_Channel_DesWidth= DMA_DesWidth_Byte; |
||
1015 | |||
1016 | |||
1017 | |||
1018 | /* Initialize The source width */ |
||
1019 | DMA_InitStruct->DMA_Channel_SrcWidth= DMA_SrcWidth_Byte; |
||
1020 | |||
1021 | |||
1022 | /* Initialize The Burst Size for the Destination */ |
||
1023 | DMA_InitStruct->DMA_Channel_DesBstSize= DMA_DesBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the Destination width */ |
||
1024 | |||
1025 | |||
1026 | |||
1027 | /* Initialize The Burst Size for the Source*/ |
||
1028 | DMA_InitStruct->DMA_Channel_SrcBstSize= DMA_SrcBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the source width */ |
||
1029 | |||
1030 | /* Initialize The Flow control and transfer type for the DMA transfer */ |
||
1031 | DMA_InitStruct->DMA_Channel_FlowCntrl=DMA_FlowCntrlt0_DMA; /* memory to memory transfer with DMA as flow controller */ |
||
1032 | |||
1033 | |||
1034 | /* Initialize The Transfer Size */ |
||
1035 | DMA_InitStruct->DMA_Channel_TrsfSize =0x00; |
||
1036 | |||
1037 | |||
1038 | |||
1039 | /* Initialize the DMA source request peripheral :"This field is ignored if the source of the transfer is from memory" */ |
||
1040 | DMA_InitStruct->DMA_Channel_Src =0x00; |
||
1041 | |||
1042 | |||
1043 | |||
1044 | /* Initialize the DMA Destination request peripheral :"This field is ignored if the destination of the transfer is to memory.*/ |
||
1045 | |||
1046 | DMA_InitStruct->DMA_Channel_Des=0x00; |
||
1047 | |||
1048 | |||
1049 | } |
||
1050 | |||
1051 | |||
1052 | |||
1053 | |||
1054 | /******************************************************************************** |
||
1055 | * Function Name : DMA_Init |
||
1056 | * Description : Initializes the DMA_Channelx according to the specified parameters |
||
1057 | * in the DMA_InitStruct . |
||
1058 | * |
||
1059 | * Input : |
||
1060 | * -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel. |
||
1061 | * -DMA_InitStruct: pointer to a DMA_InitTypeDef structure |
||
1062 | * ( Structure Config to be load in DMA Registers). . |
||
1063 | * |
||
1064 | * Output : None. |
||
1065 | * |
||
1066 | * Return : None |
||
1067 | *******************************************************************************/ |
||
1068 | |||
1069 | |||
1070 | void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct) |
||
1071 | |||
1072 | { |
||
1073 | |||
1074 | |||
1075 | |||
1076 | /* Select the DMA source peripheral request */ |
||
1077 | DMA_Channelx->CCNF &= SRC_Mask; |
||
1078 | DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Src; |
||
1079 | |||
1080 | |||
1081 | /* Select the flow controller and the transfer type */ |
||
1082 | DMA_Channelx->CCNF &= DMA_FlowCntrl_Mask; |
||
1083 | DMA_Channelx->CCNF |=DMA_InitStruct->DMA_Channel_FlowCntrl; |
||
1084 | |||
1085 | |||
1086 | /* Select the DMA Destination peripheral request*/ |
||
1087 | DMA_Channelx->CCNF &= DES_Mask; |
||
1088 | DMA_Channelx->CCNF |= DMA_InitStruct->DMA_Channel_Des; |
||
1089 | |||
1090 | /* Set the source address */ |
||
1091 | DMA_Channelx->SRC = DMA_InitStruct-> DMA_Channel_SrcAdd ; |
||
1092 | |||
1093 | |||
1094 | /* Set the destination address */ |
||
1095 | |||
1096 | DMA_Channelx->DES = DMA_InitStruct->DMA_Channel_DesAdd ; |
||
1097 | |||
1098 | |||
1099 | |||
1100 | /* Set the linked list Items address */ |
||
1101 | DMA_Channelx->LLI = DMA_InitStruct->DMA_Channel_LLstItm ; |
||
1102 | |||
1103 | |||
1104 | /* Set The Destination width */ |
||
1105 | DMA_Channelx->CC &= DMA_Width_DES_MASK; |
||
1106 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesWidth; |
||
1107 | |||
1108 | |||
1109 | /* Set The Source width */ |
||
1110 | DMA_Channelx->CC &= DMA_Width_SRC_MASK; |
||
1111 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_SrcWidth; |
||
1112 | |||
1113 | /* Set The Burst Size for the Destination */ |
||
1114 | DMA_Channelx->CC &= DMA_Bst_DES_MASK; |
||
1115 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_DesBstSize; |
||
1116 | |||
1117 | /* Set The Burst Size for the Source */ |
||
1118 | DMA_Channelx->CC &= DMA_Bst_SRC_MASK; |
||
1119 | DMA_Channelx->CC |=DMA_InitStruct->DMA_Channel_SrcBstSize; |
||
1120 | |||
1121 | |||
1122 | /* Initialize The Transfer Size for the Source */ |
||
1123 | DMA_Channelx->CC &= DMA_TrsfSisze_Mask; |
||
1124 | DMA_Channelx->CC |= DMA_InitStruct->DMA_Channel_TrsfSize; |
||
1125 | |||
1126 | |||
1127 | } |
||
1128 | |||
1129 | |||
196 | killagreg | 1130 | /******************************************************************************** |
1131 | * Function Name : DMA_LLI_CCR_Init |
||
1132 | * Description : Return linked list's control word according to the specified |
||
1133 | * parameters in the LLI_CCR_InitStruct . |
||
1134 | * |
||
1135 | * Input : -LLI_CCR_InitStruct: pointer to a LLI_CCR_InitTypeDef structure |
||
1136 | * ( Structure Config to be load in DMA Registers). . |
||
1137 | * |
||
1138 | * Output : None. |
||
1139 | * |
||
1140 | * Return : Control word |
||
1141 | *******************************************************************************/ |
||
1142 | |||
1143 | |||
1144 | u32 DMA_LLI_CCR_Init(LLI_CCR_InitTypeDef * LLI_CCR_InitStruct) |
||
1145 | |||
1146 | { |
||
1147 | u32 CC=0; |
||
1148 | /* Set The Destination width */ |
||
1149 | CC &= DMA_Width_DES_MASK; |
||
1150 | CC |= LLI_CCR_InitStruct->LLI_DesWidth; |
||
1151 | |||
1152 | /* Set The Source width */ |
||
1153 | CC &= DMA_Width_SRC_MASK; |
||
1154 | CC |= LLI_CCR_InitStruct->LLI_SrcWidth; |
||
1155 | |||
1156 | /* Set The Burst Size for the Destination */ |
||
1157 | CC &= DMA_Bst_DES_MASK; |
||
1158 | CC |= LLI_CCR_InitStruct->LLI_DesBstSize; |
||
1159 | |||
1160 | /* Set The Burst Size for the Source */ |
||
1161 | CC &= DMA_Bst_SRC_MASK; |
||
1162 | CC |= LLI_CCR_InitStruct->LLI_SrcBstSize; |
||
1163 | |||
1164 | /* Initialize The Transfer Size for the Source */ |
||
1165 | CC &= DMA_TrsfSisze_Mask; |
||
1166 | CC |= LLI_CCR_InitStruct->LLI_TrsfSize; |
||
1167 | |||
1168 | /* Enable or disable source increment*/ |
||
1169 | CC &= DMA_SrcIncrement_MASK ; |
||
1170 | CC |= LLI_CCR_InitStruct->LLI_SrcIncrement; |
||
1171 | |||
1172 | /* Enable or disable destination increment*/ |
||
1173 | CC &= DMA_DesIncrement_MASK ; |
||
1174 | CC |= LLI_CCR_InitStruct->LLI_DesIncrement; |
||
1175 | |||
1176 | /* Enable or disable cacheable access*/ |
||
1177 | CC &= DMA_CacheableAccess_MASK; |
||
1178 | CC |= LLI_CCR_InitStruct->LLI_PROT0; |
||
1179 | |||
1180 | /* Enable or disable bufferable access*/ |
||
1181 | CC &= DMA_BufferableAccess_MASK; |
||
1182 | CC |= LLI_CCR_InitStruct->LLI_PROT1; |
||
1183 | |||
1184 | /* Enable or disablePrivileged mode*/ |
||
1185 | CC &= DMA_PrivilegedAccess_MASK; |
||
1186 | CC |= LLI_CCR_InitStruct->LLI_PROT2; |
||
1187 | |||
1188 | /* Enable or disable Terminal count interrupt*/ |
||
1189 | CC &= DMA_TCInterrupt_MASK ; |
||
1190 | CC |= LLI_CCR_InitStruct->LLI_TCInterrupt; |
||
1191 | return CC; |
||
1192 | } |
||
1193 | |||
1194 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ |