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196 | killagreg | 1 | /******************** (C) COPYRIGHT 2008 STMicroelectronics ******************** |
2 | * File Name : 91x_dma.h |
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1 | ingob | 3 | * Author : MCD Application Team |
196 | killagreg | 4 | * Version : V2.1 |
5 | * Date : 12/22/2008 |
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1 | ingob | 6 | * Description : provide a short description of the source file indicating |
7 | * its purpose. |
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8 | ******************************************************************************** |
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9 | * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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10 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
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11 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
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12 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
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13 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
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14 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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15 | *******************************************************************************/ |
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16 | |||
17 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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18 | #ifndef __91x_DMA_H |
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19 | #define __91x_DMA_H |
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20 | |||
21 | /* Includes ------------------------------------------------------------------*/ |
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22 | #include"91x_map.h" |
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23 | |||
24 | |||
25 | /* Exported types ------------------------------------------------------------*/ |
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26 | |||
27 | typedef struct |
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28 | { |
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29 | u32 DMA_Channel_SrcAdd; /* The current source address (byte-aligned) of the data to be transferred.*/ |
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30 | |||
31 | u32 DMA_Channel_DesAdd; /* The current destination address (byte-aligned) of the data to be transferred.*/ |
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32 | |||
33 | u32 DMA_Channel_LLstItm; /* The word- aligned address for the next Linked List Item. */ |
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34 | |||
35 | u32 DMA_Channel_DesWidth; /* Destination transfer width. */ |
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36 | |||
37 | u32 DMA_Channel_SrcWidth; /* Source transfer width. */ |
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38 | |||
39 | u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/ |
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40 | |||
41 | u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */ |
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42 | |||
43 | u32 DMA_Channel_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/ |
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44 | |||
45 | u32 DMA_Channel_FlowCntrl; /* Flow control and transfer type. */ |
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46 | |||
47 | u32 DMA_Channel_Src; /* Source peripheral: selects the DMA source request peripheral. */ |
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48 | |||
49 | u32 DMA_Channel_Des; /* Destination peripheral:selects the DMA destination request peripheral. */ |
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50 | |||
51 | } DMA_InitTypeDef; |
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52 | |||
196 | killagreg | 53 | typedef struct |
54 | { |
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55 | |||
56 | |||
57 | u32 LLI_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/ |
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58 | u32 LLI_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */ |
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59 | u32 LLI_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/ |
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60 | u32 LLI_SrcWidth; /* Source transfer width. */ |
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61 | u32 LLI_DesWidth; /* Destination transfer width. */ |
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62 | u32 LLI_SrcIncrement; /*Source increment*/ |
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63 | u32 LLI_DesIncrement; /*Destination increment*/ |
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64 | u32 LLI_PROT0; /*Cacheable Access*/ |
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65 | u32 LLI_PROT1; /*Bufferable Access*/ |
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66 | u32 LLI_PROT2; /*Privileged mode activation*/ |
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67 | u32 LLI_TCInterrupt; /*Terminal count interrupt activation*/ |
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68 | |||
69 | } LLI_CCR_InitTypeDef; |
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70 | |||
71 | typedef struct |
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72 | { |
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73 | u32 LLI_SrcAdd; /* Source address of the data to be transferred.*/ |
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74 | |||
75 | u32 LLI_DesAdd; /* Destination address of the data to be transferred.*/ |
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76 | |||
77 | u32 LLI_Pointer; /* Pointer to the next LLI. */ |
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78 | |||
79 | u32 LLI_CCR; /* the control word. */ |
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80 | |||
81 | } LLI_InitTypeDef; |
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82 | |||
83 | |||
84 | |||
85 | |||
1 | ingob | 86 | /* Exported constants --------------------------------------------------------*/ |
87 | |||
88 | /* Interrupts masks */ |
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89 | |||
90 | #define DMA_ITMask_IE 0x4000 /* Interrupt error mask. */ |
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91 | #define DMA_ITMask_ITC 0x8000 /* Terminal count interrupt mask.*/ |
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92 | #define DMA_ITMask_ALL 0xC000 /* All DMA_Channelx interrupts enable/disable mask*/ |
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93 | |||
94 | /* Sources Request (used as masks) */ |
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95 | |||
96 | #define DMA_USB_RX_Mask 0x0001 |
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97 | #define DMA_USB_TX_Mask 0x0002 |
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98 | #define DMA_TIM0_Mask 0x0004 |
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99 | #define DMA_TIM1_Mask 0x0008 |
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100 | #define DMA_UART0_RX_Mask 0x0010 |
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101 | #define DMA_UART0_TX_Mask 0x0020 |
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102 | #define DMA_UART1_RX_Mask 0x0040 |
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103 | #define DMA_UART1_TX_Mask 0x0080 |
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104 | #define DMA_External_Req0_Mask 0x0100 |
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105 | #define DMA_External_Req1_Mask 0x0200 |
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106 | #define DMA_I2C0_Mask 0x0400 |
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107 | #define DMA_I2C1_Mask 0x0800 |
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108 | #define DMA_SSP0_RX_Mask 0x1000 |
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109 | #define DMA_SSP0_TX_Mask 0x2000 |
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110 | #define DMA_SSP1_RX_Mask 0x4000 |
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111 | #define DMA_SSP1_TX_Mask 0x8000 |
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112 | |||
113 | |||
114 | /* Previleged Mode and user mode */ |
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115 | |||
116 | #define DMA_PrevilegedMode 0x10000000 |
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117 | #define DMA_UserMode 0xEFFFFFFF |
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118 | |||
119 | |||
120 | /* Error and Terminal Count interrupts Status, after and before"raw" masking */ |
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121 | #define DMA_IS 0x01 |
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122 | #define DMA_TCS 0x02 |
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123 | #define DMA_ES 0x03 |
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124 | #define DMA_TCRS 0x04 |
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125 | #define DMA_ERS 0x05 |
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126 | |||
127 | |||
128 | /* interrupt clear: Terminal Count flag Clear and Error flag clear*/ |
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129 | |||
130 | #define DMA_TCC 0x01 |
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131 | #define DMA_EC 0x02 |
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132 | |||
133 | /* channel index "0...7"*/ |
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134 | |||
135 | #define Channel0 0 |
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136 | #define Channel1 1 |
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137 | #define Channel2 2 |
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138 | #define Channel3 3 |
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139 | #define Channel4 4 |
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140 | #define Channel5 5 |
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141 | #define Channel6 6 |
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142 | #define Channel7 7 |
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143 | |||
144 | |||
145 | |||
146 | /* Destination request selection: selects the DMA Destination request peripheral */ |
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147 | |||
148 | #define DMA_DES_USB_RX 0x00 |
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149 | #define DMA_DES_USB_TX 0x40 |
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150 | #define DMA_DES_TIM0 0x80 |
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151 | #define DMA_DES_TIM1 0xC0 |
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152 | #define DMA_DES_UART0_RX 0x100 |
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153 | #define DMA_DES_UART0_TX 0x140 |
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154 | #define DMA_DES_UART1_RX 0x180 |
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155 | #define DMA_DES_UART1_TX 0x1C0 |
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156 | #define DMA_DES_External_Req0 0x200 |
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157 | #define DMA_DES_External_Req1 0x240 |
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158 | #define DMA_DES_I2C0 0x280 |
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159 | #define DMA_DES_I2C1 0x2C0 |
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160 | #define DMA_DES_SSP0_RX 0x300 |
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161 | #define DMA_DES_SSP0_TX 0x340 |
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162 | #define DMA_DES_SSP1_RX 0x380 |
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163 | #define DMA_DES_SSP1_TX 0x3C0 |
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164 | |||
165 | |||
166 | |||
167 | |||
168 | /* Source request selection: selects the DMA Source request peripheral */ |
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169 | |||
170 | #define DMA_SRC_USB_RX 0x00 |
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171 | #define DMA_SRC_USB_TX 0x02 |
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172 | #define DMA_SRC_TIM0 0x04 |
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173 | #define DMA_SRC_TIM1 0x06 |
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174 | #define DMA_SRC_UART0_RX 0x08 |
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175 | #define DMA_SRC_UART0_TX 0x0A |
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176 | #define DMA_SRC_UART1_RX 0x0C |
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177 | #define DMA_SRC_UART1_TX 0x0E |
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178 | #define DMA_SRC_External_Req0 0x10 |
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179 | #define DMA_SRC_External_Req1 0x12 |
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180 | #define DMA_SRC_I2C0 0x14 |
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181 | #define DMA_SRC_I2C1 0x16 |
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182 | #define DMA_SRC_SSP0_RX 0x18 |
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183 | #define DMA_SRC_SSP0_TX 0x1A |
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184 | #define DMA_SRC_SSP1_RX 0x1C |
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185 | #define DMA_SRC_SSP1_TX 0x1E |
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186 | |||
187 | |||
188 | |||
189 | |||
190 | |||
191 | #define DMA_FlowCntrlt0_DMA 0x00000000 /* transfer type :Memory-to-memory, flow controller:DMA */ |
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192 | #define DMA_FlowCntrl1_DMA 0x00000800 /* transfer type :Memory-to-peripheral, flow controller:DMA */ |
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193 | #define DMA_FlowCntrl2_DMA 0x00001000 /* transfer type :Peripheral-to-memory, flow controller:DMA */ |
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194 | #define DMA_FlowCntrl3_DMA 0x00001800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */ |
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195 | #define DMA_FlowCntrl_DestPerip 0x00002000 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */ |
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196 | #define DMA_FlowCntrl_Perip1 0x00002800 /* transfer type :Memory-to-peripheral, flow controller:peripheral */ |
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197 | #define DMA_FlowCntrl_Perip2 0x00003000 /* transfer type : Peripheral-to-memory, flow controller:peripheral */ |
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198 | #define DMA_FlowCntrl_SrcPerip 0x00003800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */ |
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199 | |||
200 | |||
201 | |||
202 | |||
203 | #define DMA_SrcBst_1Data 0x00000000 /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */ |
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204 | #define DMA_SrcBst_4Data 0x00001000 /* Source Burst transfer request IS 4 Data */ |
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205 | #define DMA_SrcBst_8Data 0x00002000 /* Source Burst transfer request IS 8 Data */ |
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206 | #define DMA_SrcBst_16Data 0x00003000 /* Source Burst transfer request IS 16 Data */ |
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207 | #define DMA_SrcBst_32Data 0x00004000 /* Source Burst transfer request IS 32 Data */ |
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208 | #define DMA_SrcBst_64Data 0x00005000 /* Source Burst transfer request IS 64Data */ |
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196 | killagreg | 209 | #define DMA_SrcBst_128Data 0x00006000 /* Source Burst transfer request IS 128 Data */ |
210 | #define DMA_SrcBst_256Data 0x00007000 /* Source Burst transfer request IS 256 Data */ |
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1 | ingob | 211 | |
212 | |||
213 | |||
214 | |||
215 | #define DMA_DesBst_1Data 0x00000000 /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */ |
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216 | #define DMA_DesBst_4Data 0x00008000 /*Destination Burst transfer request IS 1 Data */ |
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217 | #define DMA_DesBst_8Data 0x00010000 /*Destination Burst transfer request IS 4 Data */ |
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218 | #define DMA_DesBst_16Data 0x00018000 /*Destination Burst transfer request IS 8 Data */ |
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219 | #define DMA_DesBst_32Data 0x00020000 /*Destination Burst transfer request IS 16 Data */ |
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220 | #define DMA_DesBst_64Data 0x00028000 /*Destination Burst transfer request IS 32 Data */ |
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196 | killagreg | 221 | #define DMA_DesBst_128Data 0x00030000 /*Destination Burst transfer request IS 128 Data */ |
222 | #define DMA_DesBst_256Data 0x00038000 /*Destination Burst transfer request IS 256 Data */ |
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1 | ingob | 223 | |
224 | |||
225 | |||
226 | |||
227 | |||
228 | #define DMA_SrcWidth_Byte 0x00000000 /* source Width is one Byte */ |
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196 | killagreg | 229 | #define DMA_SrcWidth_HalfWord 0x00040000 /* source Width is one HalfWord */ |
1 | ingob | 230 | #define DMA_SrcWidth_Word 0x00080000 /* source Width is one Word */ |
231 | |||
232 | |||
233 | |||
234 | |||
235 | #define DMA_DesWidth_Byte 0x00000000 /* Destination Width is one Byte */ |
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196 | killagreg | 236 | #define DMA_DesWidth_HalfWord 0x00200000 /* Destination Width is one HalfWord */ |
1 | ingob | 237 | #define DMA_DesWidth_Word 0x00400000 /* Destination Width is one Word */ |
238 | |||
196 | killagreg | 239 | /*Defined value used for linked list's control word stucture*/ |
1 | ingob | 240 | |
196 | killagreg | 241 | #define DMA_SrcIncrement 0x04000000 /*Source incremented*/ |
242 | #define DMA_SrcNonIncrement 0x00000000 /*Source not incremented*/ |
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243 | #define DMA_DesIncrement 0x08000000 /*Destination incremented*/ |
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244 | #define DMA_DesNonIncrement 0x00000000 /*Destination not incremented*/ |
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245 | #define DMA_CacheableAccess 0x10000000 /*Cacheable access */ |
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246 | #define DMA_NonCacheableAccess 0x00000000 /*Non Cacheable access */ |
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247 | #define DMA_BufferableAccess 0x20000000 /*Bufferable access */ |
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248 | #define DMA_NonBufferableAccess 0x00000000 /*Non Bufferable access */ |
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249 | #define DMA_PrivilegedAccess 0x40000000 /*Privileged Access*/ |
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250 | #define DMA_UsermodeAccess 0x00000000 /*User mode Access*/ |
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251 | #define DMA_TCInterrupt 0x80000000 /* Terminal count interrupt enabled*/ |
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252 | #define DMA_NonTCInterrupt 0x00000000 /* Terminal count interrupt disabled*/ |
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1 | ingob | 253 | |
254 | |||
196 | killagreg | 255 | |
1 | ingob | 256 | /* Exported macro ------------------------------------------------------------*/ |
257 | /* Exported functions ------------------------------------------------------- */ |
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258 | |||
259 | void DMA_DeInit(void); |
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260 | void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct); |
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261 | void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); |
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262 | void DMA_Cmd(FunctionalState NewState); |
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263 | void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState); |
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264 | void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); |
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265 | FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ); |
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266 | ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq); |
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267 | void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr); |
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268 | void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState); |
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269 | FlagStatus DMA_GetSReq(u16 DMA_SrcReq); |
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270 | FlagStatus DMA_GetLSReq(u16 DMA_SrcReq); |
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271 | FlagStatus DMA_GetBReq(u16 DMA_SrcReq); |
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272 | FlagStatus DMA_GetLBReq(u16 DMA_SrcReq); |
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273 | FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx); |
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274 | void DMA_SetSReq(u16 DMA_SrcReq); |
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275 | void DMA_SetLSReq(u16 DMA_SrcReq); |
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276 | void DMA_SetBReq(u16 DMA_SrcReq); |
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277 | void DMA_SetLBReq(u16 DMA_SrcReq); |
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278 | void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); |
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279 | void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); |
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280 | void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); |
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281 | void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); |
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282 | void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); |
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283 | void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode); |
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284 | void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); |
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285 | void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); |
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196 | killagreg | 286 | u32 DMA_LLI_CCR_Init(LLI_CCR_InitTypeDef * LLI_CCR_InitStruct); |
1 | ingob | 287 | |
288 | #endif /* __91x_DMA_H */ |
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289 | |||
196 | killagreg | 290 | /******************* (C) COPYRIGHT 2008 STMicroelectronics *****END OF FILE****/ |