WebSVN - NaviCtrl - Blame - Rev 109 - /tags/V0.15c/libstr91x/src/91x

Rev	Author	Line No.	Line
1	ingob	1	/****************** (C) COPYRIGHT 2006 STMicroelectronics ******************
		2	* File Name : 91x_dma.c
		3	* Author : MCD Application Team
		4	* Date First Issued : 05/18/2006 : Version 1.0
		5	* Description : This file provides all the DMA software functions
		6	* needed to access all DMA registers.
		7	********************************************************************************
		8	* History:v 1.0
		9	* 05/22/2007 : Version 1.2
		10	* 05/24/2006 : Version 1.1
		11	* 05/18/2006 : Version 1.0
		12	********************************************************************************
		13	* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
		14	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
		15	* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
		16	* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
		17	* CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
		18	* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
		19	*******************************************************************************/
		20
		21	/* Includes ------------------------------------------------------------------*/
		22
		23	# include"91x_dma.h"
		24	# include"91x_scu.h"
		25
		26	/* Private typedef -----------------------------------------------------------*/
		27	/* Private define ------------------------------------------------------------*/
		28	/* Private macro -------------------------------------------------------------*/
		29	/* Private variables ---------------------------------------------------------*/
		30
		31
		32	/* DMA Masks "used" only in this module */
		33
		34	#define DMA_Width_DES_MASK 0xFF1FFFFF
		35	#define DMA_Width_SRC_MASK 0xFFE3FFFF
		36	#define DMA_Bst_DES_MASK 0xFFFC7FFF
		37	#define DMA_Bst_SRC_MASK 0xFFFF8FFF
		38	#define DMA_FlowCntrl_Mask 0xFFFFC7FF
		39	#define DMA_TrsfSisze_Mask 0xFFFFF000
		40	#define SRC_Mask 0xFFFFFFE1
		41	#define DES_Mask 0xFFFFFC3F
		42	#define DMA_TCIE 0x80000000
		43	#define DMA_ChannelDESInc 0x08000000
		44	#define DMA_ChannelSRCInc 0x04000000
		45	#define DMA_BufferChannel 0x20000000
		46	#define DMA_HaltChannel 0x00040000
		47	#define DMA_LockChannel 0x00010000
		48	#define DMA_CacheChannel 0x40000000
		49	#define DMA_ChannelActive 0x00020000
		50	#define DMA_Enable 0x00000001
		51	#define DMA_ChannelEnable 0x00000001
		52
		53
		54
		55
		56	/* Private function prototypes -----------------------------------------------*/
		57	/* Private functions ---------------------------------------------------------*/
		58
		59	/*******************************************************************************
		60	* Function Name : DMA_ITMaskConfig
		61	* Description : Enables or disables the specified DMA_Channelx Mask interrupt.
		62	* Input :
		63	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		64	* -DMA_ITMask: specifies the DMA interrupt mask source to be enabled or disabled.
		65	* This parameter can be:
		66	* - DMA_ITMask_IE (Interrupt error mask).
		67	* - DMA_ITMask_ITC (Terminal count interrupt mask).
		68	* - DMA_ITMask_ALL ( All interrupts mask)
		69	*
		70	* -NewState: new state of the specified DMA_Channelx mask interrupt.
		71	* This parameter can be: ENABLE or DISABLE.
		72	* Output : None.
		73	* Return : None.
		74	*******************************************************************************/
		75
		76
		77	void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask , FunctionalState NewState)
		78
		79	{
		80	if (NewState==ENABLE) /* Mask the Interrupt */
		81	{
		82	DMA_Channelx-> CCNF \|= DMA_ITMask ;
		83	}
		84
		85	else /* Disable the Interrupt Mask*/
		86	{
		87	DMA_Channelx-> CCNF &= ~ DMA_ITMask ;
		88	}
		89	}
		90
		91
		92
		93
		94
		95	/*******************************************************************************
		96	* Function Name : DMA_ITConfig
		97	* Description : Enables or disables the DMA_Channelx Terminal Count interrupt.
		98	* Input :
		99	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		100	* -NewState: new state of the specified DMA_Channelx mask interrupt.
		101	* This parameter can be: ENABLE or DISABLE.
		102	* Output : None.
		103	* Return : None.
		104	*******************************************************************************/
		105
		106
		107	void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState)
		108
		109	{
		110	if (NewState==ENABLE) /* Enable the Terminal Count Interrupt */
		111	{
		112	DMA_Channelx->CC \|= DMA_TCIE ;
		113	}
		114
		115	else /* Disable the Terminal Count Interrupt */
		116	{
		117	DMA_Channelx-> CC &= ~ DMA_TCIE ;
		118	}
		119	}
		120
		121
		122	/********************************************************************************
		123	* Function Name : DMA_SyncConfig
		124	* Description : Enables or disables synchronization logic for the corresponding DMA Request Signal.
		125	* Input :
		126	* -SRCReq:specifies the DMA Request Source.
		127	* This parameter can be:
		128	* -DMA_USB_RX_Mask
		129	* -DMA_USB_TX_Mask
		130	* -DMA_TIM0_Mask
		131	* -DMA_TIM1_Mask
		132	* -DMA_UART0_RX_Mask
		133	* -DMA_UART0_TX_Mask
		134	* -DMA_UART1_RX_Mask
		135	* -DMA_UART1_TX_Mask
		136	* -DMA_External_Req0_Mask
		137	* -DMA_External_Req1_Mask
		138	* -DMA_I2C0_Mask
		139	* -DMA_I2C1_Mask
		140	* -DMA_SSP0_RX_Mask
		141	* -DMA_SSP0_TX_Mask
		142	* -DMA_SSP1_RX_Mask
		143	* -DMA_SSP1_TX_Mask
		144	*
		145	* -NewState: new state of the specified DMA_Channelx mask interrupt.
		146	* This parameter can be: ENABLE or DISABLE.
		147	* Output : None.
		148	* Return : None.
		149	*******************************************************************************/
		150
		151
		152	void DMA_SyncConfig(u16 SRCReq, FunctionalState NewState)
		153
		154	{
		155	if (NewState==ENABLE) /* Enable the synchronization logic for the corresponding DMA Request Signal */
		156	{
		157
		158	DMA->SYNR &= ~ SRCReq ;
		159
		160	}
		161
		162	else /* Disable the synchronization logic for the corresponding DMA Request Signal. */
		163	{
		164	DMA->SYNR \|= SRCReq ;
		165
		166	}
		167	}
		168
		169
		170	/********************************************************************************
		171	* Function Name : DMA_SetSReq
		172	* Description : Set the DMA to generate a Single transfer request for the corresponding DMA Request Source.
		173	* Input :
		174	* -SRCReq:specifies the DMA Request Source.
		175	* This parameter can be:
		176	* -DMA_USB_RX_Mask
		177	* -DMA_USB_TX_Mask
		178	* -DMA_TIM0_Mask
		179	* -DMA_TIM1_Mask
		180	* -DMA_UART0_RX_Mask
		181	* -DMA_UART0_TX_Mask
		182	* -DMA_UART1_RX_Mask
		183	* -DMA_UART1_TX_Mask
		184	* -DMA_External_Req0_Mask
		185	* -DMA_External_Req1_Mask
		186	* -DMA_I2C0_Mask
		187	* -DMA_I2C1_Mask
		188	* -DMA_SSP0_RX_Mask
		189	* -DMA_SSP0_TX_Mask
		190	* -DMA_SSP1_RX_Mask
		191	* -DMA_SSP1_TX_Mask
		192	*
		193	* Output : None.
		194	* Return : None.
		195	*******************************************************************************/
		196
		197
		198	void DMA_SetSReq(u16 SRCReq)
		199
		200	{ /* Set the DMA to generate a Single transfer request for the corresponding DMA Request Source */
		201	DMA->SSRR \|= SRCReq ;
		202	}
		203
		204
		205
		206
		207	/********************************************************************************
		208	* Function Name : DMA_SetLSReq
		209	* Description : Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source.
		210	* Input :
		211	* -SRCReq:specifies the DMA Request Source.
		212	* This parameter can be:
		213	* -DMA_USB_RX_Mask
		214	* -DMA_USB_TX_Mask
		215	* -DMA_TIM0_Mask
		216	* -DMA_TIM1_Mask
		217	* -DMA_UART0_RX_Mask
		218	* -DMA_UART0_TX_Mask
		219	* -DMA_UART1_RX_Mask
		220	* -DMA_UART1_TX_Mask
		221	* -DMA_External_Req0_Mask
		222	* -DMA_External_Req1_Mask
		223	* -DMA_I2C0_Mask
		224	* -DMA_I2C1_Mask
		225	* -DMA_SSP0_RX_Mask
		226	* -DMA_SSP0_TX_Mask
		227	* -DMA_SSP1_RX_Mask
		228	* -DMA_SSP1_TX_Mask
		229	* Output : None.
		230	* Return : None.
		231	*******************************************************************************/
		232
		233	void DMA_SetLSReq(u16 SRCReq )
		234	{ /* Set the DMA to generate a Last Single transfer request for the corresponding DMA Request Source */
		235	DMA->SLSRR \|= SRCReq ;
		236	}
		237
		238
		239	/********************************************************************************
		240	* Function Name : DMA_SetBReq
		241	* Description : Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source.
		242	* Input :
		243	* -SRCReq:specifies the DMA Request Source.
		244	* This parameter can be:
		245	* -DMA_USB_RX_Mask
		246	* -DMA_USB_TX_Mask
		247	* -DMA_TIM0_Mask
		248	* -DMA_TIM1_Mask
		249	* -DMA_UART0_RX_Mask
		250	* -DMA_UART0_TX_Mask
		251	* -DMA_UART1_RX_Mask
		252	* -DMA_UART1_TX_Mask
		253	* -DMA_External_Req0_Mask
		254	* -DMA_External_Req1_Mask
		255	* -DMA_I2C0_Mask
		256	* -DMA_I2C1_Mask
		257	* -DMA_SSP0_RX_Mask
		258	* -DMA_SSP0_TX_Mask
		259	* -DMA_SSP1_RX_Mask
		260	* -DMA_SSP1_TX_Mask
		261	* Output : None.
		262	* Return : None.
		263	*******************************************************************************/
		264
		265
		266	void DMA_SetBReq(u16 SRCReq)
		267
		268	{ /* Set the DMA to generate a Burst transfer request for the corresponding DMA Request Source */
		269	DMA->SBRR \|= SRCReq ;
		270	}
		271
		272
		273
		274	/********************************************************************************
		275	* Function Name : DMA_SetLBReq
		276	* Description : Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source.
		277	* Input :
		278	* -SRCReq:specifies the DMA Request Source.
		279	* This parameter can be:
		280	* -DMA_USB_RX_Mask
		281	* -DMA_USB_TX_Mask
		282	* -DMA_TIM0_Mask
		283	* -DMA_TIM1_Mask
		284	* -DMA_UART0_RX_Mask
		285	* -DMA_UART0_TX_Mask
		286	* -DMA_UART1_RX_Mask
		287	* -DMA_UART1_TX_Mask
		288	* -DMA_External_Req0_Mask
		289	* -DMA_External_Req1_Mask
		290	* -DMA_I2C0_Mask
		291	* -DMA_I2C1_Mask
		292	* -DMA_SSP0_RX_Mask
		293	* -DMA_SSP0_TX_Mask
		294	* -DMA_SSP1_RX_Mask
		295	* -DMA_SSP1_TX_Mask
		296	* Output : None.
		297	* Return : None.
		298	*******************************************************************************/
		299
		300
		301	void DMA_SetLBReq(u16 SRCReq)
		302
		303	{ /* Set the DMA to generate a Last Burst transfer request for the corresponding DMA Request Source */
		304	DMA->SLBRR \|= SRCReq ;
		305	}
		306
		307
		308	/********************************************************************************
		309	* Function Name : DMA_GetSReq
		310	* Description : Check for a specific source if it request a Single transfer .
		311	* Input :
		312	* Input :
		313	* -SRCReq:specifies the DMA Request Source.
		314	* This parameter can be:
		315	* -DMA_USB_RX_Mask
		316	* -DMA_USB_TX_Mask
		317	* -DMA_TIM0_Mask
		318	* -DMA_TIM1_Mask
		319	* -DMA_UART0_RX_Mask
		320	* -DMA_UART0_TX_Mask
		321	* -DMA_UART1_RX_Mask
		322	* -DMA_UART1_TX_Mask
		323	* -DMA_External_Req0_Mask
		324	* -DMA_External_Req1_Mask
		325	* -DMA_I2C0_Mask
		326	* -DMA_I2C1_Mask
		327	* -DMA_SSP0_RX_Mask
		328	* -DMA_SSP0_TX_Mask
		329	* -DMA_SSP1_RX_Mask
		330	* -DMA_SSP1_TX_Mask
		331	* Output : None.
		332	* Return : SET or RESET.
		333	*******************************************************************************/
		334
		335
		336	FlagStatus DMA_GetSReq(u16 SRCReq)
		337
		338	{ /* Check for a specific source if it request a Single transfer . */
		339	if ( (DMA->SSRR & SRCReq )!= RESET )
		340	{
		341	return SET;
		342	}
		343
		344	else
		345	{
		346	return RESET;
		347	}
		348	}
		349
		350
		351	/********************************************************************************
		352	* Function Name : DMA_GetLSReq
		353	* Description : Check for a specific source if it request a Last Single transfer .
		354	* Input :
		355	* -SRCReq:specifies the DMA Request Source.
		356	* This parameter can be:
		357	* -DMA_USB_RX_Mask
		358	* -DMA_USB_TX_Mask
		359	* -DMA_TIM0_Mask
		360	* -DMA_TIM1_Mask
		361	* -DMA_UART0_RX_Mask
		362	* -DMA_UART0_TX_Mask
		363	* -DMA_UART1_RX_Mask
		364	* -DMA_UART1_TX_Mask
		365	* -DMA_External_Req0_Mask
		366	* -DMA_External_Req1_Mask
		367	* -DMA_I2C0_Mask
		368	* -DMA_I2C1_Mask
		369	* -DMA_SSP0_RX_Mask
		370	* -DMA_SSP0_TX_Mask
		371	* -DMA_SSP1_RX_Mask
		372	* -DMA_SSP1_TX_Mask
		373	* Output : None.
		374	* Return : SET or RESET.
		375	*******************************************************************************/
		376
		377
		378	FlagStatus DMA_GetLSReq(u16 SRCReq)
		379
		380	{ /* Check for a specific source if it request a Last Single transfer . */
		381	if ( (DMA->SLSRR & SRCReq)!= RESET )
		382	{
		383	return SET;
		384	}
		385
		386	else
		387	{
		388	return RESET;
		389	}
		390	}
		391
		392	/********************************************************************************
		393	* Function Name : DMA_GetBReq
		394	* Description : Check for a specific source if it request a Burst transfer .
		395	* Input :
		396	* -SRCReq:specifies the DMA Request Source.
		397	* This parameter can be:
		398	* -DMA_USB_RX_Mask
		399	* -DMA_USB_TX_Mask
		400	* -DMA_TIM0_Mask
		401	* -DMA_TIM1_Mask
		402	* -DMA_UART0_RX_Mask
		403	* -DMA_UART0_TX_Mask
		404	* -DMA_UART1_RX_Mask
		405	* -DMA_UART1_TX_Mask
		406	* -DMA_External_Req0_Mask
		407	* -DMA_External_Req1_Mask
		408	* -DMA_I2C0_Mask
		409	* -DMA_I2C1_Mask
		410	* -DMA_SSP0_RX_Mask
		411	* -DMA_SSP0_TX_Mask
		412	* -DMA_SSP1_RX_Mask
		413	* -DMA_SSP1_TX_Mask
		414	* Output : None.
		415	* Return : SET or RESET.
		416	*******************************************************************************/
		417
		418
		419	FlagStatus DMA_GetBReq(u16 SRCReq)
		420
		421	{ /* Check for a specific source if it request a Burst transfer . */
		422	if (( DMA->SBRR & SRCReq ) != RESET )
		423	{
		424	return SET;
		425	}
		426
		427	else
		428	{
		429	return RESET;
		430	}
		431	}
		432
		433	/********************************************************************************
		434	* Function Name : DMA_GetLSReq
		435	* Description : Check for a specific source if it request a Last Burst transfer .
		436	* Input :
		437	* Input :
		438	* - SRCReq:specifies the DMA Request Source.
		439	* This parameter can be:
		440	* -DMA_USB_RX_Mask
		441	* -DMA_USB_TX_Mask
		442	* -DMA_TIM0_Mask
		443	* -DMA_TIM1_Mask
		444	* -DMA_UART0_RX_Mask
		445	* -DMA_UART0_TX_Mask
		446	* -DMA_UART1_RX_Mask
		447	* -DMA_UART1_TX_Mask
		448	* -DMA_External_Req0_Mask
		449	* -DMA_External_Req1_Mask
		450	* -DMA_I2C0_Mask
		451	* -DMA_I2C1_Mask
		452	* -DMA_SSP0_RX_Mask
		453	* -DMA_SSP0_TX_Mask
		454	* -DMA_SSP1_RX_Mask
		455	* -DMA_SSP1_TX_Mask
		456	* Output : None.
		457	* Return : SET or RESET.
		458	*******************************************************************************/
		459
		460
		461	FlagStatus DMA_GetLBReq(u16 SRCReq)
		462
		463	{ /* Check for a specific source if it request a Last Burst transfer . */
		464	if ( ( DMA->SLBRR & SRCReq ) != RESET )
		465	{
		466	return SET;
		467	}
		468
		469	else
		470	{
		471	return RESET;
		472	}
		473	}
		474
		475
		476
		477	/*******************************************************************************
		478	* Function Name : DMA_ChannelHalt
		479	* Description : Enables DMA requests or ignore extra source DMA requests for
		480	the specified channel.
		481	* Input :
		482	-DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		483	-NewState: new state of the specified DMA_Channelx mask interrupt.
		484	This parameter can be: ENABLE or DISABLE.
		485	* Output : None.
		486	* Return : None.
		487	*******************************************************************************/
		488
		489
		490	void DMA_ChannelHalt(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState)
		491
		492	{
		493	if (NewState==ENABLE) /* Enables DMA requests */
		494
		495	{
		496	DMA_Channelx->CCNF \|= DMA_HaltChannel ;
		497	}
		498
		499	else /* Ignore extra source DMA request */
		500	{
		501	DMA_Channelx->CCNF &= ~ DMA_HaltChannel ;
		502	}
		503	}
		504
		505
		506	/*******************************************************************************
		507	* Function Name : DMA_ChannelLockTrsf
		508	* Description : Enables or disables the Locked Transfers Feature for the specified DMA_Channelx
		509	* Input :
		510	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		511	* -NewState: new state of the specified DMA_Channelx mask interrupt.
		512	* This parameter can be: ENABLE or DISABLE.
		513	* Output : None.
		514	* Return : None.
		515	*******************************************************************************/
		516
		517
		518	void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState)
		519
		520	{
		521	if (NewState==ENABLE) /* Locked transfers enabled on channel x */
		522
		523	{
		524	DMA_Channelx->CCNF \|= DMA_LockChannel ;
		525	}
		526
		527	else /* Locked transfers disabled on channel xt */
		528	{
		529	DMA_Channelx->CCNF &= ~ DMA_LockChannel;
		530	}
		531	}
		532
		533
		534	/*******************************************************************************
		535	* Function Name : DMA_ChannelCache
		536	* Description : Enables or disables the cacheability Feature for the specified DMA_Channelx
		537	* Input :
		538	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		539	* -NewState: new state of the specified DMA_Channelx mask interrupt.
		540	* This parameter can be: ENABLE or DISABLE.
		541	* Output : None.
		542	* Return : None.
		543	*******************************************************************************/
		544
		545
		546	void DMA_ChannelCache (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState)
		547
		548	{
		549	if (NewState==ENABLE) /* Cacheability Feature enabled on channelx */
		550
		551	{
		552	DMA_Channelx->CC \|= DMA_CacheChannel ;
		553	}
		554
		555	else /* Cacheability Feature disabled on channelx */
		556	{
		557	DMA_Channelx->CC &= ~ DMA_CacheChannel ;
		558	}
		559	}
		560
		561
		562	/*******************************************************************************
		563	* Function Name : DMA_ChannelBuffering
		564	* Description : Enables or disables the Buffering Feature for the specified DMA_Channelx
		565	* Input :
		566	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		567	* -NewState: new state of the specified DMA_Channelx mask interrupt.
		568	* This parameter can be: ENABLE or DISABLE.
		569	* Output : None.
		570	* Return : None.
		571	*******************************************************************************/
		572
		573
		574	void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState)
		575
		576	{
		577	if (NewState==ENABLE) /* Cacheability Feature enabled on channel x */
		578
		579	{
		580	DMA_Channelx->CC \|= DMA_BufferChannel ;
		581	}
		582
		583	else /* Cacheability Feature disabled on channel xt */
		584	{
		585	DMA_Channelx->CC &= ~ DMA_BufferChannel ;
		586	}
		587	}
		588
		589	/*******************************************************************************
		590	* Function Name : MA_ChannelProt0Mod
		591	* Description : Sets The User or Privileged mode for the specified DMA_Channelx
		592	* Input :
		593	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		594	* -Prot0Mode: Specifies the Privileged mode Or the User mode.
		595	* This parameter can be:
		596	* - DMA_PrevilegedMode
		597	* - DMA_UserMode
		598	*
		599	*
		600	* Output : None.
		601	* Return : None.
		602	*******************************************************************************/
		603
		604
		605	void DMA_ChannelProt0Mode (DMA_Channel_TypeDef * DMA_Channelx, u32 Prot0Mode)
		606
		607	{
		608	if (Prot0Mode==DMA_PrevilegedMode) /* Privileged mode */
		609	{
		610	DMA_Channelx->CC \|= DMA_PrevilegedMode ;
		611	}
		612
		613	else /* User mode */
		614	{
		615	DMA_Channelx->CC &= DMA_UserMode ;
		616	}
		617	}
		618
		619
		620
		621
		622
		623	/*******************************************************************************
		624	* Function Name : DMA_ChannelSRCIncConfig
		625	* Description : Enables or disables the Source address incrementation after each transfer for
		626	* the specified DMA_Channelx
		627	* Input :
		628	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		629	* -NewState: new state of the specified DMA_Channelx mask interrupt.
		630	* This parameter can be: ENABLE or DISABLE.
		631	* Output : None.
		632	* Return : None.
		633	*******************************************************************************/
		634
		635
		636	void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState)
		637
		638	{
		639	if (NewState==ENABLE) /* The Source address is incremented after each transfer */
		640
		641	{
		642	DMA_Channelx->CC \|= DMA_ChannelSRCInc ;
		643	}
		644
		645	else /* The Source address is not incremented after each Transfer */
		646	{
		647	DMA_Channelx->CC &= ~ DMA_ChannelSRCInc ;
		648	}
		649	}
		650
		651
		652	/*******************************************************************************
		653	* Function Name : DMA_ChannelDESIncConfig
		654	* Description : Enables or disables the Destination address incrementation after each transfer for
		655	* the specified DMA_Channelx
		656	* Input :
		657	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		658	* -NewState: new state of the specified DMA_Channelx mask interrupt.
		659	* This parameter can be: ENABLE or DISABLE.
		660	* Output : None.
		661	* Return : None.
		662	*******************************************************************************/
		663
		664
		665	void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState)
		666
		667	{
		668	if (NewState==ENABLE) /* The Destination address is incremented after each transfer */
		669
		670	{
		671	DMA_Channelx->CC \|= DMA_ChannelDESInc ;
		672	}
		673
		674	else /* The Destination address is not incremented after each Transfer */
		675	{
		676	DMA_Channelx->CC &= ~ DMA_ChannelDESInc ;
		677	}
		678	}
		679
		680
		681
		682	/********************************************************************************
		683	* Function Name : DMA_GetChannelStatus
		684	* Description : Checks the status of DMA channelx ( Enabled or Disabled).
		685	* - ChannelIndx:specifies the DMA Channel to be checked.
		686	* This parameter can be:
		687	* - Channel0
		688	* - Channel1
		689	* - Channel2
		690	* - Channel3
		691	* - Channel4
		692	* - Channel5
		693	* - Channel6
		694	* - Channel7
		695	* Output : None.
		696	*
		697	* Return : SET or RESET.
		698	*******************************************************************************/
		699
		700
		701	FlagStatus DMA_GetChannelStatus(u8 ChannelIndx )
		702
		703	{
		704
		705	if ( ( DMA->ENCSR & (1 << ChannelIndx )) != RESET )
		706	{
		707	return SET; /* Channelx Enabled */
		708	}
		709
		710	else
		711
		712	{
		713
		714	return RESET; /* Channelx Disabled */
		715
		716	}
		717
		718	}
		719
		720
		721
		722	/********************************************************************************
		723	* Function Name : DMA_GetITStatus
		724	* Description : Checks the status of Terminal Count and Error interrupts request after and before Masking.
		725	* Input :
		726	* - ChannelIndx:specifies the DMA Channel to be checked.
		727	* This parameter can be:
		728	* - Channel0
		729	* - Channel1
		730	* - Channel2
		731	* - Channel3
		732	* - Channel4
		733	* - Channel5
		734	* - Channel6
		735	* - Channel7
		736	*
		737	*. - DMA_ITReq: specifies the DMA interrupt request status to be checked.
		738	* This parameter can be:
		739	*
		740	* - DMA_IS
		741	* - DMA_TCS
		742	* - DMA_ES
		743	* - DMA_TCRS
		744	* - DMA_ERS.
		745	*
		746	* Output : None.
		747	*
		748	* Return : SET or RESET.
		749	*******************************************************************************/
		750
		751
		752	ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq)
		753
		754	{
		755	u32 DMAReg = 0;
		756
		757	switch(DMA_ITReq)
		758
		759	{
		760
		761	case (DMA_IS): /The status of the interrupts after masking : logical or of all Interrupts after Masking/
		762	DMAReg = DMA->ISR;
		763	break;
		764
		765
		766
		767	case (DMA_TCS): /* The status of the Terminal count request after masking */
		768	DMAReg = DMA->TCISR;
		769	break;
		770
		771
		772	case (DMA_ES): /* The status of the error request after masking */
		773	DMAReg = DMA->EISR;
		774	break;
		775
		776
		777	case (DMA_TCRS): /* Indicates if the DMA channel is requesting a transfer complete (terminal count Interrupt) prior to masking or Not. */
		778	DMAReg = DMA->TCRISR;
		779	break;
		780
		781	case (DMA_ERS): /* Indicates if the DMA channel is requesting an Error Interrupt prior to masking or Not. */
		782	DMAReg = DMA->ERISR;
		783	break;
		784
		785
		786	}
		787
		788	if((DMAReg &(1 << ChannelIndx )) != RESET )
		789
		790	{
		791	return SET;
		792	}
		793
		794	else
		795
		796	{
		797
		798	return RESET;
		799
		800
		801	}
		802
		803	}
		804
		805
		806	/********************************************************************************
		807	* Function Name : DMA_ClearIT
		808	* Description : Clears The Interrupt pending bits for termnal count or Error interrupts for a specified DMA Channel.
		809	* - ChannelIndx:specifies the DMA Channel to be checked.
		810	* This parameter can be:
		811	* - Channel0
		812	* - Channel1
		813	* - Channel2
		814	* - Channel3
		815	* - Channel4
		816	* - Channel5
		817	* - Channel6
		818	* - Channel7
		819	* - DMA_ITClr : Specifies the DMA interrupt pending to be cleared.
		820	*. This parameter can be:
		821	* - DMA_TCC
		822	* - DMA_EC.
		823	*
		824	* Output : None.
		825
		826	* Return : SET or RESET.
		827	*******************************************************************************/
		828
		829
		830	void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr)
		831
		832	{
		833
		834
		835	switch(DMA_ITClr)
		836
		837	{
		838
		839	case (DMA_TCC): /* Clear The status of the Terminal count interrupt on the corresponding channel.*/
		840	DMA->TCICR \|=(1 << ChannelIndx );
		841	break;
		842
		843
		844
		845	case (DMA_EC): /* Clear The status of the error interrupt on the corresponding channel.*/
		846	DMA->EICR \|=(1 << ChannelIndx );
		847	break;
		848
		849
		850
		851	}
		852
		853
		854
		855	}
		856
		857
		858	/*******************************************************************************
		859	* Function Name : DMA_Cmd(FunctionalState NewState)
		860	* Description : Enables or disables the DMA peripheral.
		861	*
		862	* Input :
		863	* -NewState: new state of the DMA.
		864	* This parameter can be: ENABLE or DISABLE.
		865	* Output : None.
		866	* Return : None.
		867	*******************************************************************************/
		868
		869
		870	void DMA_Cmd(FunctionalState NewState)
		871
		872	{
		873	if (NewState==ENABLE) /* ENABLE the DMA peripheral */
		874
		875	{
		876	DMA-> CNFR \|= DMA_Enable ;
		877	}
		878
		879	else /* DISABLE the DMA peripheral */
		880	{
		881	DMA-> CNFR &= ~ DMA_Enable ;
		882	}
		883	}
		884
		885
		886
		887	/*******************************************************************************
		888	* Function Name : DMA_ChannelCmd
		889	* Description : Enables or disables the specified DMA_Channelx
		890	*
		891	* Input :
		892	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		893	* -NewState: new state of the specified DMA_Channelx mask interrupt.
		894	* This parameter can be: ENABLE or DISABLE.
		895	* Output : None.
		896	* Return : None.
		897	*******************************************************************************/
		898
		899
		900	void DMA_ChannelCmd (DMA_Channel_TypeDef *DMA_Channelx,FunctionalState NewState)
		901
		902	{
		903	if (NewState==ENABLE) /* Enable The Channelx */
		904
		905	{
		906	DMA_Channelx->CCNF \|= DMA_ChannelEnable ;
		907	}
		908
		909	else /* Disable The Channelx */
		910	{
		911	DMA_Channelx-> CCNF &= ~ DMA_ChannelEnable ;
		912	}
		913	}
		914
		915
		916
		917	/********************************************************************************
		918	* Function Name : DMA_GetChannelActiveStatus
		919	* Description : Checks The DMA_Channelx FIFO if it has data or not.
		920	* Input :
		921	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		922	*
		923	*
		924	* Output : None.
		925	*
		926	* Return : SET or RESET.
		927	*******************************************************************************/
		928
		929
		930	FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx )
		931
		932	{
		933
		934	if ( ( DMA_Channelx->CCNF & DMA_ChannelActive) != RESET )
		935	{
		936	return SET; /* The DMA_Channelx FIFO has data */
		937	}
		938
		939	else
		940
		941	{
		942
		943	return RESET; /* No data in the DMA_Channelx FIFO */
		944
		945
		946	}
		947
		948	}
		949
		950
		951	/********************************************************************************
		952	* Function Name : DMA_DeInit
		953	* Description : Initializes the DMA peripheral registers to their default reset values.
		954	*
		955	*
		956	* Input : None
		957	*
		958	* Output : None.
		959	*
		960	* Called Functions:
		961	*
		962	* - SCU_AHBPeriphReset: Function defined in the System clock Unit "scu.c".
		963	*
		964	*
		965	* Return : None
		966	*******************************************************************************/
		967
		968
		969	void DMA_DeInit(void)
		970
		971	{
		972
		973	SCU_AHBPeriphReset(__DMA, ENABLE); /DMA peripheral is under Reset " Reset on"/
		974	SCU_AHBPeriphReset(__DMA, DISABLE); /DMA peripheral Reset off/
		975	}
		976
		977
		978
		979	/********************************************************************************
		980	* Function Name : DMA_StructInit
		981	* Description : Fills each DMA_InitStruct member with its reset value.
		982	* Input :
		983	* -DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will be initialized.
		984	*
		985	* Output : None.
		986	*
		987	* Return : None
		988	*******************************************************************************/
		989
		990
		991	void DMA_StructInit(DMA_InitTypeDef * DMA_InitStruct)
		992
		993	{
		994
		995	/* Initialize The current source address */
		996	DMA_InitStruct-> DMA_Channel_SrcAdd =0x0000000;
		997
		998
		999	/* Initialize The current Destination address */
		1000	DMA_InitStruct->DMA_Channel_DesAdd=0x00000000;
		1001
		1002
		1003
		1004	/* Initialize The Linked List Items */
		1005	DMA_InitStruct->DMA_Channel_LLstItm=0x00000000 ;
		1006
		1007
		1008
		1009	/* Initialize The Destination width */
		1010	DMA_InitStruct->DMA_Channel_DesWidth= DMA_DesWidth_Byte;
		1011
		1012
		1013
		1014	/* Initialize The source width */
		1015	DMA_InitStruct->DMA_Channel_SrcWidth= DMA_SrcWidth_Byte;
		1016
		1017
		1018	/* Initialize The Burst Size for the Destination */
		1019	DMA_InitStruct->DMA_Channel_DesBstSize= DMA_DesBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the Destination width */
		1020
		1021
		1022
		1023	/* Initialize The Burst Size for the Source*/
		1024	DMA_InitStruct->DMA_Channel_SrcBstSize= DMA_SrcBst_1Data; /* 1 Data "one Data can be byte, halfword or word depending on the source width */
		1025
		1026	/* Initialize The Flow control and transfer type for the DMA transfer */
		1027	DMA_InitStruct->DMA_Channel_FlowCntrl=DMA_FlowCntrlt0_DMA; /* memory to memory transfer with DMA as flow controller */
		1028
		1029
		1030	/* Initialize The Transfer Size */
		1031	DMA_InitStruct->DMA_Channel_TrsfSize =0x00;
		1032
		1033
		1034
		1035	/* Initialize the DMA source request peripheral :"This field is ignored if the source of the transfer is from memory" */
		1036	DMA_InitStruct->DMA_Channel_Src =0x00;
		1037
		1038
		1039
		1040	/* Initialize the DMA Destination request peripheral :"This field is ignored if the destination of the transfer is to memory.*/
		1041
		1042	DMA_InitStruct->DMA_Channel_Des=0x00;
		1043
		1044
		1045	}
		1046
		1047
		1048
		1049
		1050	/********************************************************************************
		1051	* Function Name : DMA_Init
		1052	* Description : Initializes the DMA_Channelx according to the specified parameters
		1053	* in the DMA_InitStruct .
		1054	*
		1055	* Input :
		1056	* -DMA_Channelx: where x can be 0,1,2,3,4,5,6,or 7 to select the DMA Channel.
		1057	* -DMA_InitStruct: pointer to a DMA_InitTypeDef structure
		1058	* ( Structure Config to be load in DMA Registers). .
		1059	*
		1060	* Output : None.
		1061	*
		1062	* Return : None
		1063	*******************************************************************************/
		1064
		1065
		1066	void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct)
		1067
		1068	{
		1069
		1070
		1071
		1072	/* Select the DMA source peripheral request */
		1073	DMA_Channelx->CCNF &= SRC_Mask;
		1074	DMA_Channelx->CCNF \|= DMA_InitStruct->DMA_Channel_Src;
		1075
		1076
		1077	/* Select the flow controller and the transfer type */
		1078	DMA_Channelx->CCNF &= DMA_FlowCntrl_Mask;
		1079	DMA_Channelx->CCNF \|=DMA_InitStruct->DMA_Channel_FlowCntrl;
		1080
		1081
		1082	/* Select the DMA Destination peripheral request*/
		1083	DMA_Channelx->CCNF &= DES_Mask;
		1084	DMA_Channelx->CCNF \|= DMA_InitStruct->DMA_Channel_Des;
		1085
		1086	/* Set the source address */
		1087	DMA_Channelx->SRC = DMA_InitStruct-> DMA_Channel_SrcAdd ;
		1088
		1089
		1090	/* Set the destination address */
		1091
		1092	DMA_Channelx->DES = DMA_InitStruct->DMA_Channel_DesAdd ;
		1093
		1094
		1095
		1096	/* Set the linked list Items address */
		1097	DMA_Channelx->LLI = DMA_InitStruct->DMA_Channel_LLstItm ;
		1098
		1099
		1100	/* Set The Destination width */
		1101	DMA_Channelx->CC &= DMA_Width_DES_MASK;
		1102	DMA_Channelx->CC \|= DMA_InitStruct->DMA_Channel_DesWidth;
		1103
		1104
		1105	/* Set The Source width */
		1106	DMA_Channelx->CC &= DMA_Width_SRC_MASK;
		1107	DMA_Channelx->CC \|= DMA_InitStruct->DMA_Channel_SrcWidth;
		1108
		1109	/* Set The Burst Size for the Destination */
		1110	DMA_Channelx->CC &= DMA_Bst_DES_MASK;
		1111	DMA_Channelx->CC \|= DMA_InitStruct->DMA_Channel_DesBstSize;
		1112
		1113	/* Set The Burst Size for the Source */
		1114	DMA_Channelx->CC &= DMA_Bst_SRC_MASK;
		1115	DMA_Channelx->CC \|=DMA_InitStruct->DMA_Channel_SrcBstSize;
		1116
		1117
		1118	/* Initialize The Transfer Size for the Source */
		1119	DMA_Channelx->CC &= DMA_TrsfSisze_Mask;
		1120	DMA_Channelx->CC \|= DMA_InitStruct->DMA_Channel_TrsfSize;
		1121
		1122
		1123	}
		1124
		1125
		1126	/***************** (C) COPYRIGHT 2006 STMicroelectronics *END OF FILE**/

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(root)/tags/V0.15c/libstr91x/src/91x_dma.c - Rev 109