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1 | ingob | 1 | /******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** |
2 | * File Name : usb_regs.h |
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3 | * Author : MCD Application Team |
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4 | * Date First Issued : 10/27/2003 : V1.0 |
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5 | * Description : Interface prototype functions to USB cell registers |
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6 | ******************************************************************************** |
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7 | * History: |
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8 | * 09/18/2006 : V3.0 |
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9 | * 09/01/2006 : V2.0 |
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10 | * 10/27/2003 : V1.0 |
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11 | ******************************************************************************** |
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12 | * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
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13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
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14 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
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15 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
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16 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
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17 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
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18 | *******************************************************************************/ |
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19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
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20 | #ifndef __USB_REGS_H |
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21 | #define __USB_REGS_H |
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22 | /* Includes ------------------------------------------------------------------*/ |
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23 | /* Exported types ------------------------------------------------------------*/ |
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24 | |||
25 | typedef enum _EP_DBUF_DIR{ /* double buffered endpoint direction */ |
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26 | EP_DBUF_ERR, |
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27 | EP_DBUF_OUT, |
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28 | EP_DBUF_IN |
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29 | }EP_DBUF_DIR; |
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30 | |||
31 | /* endpoint buffer number */ |
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32 | enum EP_BUF_NUM{ |
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33 | EP_NOBUF, |
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34 | EP_BUF0, |
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35 | EP_BUF1 |
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36 | }; |
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37 | |||
38 | /* Exported constants --------------------------------------------------------*/ |
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39 | #ifdef STR7xx |
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40 | |||
41 | #ifdef STR71x /*STR71x family*/ |
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42 | #define RegBase (0xC0008800L) /* USB_IP Peripheral Registers base address */ |
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43 | #define PMAAddr (0xC0008000L) /* USB_IP Packet Memory Area base address */ |
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44 | #endif /*end of STR71x family*/ |
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45 | |||
46 | #ifdef STR75x /*STR75x family*/ |
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47 | #define RegBase (0xFFFFA800L) /* USB_IP Peripheral Registers base address */ |
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48 | #define PMAAddr (0xFFFFA000L) /* USB_IP Packet Memory Area base address */ |
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49 | #endif /*end of STR75x family*/ |
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50 | |||
51 | #endif /*end of STR7xx family*/ |
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52 | |||
53 | #ifdef STR91x /*STR91x family*/ |
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54 | |||
55 | #ifdef STR91x_USB_BUFFERED |
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56 | #define RegBase (0x60000800L) /* USB_IP Peripheral Registers base address */ |
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57 | #define PMAAddr (0x60000000L) /* USB_IP Packet Memory Area base address */ |
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58 | #endif |
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59 | |||
60 | #ifdef STR91x_USB_NON_BUFFERED |
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61 | #define RegBase (0x70000800L) /* USB_IP Peripheral Registers base address */ |
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62 | #define PMAAddr (0x70000000L) /* USB_IP Packet Memory Area base address */ |
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63 | #endif |
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64 | #endif |
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65 | |||
66 | /* General registers */ |
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67 | #define CNTR ((volatile unsigned *)(RegBase + 0x40)) /* Control register */ |
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68 | #define ISTR ((volatile unsigned *)(RegBase + 0x44)) /* Interrupt status register */ |
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69 | #define FNR ((volatile unsigned *)(RegBase + 0x48)) /* Frame number register */ |
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70 | #define DADDR ((volatile unsigned *)(RegBase + 0x4C)) /* Device address register */ |
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71 | #define BTABLE ((volatile unsigned *)(RegBase + 0x50)) /* Buffer Table address register */ |
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72 | |||
73 | #ifdef STR91x /*STR91x family DMA registers*/ |
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74 | |||
75 | #define DMACR1 ((volatile unsigned *)(RegBase + 0x54)) /* DMA control register 1 */ |
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76 | #define DMACR2 ((volatile unsigned *)(RegBase + 0x58)) /* DMA control register 2 */ |
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77 | #define DMACR3 ((volatile unsigned *)(RegBase + 0x5C)) /* DMA control register 3 */ |
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78 | #define DMABSIZE ((volatile unsigned *)(RegBase + 0x60))/* DMA burst size register */ |
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79 | #define DMALLI ((volatile unsigned *)(RegBase + 0x64)) /* DMA LLI register */ |
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80 | |||
81 | #endif |
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82 | |||
83 | /* Endpoint registers */ |
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84 | #define EP0REG ((volatile unsigned *)(RegBase)) /* endpoint 0 register address */ |
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85 | /* endpoints enumeration */ |
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86 | #define ENDP0 ((u8)0) |
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87 | #define ENDP1 ((u8)1) |
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88 | #define ENDP2 ((u8)2) |
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89 | #define ENDP3 ((u8)3) |
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90 | #define ENDP4 ((u8)4) |
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91 | #define ENDP5 ((u8)5) |
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92 | #define ENDP6 ((u8)6) |
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93 | #define ENDP7 ((u8)7) /* Only 8 endpoints for STR75x Family */ |
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94 | #define ENDP8 ((u8)8) |
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95 | #define ENDP9 ((u8)9) /* Only 10 endpoints for STR91x Family */ |
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96 | #define ENDP10 ((u8)10) |
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97 | #define ENDP11 ((u8)11) |
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98 | #define ENDP12 ((u8)12) |
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99 | #define ENDP13 ((u8)13) |
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100 | #define ENDP14 ((u8)14) |
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101 | #define ENDP15 ((u8)15) |
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102 | |||
103 | /*******************************************************************************/ |
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104 | /* ISTR interrupt events */ |
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105 | /*******************************************************************************/ |
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106 | #define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */ |
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107 | #define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */ |
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108 | #define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */ |
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109 | #define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */ |
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110 | #define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */ |
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111 | #define ISTR_RESET (0x0400) /* RESET (clear-only bit) */ |
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112 | #define ISTR_SOF (0x0200) /* Start Of Frame (clear-only bit) */ |
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113 | #define ISTR_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */ |
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114 | |||
115 | #ifdef STR91x /*STR91x family*/ |
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116 | #define ISTR_SZDPR (0x0080) /* Short or Zero-Length Received Data Packet */ |
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117 | #endif |
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118 | |||
119 | #define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */ |
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120 | #define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */ |
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121 | |||
122 | #define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */ |
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123 | #define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/ |
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124 | #define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */ |
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125 | #define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */ |
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126 | #define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */ |
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127 | #define CLR_RESET (~ISTR_RESET) /* clear RESET bit */ |
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128 | #define CLR_SOF (~ISTR_SOF) /* clear Start Of Frame bit */ |
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129 | #define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */ |
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130 | |||
131 | #ifdef STR91x /*STR91x family*/ |
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132 | #define CLR_SZDPR (~ISTR_SZDPR)/* clear SZDPR bit */ |
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133 | #endif |
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134 | |||
135 | /*******************************************************************************/ |
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136 | /* CNTR control register bits definitions */ |
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137 | /*******************************************************************************/ |
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138 | #define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */ |
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139 | #define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */ |
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140 | #define CNTR_ERRM (0x2000) /* ERRor Mask */ |
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141 | #define CNTR_WKUPM (0x1000) /* WaKe UP Mask */ |
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142 | #define CNTR_SUSPM (0x0800) /* SUSPend Mask */ |
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143 | #define CNTR_RESETM (0x0400) /* RESET Mask */ |
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144 | #define CNTR_SOFM (0x0200) /* Start Of Frame Mask */ |
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145 | #define CNTR_ESOFM (0x0100) /* Expected Start Of Frame Mask */ |
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146 | |||
147 | #ifdef STR91x /*STR91x family*/ |
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148 | #define CNTR_SZDPRM (0x0080) /* Short or Zero-Length Received Data Packet Mask*/ |
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149 | #endif |
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150 | |||
151 | #define CNTR_RESUME (0x0010) /* RESUME request */ |
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152 | #define CNTR_FSUSP (0x0008) /* Force SUSPend */ |
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153 | #define CNTR_LPMODE (0x0004) /* Low-power MODE */ |
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154 | #define CNTR_PDWN (0x0002) /* Power DoWN */ |
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155 | #define CNTR_FRES (0x0001) /* Force USB RESet */ |
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156 | |||
157 | /*******************************************************************************/ |
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158 | /* FNR Frame Number Register bit definitions */ |
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159 | /*******************************************************************************/ |
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160 | #define FNR_RXDP (0x8000) /* status of D+ data line */ |
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161 | #define FNR_RXDM (0x4000) /* status of D- data line */ |
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162 | #define FNR_LCK (0x2000) /* LoCKed */ |
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163 | #define FNR_LSOF (0x1800) /* Lost SOF */ |
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164 | #define FNR_FN (0x07FF) /* Frame Number */ |
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165 | /*******************************************************************************/ |
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166 | /* DADDR Device ADDRess bit definitions */ |
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167 | /*******************************************************************************/ |
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168 | #define DADDR_EF (0x80) |
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169 | #define DADDR_ADD (0x7F) |
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170 | /*===============================================================================*/ |
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171 | /* Endpoint register */ |
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172 | /*===============================================================================*/ |
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173 | /* bit positions */ |
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174 | #define EP_CTR_RX (0x8000) /* EndPoint Correct TRansfer RX */ |
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175 | #define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */ |
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176 | #define EPRX_STAT (0x3000) /* EndPoint RX STATus bit field */ |
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177 | #define EP_SETUP (0x0800) /* EndPoint SETUP */ |
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178 | #define EP_T_FIELD (0x0600) /* EndPoint TYPE */ |
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179 | #define EP_KIND (0x0100) /* EndPoint KIND */ |
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180 | #define EP_CTR_TX (0x0080) /* EndPoint Correct TRansfer TX */ |
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181 | #define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */ |
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182 | #define EPTX_STAT (0x0030) /* EndPoint TX STATus bit field */ |
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183 | #define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */ |
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184 | |||
185 | /* EndPoint REGister MASK (no toggle fields) */ |
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186 | #define EPREG_MASK (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD) |
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187 | |||
188 | /* EP_TYPE[1:0] EndPoint TYPE */ |
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189 | #define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */ |
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190 | #define EP_BULK (0x0000) /* EndPoint BULK */ |
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191 | #define EP_CONTROL (0x0200) /* EndPoint CONTROL */ |
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192 | #define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */ |
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193 | #define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */ |
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194 | #define EP_T_MASK (~EP_T_FIELD & EPREG_MASK) |
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195 | |||
196 | |||
197 | /* EP_KIND EndPoint KIND */ |
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198 | #define EPKIND_MASK (~EP_KIND & EPREG_MASK) |
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199 | |||
200 | /* STAT_TX[1:0] STATus for TX transfer */ |
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201 | #define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */ |
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202 | #define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */ |
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203 | #define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */ |
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204 | #define EP_TX_VALID (0x0030) /* EndPoint TX VALID */ |
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205 | #define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */ |
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206 | #define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */ |
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207 | #define EPTX_DTOGMASK (EPTX_STAT|EPREG_MASK) |
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208 | |||
209 | /* STAT_RX[1:0] STATus for RX transfer */ |
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210 | #define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */ |
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211 | #define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */ |
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212 | #define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */ |
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213 | #define EP_RX_VALID (0x3000) /* EndPoint RX VALID */ |
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214 | #define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */ |
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215 | #define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */ |
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216 | #define EPRX_DTOGMASK (EPRX_STAT|EPREG_MASK) |
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217 | |||
218 | /* Exported macro ------------------------------------------------------------*/ |
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219 | /*----------------------------------------------------------------*/ |
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220 | /* SetCNTR */ |
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221 | /*----------------------------------------------------------------*/ |
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222 | #define _SetCNTR(wRegValue) (*CNTR = (u16)wRegValue) |
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223 | /*----------------------------------------------------------------*/ |
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224 | /* SetISTR */ |
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225 | /*----------------------------------------------------------------*/ |
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226 | #define _SetISTR(wRegValue) (*ISTR = (u16)wRegValue) |
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227 | /*----------------------------------------------------------------*/ |
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228 | /* SetDADDR */ |
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229 | /*----------------------------------------------------------------*/ |
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230 | #define _SetDADDR(wRegValue) (*DADDR = (u16)wRegValue) |
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231 | /*----------------------------------------------------------------*/ |
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232 | /* SetBTABLE */ |
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233 | /*----------------------------------------------------------------*/ |
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234 | #define _SetBTABLE(wRegValue)(*BTABLE = (u16)(wRegValue & 0xFFF8)) |
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235 | /*----------------------------------------------------------------*/ |
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236 | /* GetCNTR */ |
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237 | /*----------------------------------------------------------------*/ |
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238 | #define _GetCNTR() ((u16) *CNTR) |
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239 | /*----------------------------------------------------------------*/ |
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240 | /* GetISTR */ |
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241 | /*----------------------------------------------------------------*/ |
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242 | #define _GetISTR() ((u16) *ISTR) |
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243 | /*----------------------------------------------------------------*/ |
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244 | /* GetFNR */ |
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245 | /*----------------------------------------------------------------*/ |
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246 | #define _GetFNR() ((u16) *FNR) |
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247 | /*----------------------------------------------------------------*/ |
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248 | /* GetDADDR */ |
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249 | /*----------------------------------------------------------------*/ |
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250 | #define _GetDADDR() ((u16) *DADDR) |
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251 | /*----------------------------------------------------------------*/ |
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252 | /* GetBTABLE */ |
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253 | /*----------------------------------------------------------------*/ |
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254 | #define _GetBTABLE() ((u16) *BTABLE) |
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255 | /*----------------------------------------------------------------*/ |
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256 | /* SetENDPOINT */ |
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257 | /*----------------------------------------------------------------*/ |
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258 | #define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \ |
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259 | (u16)wRegValue) |
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260 | /*----------------------------------------------------------------*/ |
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261 | /* GetENDPOINT */ |
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262 | /*----------------------------------------------------------------*/ |
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263 | #define _GetENDPOINT(bEpNum) ((u16)(*(EP0REG + bEpNum))) |
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264 | /*----------------------------------------------------------------*/ |
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265 | /* SetEPType */ |
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266 | /* sets the type in the endpoint register(bits EP_TYPE[1:0]) */ |
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267 | /* IN : bEpNum = endpoint number */ |
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268 | /* wType = type definition */ |
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269 | /* OUT: none */ |
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270 | /*----------------------------------------------------------------*/ |
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271 | #define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\ |
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272 | ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType))) |
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273 | /*----------------------------------------------------------------*/ |
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274 | /* GetEPType */ |
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275 | /* gets the type in the endpoint register(bits EP_TYPE[1:0]) */ |
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276 | /* IN : bEpNum = endpoint number */ |
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277 | /* OUT: type definition */ |
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278 | /*----------------------------------------------------------------*/ |
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279 | #define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD) |
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280 | /*----------------------------------------------------------------*/ |
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281 | /* SetEPTxStatus */ |
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282 | /* sets the status for tx transfer (bits STAT_TX[1:0]) */ |
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283 | /* IN : bEpNum = endpoint number */ |
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284 | /* wState = new state */ |
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285 | /* OUT: none */ |
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286 | /*----------------------------------------------------------------*/ |
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287 | #define _SetEPTxStatus(bEpNum,wState) {\ |
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288 | register u16 _wRegVal; \ |
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289 | _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\ |
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290 | /* toggle first bit ? */ \ |
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291 | if((EPTX_DTOG1 & wState)!= 0) \ |
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292 | _wRegVal ^= EPTX_DTOG1; \ |
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293 | /* toggle second bit ? */ \ |
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294 | if((EPTX_DTOG2 & wState)!= 0) \ |
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295 | _wRegVal ^= EPTX_DTOG2; \ |
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296 | _SetENDPOINT(bEpNum, _wRegVal); \ |
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297 | } /* _SetEPTxStatus */ |
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298 | |||
299 | /*----------------------------------------------------------------*/ |
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300 | /* SetEPRxStatus */ |
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301 | /* sets the status for rx transfer (bits STAT_TX[1:0]) */ |
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302 | /* IN : bEpNum = endpoint number */ |
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303 | /* wState = new state */ |
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304 | /* OUT: none */ |
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305 | /*----------------------------------------------------------------*/ |
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306 | #define _SetEPRxStatus(bEpNum,wState) {\ |
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307 | register u16 _wRegVal; \ |
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308 | \ |
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309 | _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\ |
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310 | /* toggle first bit ? */ \ |
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311 | if((EPRX_DTOG1 & wState)!= 0) \ |
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312 | _wRegVal ^= EPRX_DTOG1; \ |
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313 | /* toggle second bit ? */ \ |
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314 | if((EPRX_DTOG2 & wState)!= 0) \ |
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315 | _wRegVal ^= EPRX_DTOG2; \ |
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316 | _SetENDPOINT(bEpNum, _wRegVal); \ |
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317 | } /* _SetEPRxStatus */ |
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318 | /*----------------------------------------------------------------*/ |
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319 | /* GetEPTxStatus / GetEPRxStatus */ |
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320 | /* gets the status for tx/rx transfer (bits STAT_TX[1:0]/STAT_RX[1:0]) */ |
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321 | /* IN : bEpNum = endpoint number */ |
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322 | /* OUT: u16 status */ |
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323 | /*----------------------------------------------------------------*/ |
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324 | #define _GetEPTxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPTX_STAT) |
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325 | #define _GetEPRxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPRX_STAT) |
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326 | /*----------------------------------------------------------------*/ |
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327 | /* SetEPTxValid / SetEPRxValid */ |
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328 | /* sets directly the VALID tx/rx-status into the enpoint register */ |
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329 | /* IN : bEpNum = endpoint number */ |
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330 | /* OUT: none */ |
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331 | /*----------------------------------------------------------------*/ |
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332 | #define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID)) |
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333 | #define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID)) |
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334 | /*----------------------------------------------------------------*/ |
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335 | /* GetTxStallStatus / GetRxStallStatus */ |
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336 | /* checks stall condition in an endpoint */ |
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337 | /* IN : bEpNum = endpoint number */ |
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338 | /* OUT: TRUE = endpoint in stall condition */ |
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339 | /*----------------------------------------------------------------*/ |
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340 | #define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \ |
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341 | == EP_TX_STALL) |
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342 | #define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \ |
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343 | == EP_RX_STALL) |
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344 | /*----------------------------------------------------------------*/ |
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345 | /* SetEP_KIND / ClearEP_KIND */ |
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346 | /* IN : bEpNum = endpoint number */ |
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347 | /* OUT: none */ |
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348 | /*----------------------------------------------------------------*/ |
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349 | #define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ |
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350 | (_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK)) |
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351 | #define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ |
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352 | (_GetENDPOINT(bEpNum) & EPKIND_MASK))) |
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353 | /*----------------------------------------------------------------*/ |
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354 | /* Set_Status_Out / Clear_Status_Out */ |
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355 | /* sets/clears directly STATUS_OUT bit in the endpoint register */ |
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356 | /* to be used only during control transfers */ |
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357 | /* IN : bEpNum = endpoint number */ |
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358 | /* OUT: none */ |
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359 | /*----------------------------------------------------------------*/ |
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360 | #define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum) |
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361 | #define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum) |
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362 | /*----------------------------------------------------------------*/ |
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363 | /* SetEPDoubleBuff / ClearEPDoubleBuff */ |
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364 | /* sets/clears directly EP_KIND bit in the endpoint register */ |
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365 | /* IN : bEpNum = endpoint number */ |
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366 | /* OUT: none */ |
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367 | /*----------------------------------------------------------------*/ |
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368 | #define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum) |
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369 | #define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum) |
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370 | /*----------------------------------------------------------------*/ |
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371 | /* ClearEP_CTR_RX / ClearEP_CTR_TX */ |
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372 | /* clears bit CTR_RX / CTR_TX in the endpoint register */ |
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373 | /* IN : bEpNum = endpoint number */ |
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374 | /* OUT: none */ |
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375 | /*----------------------------------------------------------------*/ |
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376 | #define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum,\ |
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377 | _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK)) |
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378 | #define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum,\ |
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379 | _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK)) |
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380 | /*----------------------------------------------------------------*/ |
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381 | /* ToggleDTOG_RX / ToggleDTOG_TX */ |
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382 | /* toggles DTOG_RX / DTOG_TX bit in the endpoint register */ |
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383 | /* IN : bEpNum = endpoint number */ |
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384 | /* OUT: none */ |
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385 | /*----------------------------------------------------------------*/ |
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386 | #define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \ |
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387 | EP_DTOG_RX | _GetENDPOINT(bEpNum) & EPREG_MASK)) |
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388 | #define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \ |
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389 | EP_DTOG_TX | _GetENDPOINT(bEpNum) & EPREG_MASK)) |
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390 | /*----------------------------------------------------------------*/ |
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391 | /* ClearDTOG_RX / ClearDTOG_TX */ |
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392 | /* IN : bEpNum = endpoint number */ |
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393 | /* OUT: none */ |
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394 | /*----------------------------------------------------------------*/ |
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395 | #define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\ |
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396 | _ToggleDTOG_RX(bEpNum) |
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397 | #define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\ |
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398 | _ToggleDTOG_TX(bEpNum) |
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399 | /*----------------------------------------------------------------*/ |
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400 | /* SetEPAddress */ |
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401 | /* sets address in an endpoint register */ |
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402 | /* IN : bEpNum = endpoint number */ |
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403 | /* bAddr = address */ |
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404 | /* OUT: none */ |
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405 | /*----------------------------------------------------------------*/ |
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406 | |||
407 | #define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\ |
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408 | _GetENDPOINT(bEpNum) & EPREG_MASK | bAddr) |
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409 | /*----------------------------------------------------------------*/ |
||
410 | /* GetEPAddress */ |
||
411 | /* IN : bEpNum = endpoint number */ |
||
412 | /* OUT: none */ |
||
413 | /*----------------------------------------------------------------*/ |
||
414 | #define _GetEPAddress(bEpNum) ((u8)(_GetENDPOINT(bEpNum) & EPADDR_FIELD)) |
||
415 | /*----------------------------------------------------------------*/ |
||
416 | #ifdef STR7xx /*STR7xx family*/ |
||
417 | #define _pEPTxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8 )*2 + PMAAddr)) |
||
418 | #define _pEPTxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr)) |
||
419 | #define _pEPRxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr)) |
||
420 | #define _pEPRxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr)) |
||
421 | #endif |
||
422 | |||
423 | #ifdef STR91x /*STR91x family*/ |
||
424 | /* Pointers on endpoint(bEpNum) Count & Addr registers on PMA */ |
||
425 | #define _pEPBufCount(bEpNum) ((u32 *)(_GetBTABLE()+bEpNum*8 + 4 + PMAAddr)) |
||
426 | #define _pEPBufAddr(bEpNum) ((u32 *)(_GetBTABLE()+bEpNum*8 + PMAAddr)) |
||
427 | #endif |
||
428 | /*----------------------------------------------------------------*/ |
||
429 | /* SetEPTxAddr / SetEPRxAddr */ |
||
430 | /* sets address of the tx/rx buffer */ |
||
431 | /* IN : bEpNum = endpoint number */ |
||
432 | /* wAddr = address to be set ( must be word aligned ) */ |
||
433 | /* OUT: none */ |
||
434 | /*----------------------------------------------------------------*/ |
||
435 | |||
436 | #ifdef STR7xx /*STR7xx family*/ |
||
437 | #define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1)) |
||
438 | #define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1)) |
||
439 | #endif |
||
440 | |||
441 | #ifdef STR91x /*STR91x family*/ |
||
442 | #define _SetEPTxAddr(bEpNum , wAddr) {\ |
||
443 | *_pEPBufAddr(bEpNum) &=0xFFFF0000; \ |
||
444 | *_pEPBufAddr(bEpNum) |=((wAddr)&0x0FFFC);\ |
||
445 | } |
||
446 | #define _SetEPRxAddr(bEpNum, wAddr) {\ |
||
447 | *_pEPBufAddr(bEpNum) &=0x0000FFFF;\ |
||
448 | *_pEPBufAddr(bEpNum) |=((wAddr<<16)&0xFFFC0000);\ |
||
449 | } |
||
450 | #endif |
||
451 | |||
452 | /*----------------------------------------------------------------*/ |
||
453 | /* GetEPTxAddr / GetEPRxAddr */ |
||
454 | /* gets address of the tx/rx buffer */ |
||
455 | /* IN : bEpNum = endpoint number */ |
||
456 | /* IN : */ |
||
457 | /* OUT: address of the buffer */ |
||
458 | /*----------------------------------------------------------------*/ |
||
459 | |||
460 | #ifdef STR7xx /*STR7xx family*/ |
||
461 | #define _GetEPTxAddr(bEpNum) ((u16)*_pEPTxAddr(bEpNum)) |
||
462 | #define _GetEPRxAddr(bEpNum) ((u16)*_pEPRxAddr(bEpNum)) |
||
463 | #endif |
||
464 | |||
465 | #ifdef STR91x /*STR91x family*/ |
||
466 | #define _GetEPTxAddr(bEpNum) ((u16)(*_pEPBufAddr(bEpNum) &0x0000FFFF)) |
||
467 | #define _GetEPRxAddr(bEpNum) ((u16)((*_pEPBufAddr(bEpNum)&0xFFFF0000)>>16)) |
||
468 | #endif |
||
469 | /*----------------------------------------------------------------*/ |
||
470 | /* SetEPCountRxReg */ |
||
471 | /* sets counter of rx buffer with no. of blocks */ |
||
472 | /* IN : pdwReg = pointer to counter */ |
||
473 | /* wCount = counter */ |
||
474 | /* OUT: none */ |
||
475 | /*----------------------------------------------------------------*/ |
||
476 | |||
477 | #ifdef STR7xx /*STR7xx family*/ |
||
478 | #define _BlocksOf32(dwReg,wCount,wNBlocks) {\ |
||
479 | wNBlocks = wCount >> 5;\ |
||
480 | if((wCount & 0x1f) == 0)\ |
||
481 | wNBlocks--;\ |
||
482 | *pdwReg = (u32)((wNBlocks << 10) | 0x8000);\ |
||
483 | }/* _BlocksOf32 */ |
||
484 | |||
485 | #define _BlocksOf2(dwReg,wCount,wNBlocks) {\ |
||
486 | wNBlocks = wCount >> 1;\ |
||
487 | if((wCount & 0x1) != 0)\ |
||
488 | wNBlocks++;\ |
||
489 | *pdwReg = (u32)(wNBlocks << 10);\ |
||
490 | }/* _BlocksOf2 */ |
||
491 | |||
492 | #define _SetEPCountRxReg(dwReg,wCount) {\ |
||
493 | u16 wNBlocks;\ |
||
494 | if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\ |
||
495 | else {_BlocksOf2(dwReg,wCount,wNBlocks);}\ |
||
496 | }/* _SetEPCountRxReg */ |
||
497 | |||
498 | |||
499 | |||
500 | #define _SetEPRxDblBuf0Count(bEpNum,wCount) {\ |
||
501 | u32 *pdwReg = _pEPTxCount(bEpNum); \ |
||
502 | _SetEPCountRxReg(pdwReg, wCount);\ |
||
503 | } |
||
504 | #endif |
||
505 | /*----------------------------------------------------------------*/ |
||
506 | /* SetEPTxCount / SetEPRxCount */ |
||
507 | /* sets counter for the tx/rx buffer */ |
||
508 | /* IN : bEpNum = endpoint number */ |
||
509 | /* wCount = counter value */ |
||
510 | /* OUT: none */ |
||
511 | /*----------------------------------------------------------------*/ |
||
512 | |||
513 | #ifdef STR7xx /*STR7xx family*/ |
||
514 | #define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount) |
||
515 | #define _SetEPRxCount(bEpNum,wCount) {\ |
||
516 | u32 *pdwReg = _pEPRxCount(bEpNum); \ |
||
517 | _SetEPCountRxReg(pdwReg, wCount);\ |
||
518 | } |
||
519 | #endif |
||
520 | |||
521 | #ifdef STR91x /*STR91x family*/ |
||
522 | #define _SetEPTxCount(bEpNum,wCount) {\ |
||
523 | *_pEPBufCount(bEpNum) &=0xFFFFFC00;\ |
||
524 | *_pEPBufCount(bEpNum) |=wCount;\ |
||
525 | } |
||
526 | |||
527 | #define _SetEPRxCount(bEpNum,wCount) {\ |
||
528 | u32 BLsize=0;\ |
||
529 | u32 Blocks;\ |
||
530 | if (wCount < 64) Blocks = wCount>>1;\ |
||
531 | else\ |
||
532 | {\ |
||
533 | BLsize = 0x80000000;\ |
||
534 | Blocks = wCount>>6;\ |
||
535 | }\ |
||
536 | *_pEPBufCount(bEpNum) &=~0x80000000;\ |
||
537 | *_pEPBufCount(bEpNum) |=BLsize;\ |
||
538 | *_pEPBufCount(bEpNum) &=0x83FFFFFF;\ |
||
539 | *_pEPBufCount(bEpNum) |=Blocks<<26;\ |
||
540 | *_pEPBufCount(bEpNum) &=0xFC00FFFF;\ |
||
541 | } |
||
542 | #endif |
||
543 | /*----------------------------------------------------------------*/ |
||
544 | /* GetEPTxCount / GetEPRxCount */ |
||
545 | /* gets counter of the tx buffer */ |
||
546 | /* IN : bEpNum = endpoint number */ |
||
547 | /* OUT: counter value */ |
||
548 | /*----------------------------------------------------------------*/ |
||
549 | #ifdef STR7xx /*STR7xx family*/ |
||
550 | #define _GetEPTxCount(bEpNum)((u16)(*_pEPTxCount(bEpNum)) & 0x3ff) |
||
551 | #define _GetEPRxCount(bEpNum)((u16)(*_pEPRxCount(bEpNum)) & 0x3ff) |
||
552 | #endif |
||
553 | |||
554 | #ifdef STR91x /*STR91x family*/ |
||
555 | #define _GetEPTxCount(bEpNum) (u16)(*_pEPBufCount(bEpNum)&0x3FF) |
||
556 | #define _GetEPRxCount(bEpNum) (u16)((*_pEPBufCount(bEpNum)&0x3FF0000)>>16) |
||
557 | #endif |
||
558 | /*----------------------------------------------------------------*/ |
||
559 | /* SetEPDblBuf0Addr / SetEPDblBuf1Addr */ |
||
560 | /* sets buffer 0/1 address in a double buffer endpoint */ |
||
561 | /* IN : bEpNum = endpoint number */ |
||
562 | /* wBuf0Addr = buffer 0 address */ |
||
563 | /* OUT: none */ |
||
564 | /*----------------------------------------------------------------*/ |
||
565 | #define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);} |
||
566 | #define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);} |
||
567 | |||
568 | /*----------------------------------------------------------------*/ |
||
569 | /* SetEPDblBuffAddr */ |
||
570 | /* sets addresses in a double buffer endpoint */ |
||
571 | /* IN : bEpNum = endpoint number */ |
||
572 | /* wBuf0Addr = buffer 0 address */ |
||
573 | /* wBuf1Addr = buffer 1 address */ |
||
574 | /* OUT: none */ |
||
575 | /*----------------------------------------------------------------*/ |
||
576 | #define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \ |
||
577 | _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\ |
||
578 | _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\ |
||
579 | } /* _SetEPDblBuffAddr */ |
||
580 | /*----------------------------------------------------------------*/ |
||
581 | /* GetEPDblBuf0Addr / GetEPDblBuf1Addr */ |
||
582 | /* gets buffer 0/1 address of a double buffer endpoint */ |
||
583 | /* IN : bEpNum = endpoint number */ |
||
584 | /* OUT: none */ |
||
585 | /*----------------------------------------------------------------*/ |
||
586 | #define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum)) |
||
587 | #define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum)) |
||
588 | /*----------------------------------------------------------------*/ |
||
589 | /* SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count */ |
||
590 | /* sets both buffers or buff0 or buff1 counter for double buffering */ |
||
591 | /* IN : bEpNum = endpoint number */ |
||
592 | /* bDir = endpoint dir EP_DBUF_OUT = OUT */ |
||
593 | /* EP_DBUF_IN = IN */ |
||
594 | /* wCount = counter value */ |
||
595 | /* OUT: none */ |
||
596 | /*----------------------------------------------------------------*/ |
||
597 | |||
598 | #ifdef STR7xx /*STR7xx family*/ |
||
599 | |||
600 | #define _SetEPDblBuf0Count(bEpNum, bDir, wCount) { \ |
||
601 | if(bDir == EP_DBUF_OUT)\ |
||
602 | /* OUT endpoint */ \ |
||
603 | {_SetEPRxDblBuf0Count(bEpNum,wCount);} \ |
||
604 | else if(bDir == EP_DBUF_IN)\ |
||
605 | /* IN endpoint */ \ |
||
606 | *_pEPTxCount(bEpNum) = (u32)wCount; \ |
||
607 | } /* SetEPDblBuf0Count*/ |
||
608 | |||
609 | #define _SetEPDblBuf1Count(bEpNum, bDir, wCount) { \ |
||
610 | if(bDir == EP_DBUF_OUT)\ |
||
611 | /* OUT endpoint */ \ |
||
612 | {_SetEPRxCount(bEpNum,wCount);}\ |
||
613 | else if(bDir == EP_DBUF_IN)\ |
||
614 | /* IN endpoint */\ |
||
615 | *_pEPRxCount(bEpNum) = (u32)wCount; \ |
||
616 | } /* SetEPDblBuf1Count */ |
||
617 | |||
618 | #define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\ |
||
619 | _SetEPDblBuf0Count(bEpNum, bDir, wCount); \ |
||
620 | _SetEPDblBuf1Count(bEpNum, bDir, wCount); \ |
||
621 | } /* _SetEPDblBuffCount */ |
||
622 | #endif |
||
623 | /*----------------------------------------------------------------*/ |
||
624 | /* GetEPDblBuf0Count / GetEPDblBuf1Count */ |
||
625 | /* gets buffer 0/1 rx/tx counter for double buffering */ |
||
626 | /* IN : bEpNum = endpoint number */ |
||
627 | /* OUT: none */ |
||
628 | /*----------------------------------------------------------------*/ |
||
629 | #define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum)) |
||
630 | #define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum)) |
||
631 | |||
632 | |||
633 | /* External variables --------------------------------------------------------*/ |
||
634 | extern volatile u16 wIstr; /* ISTR register last read value */ |
||
635 | |||
636 | /* Exported functions ------------------------------------------------------- */ |
||
637 | void SetCNTR(u16 /*wRegValue*/); |
||
638 | void SetISTR(u16 /*wRegValue*/); |
||
639 | void SetDADDR(u16 /*wRegValue*/); |
||
640 | void SetBTABLE(u16 /*wRegValue*/); |
||
641 | void SetBTABLE(u16 /*wRegValue*/); |
||
642 | u16 GetCNTR(void); |
||
643 | u16 GetISTR(void); |
||
644 | u16 GetFNR(void); |
||
645 | u16 GetDADDR(void); |
||
646 | u16 GetBTABLE(void); |
||
647 | void SetENDPOINT(u8 /*bEpNum*/,u16 /*wRegValue*/); |
||
648 | u16 GetENDPOINT(u8 /*bEpNum*/); |
||
649 | void SetEPType(u8 /*bEpNum*/,u16 /*wType*/); |
||
650 | u16 GetEPType(u8 /*bEpNum*/); |
||
651 | void SetEPTxStatus(u8 /*bEpNum*/,u16 /*wState*/); |
||
652 | void SetEPRxStatus(u8 /*bEpNum*/,u16 /*wState*/); |
||
653 | void SetDouBleBuffEPStall(u8 /*bEpNum*/,u8 bDir); |
||
654 | u16 GetEPTxStatus(u8 /*bEpNum*/); |
||
655 | u16 GetEPRxStatus(u8 /*bEpNum*/); |
||
656 | void SetEPTxValid(u8 /*bEpNum*/); |
||
657 | void SetEPRxValid(u8 /*bEpNum*/); |
||
658 | u16 GetTxStallStatus(u8 /*bEpNum*/); |
||
659 | u16 GetRxStallStatus(u8 /*bEpNum*/); |
||
660 | void SetEP_KIND(u8 /*bEpNum*/); |
||
661 | void ClearEP_KIND(u8 /*bEpNum*/); |
||
662 | void Set_Status_Out(u8 /*bEpNum*/); |
||
663 | void Clear_Status_Out(u8 /*bEpNum*/); |
||
664 | void SetEPDoubleBuff(u8 /*bEpNum*/); |
||
665 | void ClearEPDoubleBuff(u8 /*bEpNum*/); |
||
666 | void ClearEP_CTR_RX(u8 /*bEpNum*/); |
||
667 | void ClearEP_CTR_TX(u8 /*bEpNum*/); |
||
668 | void ToggleDTOG_RX(u8 /*bEpNum*/); |
||
669 | void ToggleDTOG_TX(u8 /*bEpNum*/); |
||
670 | void ClearDTOG_RX(u8 /*bEpNum*/); |
||
671 | void ClearDTOG_TX(u8 /*bEpNum*/); |
||
672 | void SetEPAddress(u8 /*bEpNum*/,u8 /*bAddr*/); |
||
673 | u8 GetEPAddress(u8 /*bEpNum*/); |
||
674 | void SetEPTxAddr(u8 /*bEpNum*/,u16 /*wAddr*/); |
||
675 | void SetEPRxAddr(u8 /*bEpNum*/,u16 /*wAddr*/); |
||
676 | u16 GetEPTxAddr(u8 /*bEpNum*/); |
||
677 | u16 GetEPRxAddr(u8 /*bEpNum*/); |
||
678 | void SetEPCountRxReg(u32 * /*pdwReg*/, u16 /*wCount*/); |
||
679 | void SetEPTxCount(u8 /*bEpNum*/,u16 /*wCount*/); |
||
680 | void SetEPRxCount(u8 /*bEpNum*/,u16 /*wCount*/); |
||
681 | u16 GetEPTxCount(u8 /*bEpNum*/); |
||
682 | u16 GetEPRxCount(u8 /*bEpNum*/); |
||
683 | void SetEPDblBuf0Addr(u8 /*bEpNum*/,u16 /*wBuf0Addr*/); |
||
684 | void SetEPDblBuf1Addr(u8 /*bEpNum*/,u16 /*wBuf1Addr*/); |
||
685 | void SetEPDblBuffAddr(u8 /*bEpNum*/,u16 /*wBuf0Addr*/,u16 /*wBuf1Addr*/); |
||
686 | u16 GetEPDblBuf0Addr(u8 /*bEpNum*/); |
||
687 | u16 GetEPDblBuf1Addr(u8 /*bEpNum*/); |
||
688 | void SetEPDblBuffCount(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
||
689 | void SetEPDblBuf0Count(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
||
690 | void SetEPDblBuf1Count(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
||
691 | u16 GetEPDblBuf0Count(u8 /*bEpNum*/); |
||
692 | u16 GetEPDblBuf1Count(u8 /*bEpNum*/); |
||
693 | EP_DBUF_DIR GetEPDblBufDir(u8 /*bEpNum*/); |
||
694 | void FreeUserBuffer(u8 bEpNum/*bEpNum*/,u8 bDir); |
||
695 | u16 ToWord(u8,u8); |
||
696 | u16 ByteSwap(u16); |
||
697 | |||
698 | #ifdef STR91x /*STR91x family*/ |
||
699 | /* DMA Functions */ |
||
700 | void SetDMABurstTxSize(u8 /*DestBsize*/); |
||
701 | void SetDMABurstRxSize(u8 /*SrcBsize*/); |
||
702 | void DMAUnlinkedModeTxConfig(u8 /*bEpNum*/ ,u8 /*index*/); |
||
703 | void DMAUnlinkedModeTxEnable(u8 /*index*/); |
||
704 | void DMAUnlinkedModeTxDisable(u8 /*index*/); |
||
705 | void DMAUnlinkedModeRxEnable(u8 /*bEpNum*/); |
||
706 | void DMAUnlinkedModeRxDisable(u8 /*bEpNum*/); |
||
707 | void DMALinkedModeRxConfig(u8 /*bEpNum*/); |
||
708 | void DMALinkedModeTxConfig(u8 /*bEpNum*/); |
||
709 | void DMALinkedModeRxEnable(void); |
||
710 | void DMALinkedModeTxEnable(void); |
||
711 | void DMALinkedModeRxDisable(void); |
||
712 | void DMALinkedModeTxDisable(void); |
||
713 | void DMASynchEnable(void); |
||
714 | void DMASynchDisable(void); |
||
715 | void SetDMALLITxLength(u8 /*length*/); |
||
716 | void SetDMALLIRxLength(u8 /*length*/ ); |
||
717 | void SetDMALLIRxPacketNum(u8 /*PacketNum*/); |
||
718 | u8 GetDMALLIRxPacketNum(void); |
||
719 | #endif /* End of STR91x family*/ |
||
720 | |||
721 | #endif /* __USB_REGS_H */ |
||
722 | |||
723 | |||
724 | /******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ |