Go to most recent revision | Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1 | ingob | 1 | /******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** |
| 2 | * File Name : usb_regs.h |
||
| 3 | * Author : MCD Application Team |
||
| 4 | * Date First Issued : 10/27/2003 : V1.0 |
||
| 5 | * Description : Interface prototype functions to USB cell registers |
||
| 6 | ******************************************************************************** |
||
| 7 | * History: |
||
| 8 | * 09/18/2006 : V3.0 |
||
| 9 | * 09/01/2006 : V2.0 |
||
| 10 | * 10/27/2003 : V1.0 |
||
| 11 | ******************************************************************************** |
||
| 12 | * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||
| 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
||
| 14 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
||
| 15 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
||
| 16 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
||
| 17 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||
| 18 | *******************************************************************************/ |
||
| 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
||
| 20 | #ifndef __USB_REGS_H |
||
| 21 | #define __USB_REGS_H |
||
| 22 | /* Includes ------------------------------------------------------------------*/ |
||
| 23 | /* Exported types ------------------------------------------------------------*/ |
||
| 24 | |||
| 25 | typedef enum _EP_DBUF_DIR{ /* double buffered endpoint direction */ |
||
| 26 | EP_DBUF_ERR, |
||
| 27 | EP_DBUF_OUT, |
||
| 28 | EP_DBUF_IN |
||
| 29 | }EP_DBUF_DIR; |
||
| 30 | |||
| 31 | /* endpoint buffer number */ |
||
| 32 | enum EP_BUF_NUM{ |
||
| 33 | EP_NOBUF, |
||
| 34 | EP_BUF0, |
||
| 35 | EP_BUF1 |
||
| 36 | }; |
||
| 37 | |||
| 38 | /* Exported constants --------------------------------------------------------*/ |
||
| 39 | #ifdef STR7xx |
||
| 40 | |||
| 41 | #ifdef STR71x /*STR71x family*/ |
||
| 42 | #define RegBase (0xC0008800L) /* USB_IP Peripheral Registers base address */ |
||
| 43 | #define PMAAddr (0xC0008000L) /* USB_IP Packet Memory Area base address */ |
||
| 44 | #endif /*end of STR71x family*/ |
||
| 45 | |||
| 46 | #ifdef STR75x /*STR75x family*/ |
||
| 47 | #define RegBase (0xFFFFA800L) /* USB_IP Peripheral Registers base address */ |
||
| 48 | #define PMAAddr (0xFFFFA000L) /* USB_IP Packet Memory Area base address */ |
||
| 49 | #endif /*end of STR75x family*/ |
||
| 50 | |||
| 51 | #endif /*end of STR7xx family*/ |
||
| 52 | |||
| 53 | #ifdef STR91x /*STR91x family*/ |
||
| 54 | |||
| 55 | #ifdef STR91x_USB_BUFFERED |
||
| 56 | #define RegBase (0x60000800L) /* USB_IP Peripheral Registers base address */ |
||
| 57 | #define PMAAddr (0x60000000L) /* USB_IP Packet Memory Area base address */ |
||
| 58 | #endif |
||
| 59 | |||
| 60 | #ifdef STR91x_USB_NON_BUFFERED |
||
| 61 | #define RegBase (0x70000800L) /* USB_IP Peripheral Registers base address */ |
||
| 62 | #define PMAAddr (0x70000000L) /* USB_IP Packet Memory Area base address */ |
||
| 63 | #endif |
||
| 64 | #endif |
||
| 65 | |||
| 66 | /* General registers */ |
||
| 67 | #define CNTR ((volatile unsigned *)(RegBase + 0x40)) /* Control register */ |
||
| 68 | #define ISTR ((volatile unsigned *)(RegBase + 0x44)) /* Interrupt status register */ |
||
| 69 | #define FNR ((volatile unsigned *)(RegBase + 0x48)) /* Frame number register */ |
||
| 70 | #define DADDR ((volatile unsigned *)(RegBase + 0x4C)) /* Device address register */ |
||
| 71 | #define BTABLE ((volatile unsigned *)(RegBase + 0x50)) /* Buffer Table address register */ |
||
| 72 | |||
| 73 | #ifdef STR91x /*STR91x family DMA registers*/ |
||
| 74 | |||
| 75 | #define DMACR1 ((volatile unsigned *)(RegBase + 0x54)) /* DMA control register 1 */ |
||
| 76 | #define DMACR2 ((volatile unsigned *)(RegBase + 0x58)) /* DMA control register 2 */ |
||
| 77 | #define DMACR3 ((volatile unsigned *)(RegBase + 0x5C)) /* DMA control register 3 */ |
||
| 78 | #define DMABSIZE ((volatile unsigned *)(RegBase + 0x60))/* DMA burst size register */ |
||
| 79 | #define DMALLI ((volatile unsigned *)(RegBase + 0x64)) /* DMA LLI register */ |
||
| 80 | |||
| 81 | #endif |
||
| 82 | |||
| 83 | /* Endpoint registers */ |
||
| 84 | #define EP0REG ((volatile unsigned *)(RegBase)) /* endpoint 0 register address */ |
||
| 85 | /* endpoints enumeration */ |
||
| 86 | #define ENDP0 ((u8)0) |
||
| 87 | #define ENDP1 ((u8)1) |
||
| 88 | #define ENDP2 ((u8)2) |
||
| 89 | #define ENDP3 ((u8)3) |
||
| 90 | #define ENDP4 ((u8)4) |
||
| 91 | #define ENDP5 ((u8)5) |
||
| 92 | #define ENDP6 ((u8)6) |
||
| 93 | #define ENDP7 ((u8)7) /* Only 8 endpoints for STR75x Family */ |
||
| 94 | #define ENDP8 ((u8)8) |
||
| 95 | #define ENDP9 ((u8)9) /* Only 10 endpoints for STR91x Family */ |
||
| 96 | #define ENDP10 ((u8)10) |
||
| 97 | #define ENDP11 ((u8)11) |
||
| 98 | #define ENDP12 ((u8)12) |
||
| 99 | #define ENDP13 ((u8)13) |
||
| 100 | #define ENDP14 ((u8)14) |
||
| 101 | #define ENDP15 ((u8)15) |
||
| 102 | |||
| 103 | /*******************************************************************************/ |
||
| 104 | /* ISTR interrupt events */ |
||
| 105 | /*******************************************************************************/ |
||
| 106 | #define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */ |
||
| 107 | #define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */ |
||
| 108 | #define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */ |
||
| 109 | #define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */ |
||
| 110 | #define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */ |
||
| 111 | #define ISTR_RESET (0x0400) /* RESET (clear-only bit) */ |
||
| 112 | #define ISTR_SOF (0x0200) /* Start Of Frame (clear-only bit) */ |
||
| 113 | #define ISTR_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */ |
||
| 114 | |||
| 115 | #ifdef STR91x /*STR91x family*/ |
||
| 116 | #define ISTR_SZDPR (0x0080) /* Short or Zero-Length Received Data Packet */ |
||
| 117 | #endif |
||
| 118 | |||
| 119 | #define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */ |
||
| 120 | #define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */ |
||
| 121 | |||
| 122 | #define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */ |
||
| 123 | #define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/ |
||
| 124 | #define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */ |
||
| 125 | #define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */ |
||
| 126 | #define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */ |
||
| 127 | #define CLR_RESET (~ISTR_RESET) /* clear RESET bit */ |
||
| 128 | #define CLR_SOF (~ISTR_SOF) /* clear Start Of Frame bit */ |
||
| 129 | #define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */ |
||
| 130 | |||
| 131 | #ifdef STR91x /*STR91x family*/ |
||
| 132 | #define CLR_SZDPR (~ISTR_SZDPR)/* clear SZDPR bit */ |
||
| 133 | #endif |
||
| 134 | |||
| 135 | /*******************************************************************************/ |
||
| 136 | /* CNTR control register bits definitions */ |
||
| 137 | /*******************************************************************************/ |
||
| 138 | #define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */ |
||
| 139 | #define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */ |
||
| 140 | #define CNTR_ERRM (0x2000) /* ERRor Mask */ |
||
| 141 | #define CNTR_WKUPM (0x1000) /* WaKe UP Mask */ |
||
| 142 | #define CNTR_SUSPM (0x0800) /* SUSPend Mask */ |
||
| 143 | #define CNTR_RESETM (0x0400) /* RESET Mask */ |
||
| 144 | #define CNTR_SOFM (0x0200) /* Start Of Frame Mask */ |
||
| 145 | #define CNTR_ESOFM (0x0100) /* Expected Start Of Frame Mask */ |
||
| 146 | |||
| 147 | #ifdef STR91x /*STR91x family*/ |
||
| 148 | #define CNTR_SZDPRM (0x0080) /* Short or Zero-Length Received Data Packet Mask*/ |
||
| 149 | #endif |
||
| 150 | |||
| 151 | #define CNTR_RESUME (0x0010) /* RESUME request */ |
||
| 152 | #define CNTR_FSUSP (0x0008) /* Force SUSPend */ |
||
| 153 | #define CNTR_LPMODE (0x0004) /* Low-power MODE */ |
||
| 154 | #define CNTR_PDWN (0x0002) /* Power DoWN */ |
||
| 155 | #define CNTR_FRES (0x0001) /* Force USB RESet */ |
||
| 156 | |||
| 157 | /*******************************************************************************/ |
||
| 158 | /* FNR Frame Number Register bit definitions */ |
||
| 159 | /*******************************************************************************/ |
||
| 160 | #define FNR_RXDP (0x8000) /* status of D+ data line */ |
||
| 161 | #define FNR_RXDM (0x4000) /* status of D- data line */ |
||
| 162 | #define FNR_LCK (0x2000) /* LoCKed */ |
||
| 163 | #define FNR_LSOF (0x1800) /* Lost SOF */ |
||
| 164 | #define FNR_FN (0x07FF) /* Frame Number */ |
||
| 165 | /*******************************************************************************/ |
||
| 166 | /* DADDR Device ADDRess bit definitions */ |
||
| 167 | /*******************************************************************************/ |
||
| 168 | #define DADDR_EF (0x80) |
||
| 169 | #define DADDR_ADD (0x7F) |
||
| 170 | /*===============================================================================*/ |
||
| 171 | /* Endpoint register */ |
||
| 172 | /*===============================================================================*/ |
||
| 173 | /* bit positions */ |
||
| 174 | #define EP_CTR_RX (0x8000) /* EndPoint Correct TRansfer RX */ |
||
| 175 | #define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */ |
||
| 176 | #define EPRX_STAT (0x3000) /* EndPoint RX STATus bit field */ |
||
| 177 | #define EP_SETUP (0x0800) /* EndPoint SETUP */ |
||
| 178 | #define EP_T_FIELD (0x0600) /* EndPoint TYPE */ |
||
| 179 | #define EP_KIND (0x0100) /* EndPoint KIND */ |
||
| 180 | #define EP_CTR_TX (0x0080) /* EndPoint Correct TRansfer TX */ |
||
| 181 | #define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */ |
||
| 182 | #define EPTX_STAT (0x0030) /* EndPoint TX STATus bit field */ |
||
| 183 | #define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */ |
||
| 184 | |||
| 185 | /* EndPoint REGister MASK (no toggle fields) */ |
||
| 186 | #define EPREG_MASK (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD) |
||
| 187 | |||
| 188 | /* EP_TYPE[1:0] EndPoint TYPE */ |
||
| 189 | #define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */ |
||
| 190 | #define EP_BULK (0x0000) /* EndPoint BULK */ |
||
| 191 | #define EP_CONTROL (0x0200) /* EndPoint CONTROL */ |
||
| 192 | #define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */ |
||
| 193 | #define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */ |
||
| 194 | #define EP_T_MASK (~EP_T_FIELD & EPREG_MASK) |
||
| 195 | |||
| 196 | |||
| 197 | /* EP_KIND EndPoint KIND */ |
||
| 198 | #define EPKIND_MASK (~EP_KIND & EPREG_MASK) |
||
| 199 | |||
| 200 | /* STAT_TX[1:0] STATus for TX transfer */ |
||
| 201 | #define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */ |
||
| 202 | #define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */ |
||
| 203 | #define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */ |
||
| 204 | #define EP_TX_VALID (0x0030) /* EndPoint TX VALID */ |
||
| 205 | #define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */ |
||
| 206 | #define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */ |
||
| 207 | #define EPTX_DTOGMASK (EPTX_STAT|EPREG_MASK) |
||
| 208 | |||
| 209 | /* STAT_RX[1:0] STATus for RX transfer */ |
||
| 210 | #define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */ |
||
| 211 | #define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */ |
||
| 212 | #define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */ |
||
| 213 | #define EP_RX_VALID (0x3000) /* EndPoint RX VALID */ |
||
| 214 | #define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */ |
||
| 215 | #define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */ |
||
| 216 | #define EPRX_DTOGMASK (EPRX_STAT|EPREG_MASK) |
||
| 217 | |||
| 218 | /* Exported macro ------------------------------------------------------------*/ |
||
| 219 | /*----------------------------------------------------------------*/ |
||
| 220 | /* SetCNTR */ |
||
| 221 | /*----------------------------------------------------------------*/ |
||
| 222 | #define _SetCNTR(wRegValue) (*CNTR = (u16)wRegValue) |
||
| 223 | /*----------------------------------------------------------------*/ |
||
| 224 | /* SetISTR */ |
||
| 225 | /*----------------------------------------------------------------*/ |
||
| 226 | #define _SetISTR(wRegValue) (*ISTR = (u16)wRegValue) |
||
| 227 | /*----------------------------------------------------------------*/ |
||
| 228 | /* SetDADDR */ |
||
| 229 | /*----------------------------------------------------------------*/ |
||
| 230 | #define _SetDADDR(wRegValue) (*DADDR = (u16)wRegValue) |
||
| 231 | /*----------------------------------------------------------------*/ |
||
| 232 | /* SetBTABLE */ |
||
| 233 | /*----------------------------------------------------------------*/ |
||
| 234 | #define _SetBTABLE(wRegValue)(*BTABLE = (u16)(wRegValue & 0xFFF8)) |
||
| 235 | /*----------------------------------------------------------------*/ |
||
| 236 | /* GetCNTR */ |
||
| 237 | /*----------------------------------------------------------------*/ |
||
| 238 | #define _GetCNTR() ((u16) *CNTR) |
||
| 239 | /*----------------------------------------------------------------*/ |
||
| 240 | /* GetISTR */ |
||
| 241 | /*----------------------------------------------------------------*/ |
||
| 242 | #define _GetISTR() ((u16) *ISTR) |
||
| 243 | /*----------------------------------------------------------------*/ |
||
| 244 | /* GetFNR */ |
||
| 245 | /*----------------------------------------------------------------*/ |
||
| 246 | #define _GetFNR() ((u16) *FNR) |
||
| 247 | /*----------------------------------------------------------------*/ |
||
| 248 | /* GetDADDR */ |
||
| 249 | /*----------------------------------------------------------------*/ |
||
| 250 | #define _GetDADDR() ((u16) *DADDR) |
||
| 251 | /*----------------------------------------------------------------*/ |
||
| 252 | /* GetBTABLE */ |
||
| 253 | /*----------------------------------------------------------------*/ |
||
| 254 | #define _GetBTABLE() ((u16) *BTABLE) |
||
| 255 | /*----------------------------------------------------------------*/ |
||
| 256 | /* SetENDPOINT */ |
||
| 257 | /*----------------------------------------------------------------*/ |
||
| 258 | #define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \ |
||
| 259 | (u16)wRegValue) |
||
| 260 | /*----------------------------------------------------------------*/ |
||
| 261 | /* GetENDPOINT */ |
||
| 262 | /*----------------------------------------------------------------*/ |
||
| 263 | #define _GetENDPOINT(bEpNum) ((u16)(*(EP0REG + bEpNum))) |
||
| 264 | /*----------------------------------------------------------------*/ |
||
| 265 | /* SetEPType */ |
||
| 266 | /* sets the type in the endpoint register(bits EP_TYPE[1:0]) */ |
||
| 267 | /* IN : bEpNum = endpoint number */ |
||
| 268 | /* wType = type definition */ |
||
| 269 | /* OUT: none */ |
||
| 270 | /*----------------------------------------------------------------*/ |
||
| 271 | #define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\ |
||
| 272 | ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType))) |
||
| 273 | /*----------------------------------------------------------------*/ |
||
| 274 | /* GetEPType */ |
||
| 275 | /* gets the type in the endpoint register(bits EP_TYPE[1:0]) */ |
||
| 276 | /* IN : bEpNum = endpoint number */ |
||
| 277 | /* OUT: type definition */ |
||
| 278 | /*----------------------------------------------------------------*/ |
||
| 279 | #define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD) |
||
| 280 | /*----------------------------------------------------------------*/ |
||
| 281 | /* SetEPTxStatus */ |
||
| 282 | /* sets the status for tx transfer (bits STAT_TX[1:0]) */ |
||
| 283 | /* IN : bEpNum = endpoint number */ |
||
| 284 | /* wState = new state */ |
||
| 285 | /* OUT: none */ |
||
| 286 | /*----------------------------------------------------------------*/ |
||
| 287 | #define _SetEPTxStatus(bEpNum,wState) {\ |
||
| 288 | register u16 _wRegVal; \ |
||
| 289 | _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\ |
||
| 290 | /* toggle first bit ? */ \ |
||
| 291 | if((EPTX_DTOG1 & wState)!= 0) \ |
||
| 292 | _wRegVal ^= EPTX_DTOG1; \ |
||
| 293 | /* toggle second bit ? */ \ |
||
| 294 | if((EPTX_DTOG2 & wState)!= 0) \ |
||
| 295 | _wRegVal ^= EPTX_DTOG2; \ |
||
| 296 | _SetENDPOINT(bEpNum, _wRegVal); \ |
||
| 297 | } /* _SetEPTxStatus */ |
||
| 298 | |||
| 299 | /*----------------------------------------------------------------*/ |
||
| 300 | /* SetEPRxStatus */ |
||
| 301 | /* sets the status for rx transfer (bits STAT_TX[1:0]) */ |
||
| 302 | /* IN : bEpNum = endpoint number */ |
||
| 303 | /* wState = new state */ |
||
| 304 | /* OUT: none */ |
||
| 305 | /*----------------------------------------------------------------*/ |
||
| 306 | #define _SetEPRxStatus(bEpNum,wState) {\ |
||
| 307 | register u16 _wRegVal; \ |
||
| 308 | \ |
||
| 309 | _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\ |
||
| 310 | /* toggle first bit ? */ \ |
||
| 311 | if((EPRX_DTOG1 & wState)!= 0) \ |
||
| 312 | _wRegVal ^= EPRX_DTOG1; \ |
||
| 313 | /* toggle second bit ? */ \ |
||
| 314 | if((EPRX_DTOG2 & wState)!= 0) \ |
||
| 315 | _wRegVal ^= EPRX_DTOG2; \ |
||
| 316 | _SetENDPOINT(bEpNum, _wRegVal); \ |
||
| 317 | } /* _SetEPRxStatus */ |
||
| 318 | /*----------------------------------------------------------------*/ |
||
| 319 | /* GetEPTxStatus / GetEPRxStatus */ |
||
| 320 | /* gets the status for tx/rx transfer (bits STAT_TX[1:0]/STAT_RX[1:0]) */ |
||
| 321 | /* IN : bEpNum = endpoint number */ |
||
| 322 | /* OUT: u16 status */ |
||
| 323 | /*----------------------------------------------------------------*/ |
||
| 324 | #define _GetEPTxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPTX_STAT) |
||
| 325 | #define _GetEPRxStatus(bEpNum) ((u16)_GetENDPOINT(bEpNum) & EPRX_STAT) |
||
| 326 | /*----------------------------------------------------------------*/ |
||
| 327 | /* SetEPTxValid / SetEPRxValid */ |
||
| 328 | /* sets directly the VALID tx/rx-status into the enpoint register */ |
||
| 329 | /* IN : bEpNum = endpoint number */ |
||
| 330 | /* OUT: none */ |
||
| 331 | /*----------------------------------------------------------------*/ |
||
| 332 | #define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID)) |
||
| 333 | #define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID)) |
||
| 334 | /*----------------------------------------------------------------*/ |
||
| 335 | /* GetTxStallStatus / GetRxStallStatus */ |
||
| 336 | /* checks stall condition in an endpoint */ |
||
| 337 | /* IN : bEpNum = endpoint number */ |
||
| 338 | /* OUT: TRUE = endpoint in stall condition */ |
||
| 339 | /*----------------------------------------------------------------*/ |
||
| 340 | #define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \ |
||
| 341 | == EP_TX_STALL) |
||
| 342 | #define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \ |
||
| 343 | == EP_RX_STALL) |
||
| 344 | /*----------------------------------------------------------------*/ |
||
| 345 | /* SetEP_KIND / ClearEP_KIND */ |
||
| 346 | /* IN : bEpNum = endpoint number */ |
||
| 347 | /* OUT: none */ |
||
| 348 | /*----------------------------------------------------------------*/ |
||
| 349 | #define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ |
||
| 350 | (_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK)) |
||
| 351 | #define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \ |
||
| 352 | (_GetENDPOINT(bEpNum) & EPKIND_MASK))) |
||
| 353 | /*----------------------------------------------------------------*/ |
||
| 354 | /* Set_Status_Out / Clear_Status_Out */ |
||
| 355 | /* sets/clears directly STATUS_OUT bit in the endpoint register */ |
||
| 356 | /* to be used only during control transfers */ |
||
| 357 | /* IN : bEpNum = endpoint number */ |
||
| 358 | /* OUT: none */ |
||
| 359 | /*----------------------------------------------------------------*/ |
||
| 360 | #define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum) |
||
| 361 | #define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum) |
||
| 362 | /*----------------------------------------------------------------*/ |
||
| 363 | /* SetEPDoubleBuff / ClearEPDoubleBuff */ |
||
| 364 | /* sets/clears directly EP_KIND bit in the endpoint register */ |
||
| 365 | /* IN : bEpNum = endpoint number */ |
||
| 366 | /* OUT: none */ |
||
| 367 | /*----------------------------------------------------------------*/ |
||
| 368 | #define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum) |
||
| 369 | #define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum) |
||
| 370 | /*----------------------------------------------------------------*/ |
||
| 371 | /* ClearEP_CTR_RX / ClearEP_CTR_TX */ |
||
| 372 | /* clears bit CTR_RX / CTR_TX in the endpoint register */ |
||
| 373 | /* IN : bEpNum = endpoint number */ |
||
| 374 | /* OUT: none */ |
||
| 375 | /*----------------------------------------------------------------*/ |
||
| 376 | #define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum,\ |
||
| 377 | _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK)) |
||
| 378 | #define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum,\ |
||
| 379 | _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK)) |
||
| 380 | /*----------------------------------------------------------------*/ |
||
| 381 | /* ToggleDTOG_RX / ToggleDTOG_TX */ |
||
| 382 | /* toggles DTOG_RX / DTOG_TX bit in the endpoint register */ |
||
| 383 | /* IN : bEpNum = endpoint number */ |
||
| 384 | /* OUT: none */ |
||
| 385 | /*----------------------------------------------------------------*/ |
||
| 386 | #define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \ |
||
| 387 | EP_DTOG_RX | _GetENDPOINT(bEpNum) & EPREG_MASK)) |
||
| 388 | #define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \ |
||
| 389 | EP_DTOG_TX | _GetENDPOINT(bEpNum) & EPREG_MASK)) |
||
| 390 | /*----------------------------------------------------------------*/ |
||
| 391 | /* ClearDTOG_RX / ClearDTOG_TX */ |
||
| 392 | /* IN : bEpNum = endpoint number */ |
||
| 393 | /* OUT: none */ |
||
| 394 | /*----------------------------------------------------------------*/ |
||
| 395 | #define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\ |
||
| 396 | _ToggleDTOG_RX(bEpNum) |
||
| 397 | #define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\ |
||
| 398 | _ToggleDTOG_TX(bEpNum) |
||
| 399 | /*----------------------------------------------------------------*/ |
||
| 400 | /* SetEPAddress */ |
||
| 401 | /* sets address in an endpoint register */ |
||
| 402 | /* IN : bEpNum = endpoint number */ |
||
| 403 | /* bAddr = address */ |
||
| 404 | /* OUT: none */ |
||
| 405 | /*----------------------------------------------------------------*/ |
||
| 406 | |||
| 407 | #define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\ |
||
| 408 | _GetENDPOINT(bEpNum) & EPREG_MASK | bAddr) |
||
| 409 | /*----------------------------------------------------------------*/ |
||
| 410 | /* GetEPAddress */ |
||
| 411 | /* IN : bEpNum = endpoint number */ |
||
| 412 | /* OUT: none */ |
||
| 413 | /*----------------------------------------------------------------*/ |
||
| 414 | #define _GetEPAddress(bEpNum) ((u8)(_GetENDPOINT(bEpNum) & EPADDR_FIELD)) |
||
| 415 | /*----------------------------------------------------------------*/ |
||
| 416 | #ifdef STR7xx /*STR7xx family*/ |
||
| 417 | #define _pEPTxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8 )*2 + PMAAddr)) |
||
| 418 | #define _pEPTxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr)) |
||
| 419 | #define _pEPRxAddr(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr)) |
||
| 420 | #define _pEPRxCount(bEpNum) ((u32 *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr)) |
||
| 421 | #endif |
||
| 422 | |||
| 423 | #ifdef STR91x /*STR91x family*/ |
||
| 424 | /* Pointers on endpoint(bEpNum) Count & Addr registers on PMA */ |
||
| 425 | #define _pEPBufCount(bEpNum) ((u32 *)(_GetBTABLE()+bEpNum*8 + 4 + PMAAddr)) |
||
| 426 | #define _pEPBufAddr(bEpNum) ((u32 *)(_GetBTABLE()+bEpNum*8 + PMAAddr)) |
||
| 427 | #endif |
||
| 428 | /*----------------------------------------------------------------*/ |
||
| 429 | /* SetEPTxAddr / SetEPRxAddr */ |
||
| 430 | /* sets address of the tx/rx buffer */ |
||
| 431 | /* IN : bEpNum = endpoint number */ |
||
| 432 | /* wAddr = address to be set ( must be word aligned ) */ |
||
| 433 | /* OUT: none */ |
||
| 434 | /*----------------------------------------------------------------*/ |
||
| 435 | |||
| 436 | #ifdef STR7xx /*STR7xx family*/ |
||
| 437 | #define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1)) |
||
| 438 | #define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1)) |
||
| 439 | #endif |
||
| 440 | |||
| 441 | #ifdef STR91x /*STR91x family*/ |
||
| 442 | #define _SetEPTxAddr(bEpNum , wAddr) {\ |
||
| 443 | *_pEPBufAddr(bEpNum) &=0xFFFF0000; \ |
||
| 444 | *_pEPBufAddr(bEpNum) |=((wAddr)&0x0FFFC);\ |
||
| 445 | } |
||
| 446 | #define _SetEPRxAddr(bEpNum, wAddr) {\ |
||
| 447 | *_pEPBufAddr(bEpNum) &=0x0000FFFF;\ |
||
| 448 | *_pEPBufAddr(bEpNum) |=((wAddr<<16)&0xFFFC0000);\ |
||
| 449 | } |
||
| 450 | #endif |
||
| 451 | |||
| 452 | /*----------------------------------------------------------------*/ |
||
| 453 | /* GetEPTxAddr / GetEPRxAddr */ |
||
| 454 | /* gets address of the tx/rx buffer */ |
||
| 455 | /* IN : bEpNum = endpoint number */ |
||
| 456 | /* IN : */ |
||
| 457 | /* OUT: address of the buffer */ |
||
| 458 | /*----------------------------------------------------------------*/ |
||
| 459 | |||
| 460 | #ifdef STR7xx /*STR7xx family*/ |
||
| 461 | #define _GetEPTxAddr(bEpNum) ((u16)*_pEPTxAddr(bEpNum)) |
||
| 462 | #define _GetEPRxAddr(bEpNum) ((u16)*_pEPRxAddr(bEpNum)) |
||
| 463 | #endif |
||
| 464 | |||
| 465 | #ifdef STR91x /*STR91x family*/ |
||
| 466 | #define _GetEPTxAddr(bEpNum) ((u16)(*_pEPBufAddr(bEpNum) &0x0000FFFF)) |
||
| 467 | #define _GetEPRxAddr(bEpNum) ((u16)((*_pEPBufAddr(bEpNum)&0xFFFF0000)>>16)) |
||
| 468 | #endif |
||
| 469 | /*----------------------------------------------------------------*/ |
||
| 470 | /* SetEPCountRxReg */ |
||
| 471 | /* sets counter of rx buffer with no. of blocks */ |
||
| 472 | /* IN : pdwReg = pointer to counter */ |
||
| 473 | /* wCount = counter */ |
||
| 474 | /* OUT: none */ |
||
| 475 | /*----------------------------------------------------------------*/ |
||
| 476 | |||
| 477 | #ifdef STR7xx /*STR7xx family*/ |
||
| 478 | #define _BlocksOf32(dwReg,wCount,wNBlocks) {\ |
||
| 479 | wNBlocks = wCount >> 5;\ |
||
| 480 | if((wCount & 0x1f) == 0)\ |
||
| 481 | wNBlocks--;\ |
||
| 482 | *pdwReg = (u32)((wNBlocks << 10) | 0x8000);\ |
||
| 483 | }/* _BlocksOf32 */ |
||
| 484 | |||
| 485 | #define _BlocksOf2(dwReg,wCount,wNBlocks) {\ |
||
| 486 | wNBlocks = wCount >> 1;\ |
||
| 487 | if((wCount & 0x1) != 0)\ |
||
| 488 | wNBlocks++;\ |
||
| 489 | *pdwReg = (u32)(wNBlocks << 10);\ |
||
| 490 | }/* _BlocksOf2 */ |
||
| 491 | |||
| 492 | #define _SetEPCountRxReg(dwReg,wCount) {\ |
||
| 493 | u16 wNBlocks;\ |
||
| 494 | if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\ |
||
| 495 | else {_BlocksOf2(dwReg,wCount,wNBlocks);}\ |
||
| 496 | }/* _SetEPCountRxReg */ |
||
| 497 | |||
| 498 | |||
| 499 | |||
| 500 | #define _SetEPRxDblBuf0Count(bEpNum,wCount) {\ |
||
| 501 | u32 *pdwReg = _pEPTxCount(bEpNum); \ |
||
| 502 | _SetEPCountRxReg(pdwReg, wCount);\ |
||
| 503 | } |
||
| 504 | #endif |
||
| 505 | /*----------------------------------------------------------------*/ |
||
| 506 | /* SetEPTxCount / SetEPRxCount */ |
||
| 507 | /* sets counter for the tx/rx buffer */ |
||
| 508 | /* IN : bEpNum = endpoint number */ |
||
| 509 | /* wCount = counter value */ |
||
| 510 | /* OUT: none */ |
||
| 511 | /*----------------------------------------------------------------*/ |
||
| 512 | |||
| 513 | #ifdef STR7xx /*STR7xx family*/ |
||
| 514 | #define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount) |
||
| 515 | #define _SetEPRxCount(bEpNum,wCount) {\ |
||
| 516 | u32 *pdwReg = _pEPRxCount(bEpNum); \ |
||
| 517 | _SetEPCountRxReg(pdwReg, wCount);\ |
||
| 518 | } |
||
| 519 | #endif |
||
| 520 | |||
| 521 | #ifdef STR91x /*STR91x family*/ |
||
| 522 | #define _SetEPTxCount(bEpNum,wCount) {\ |
||
| 523 | *_pEPBufCount(bEpNum) &=0xFFFFFC00;\ |
||
| 524 | *_pEPBufCount(bEpNum) |=wCount;\ |
||
| 525 | } |
||
| 526 | |||
| 527 | #define _SetEPRxCount(bEpNum,wCount) {\ |
||
| 528 | u32 BLsize=0;\ |
||
| 529 | u32 Blocks;\ |
||
| 530 | if (wCount < 64) Blocks = wCount>>1;\ |
||
| 531 | else\ |
||
| 532 | {\ |
||
| 533 | BLsize = 0x80000000;\ |
||
| 534 | Blocks = wCount>>6;\ |
||
| 535 | }\ |
||
| 536 | *_pEPBufCount(bEpNum) &=~0x80000000;\ |
||
| 537 | *_pEPBufCount(bEpNum) |=BLsize;\ |
||
| 538 | *_pEPBufCount(bEpNum) &=0x83FFFFFF;\ |
||
| 539 | *_pEPBufCount(bEpNum) |=Blocks<<26;\ |
||
| 540 | *_pEPBufCount(bEpNum) &=0xFC00FFFF;\ |
||
| 541 | } |
||
| 542 | #endif |
||
| 543 | /*----------------------------------------------------------------*/ |
||
| 544 | /* GetEPTxCount / GetEPRxCount */ |
||
| 545 | /* gets counter of the tx buffer */ |
||
| 546 | /* IN : bEpNum = endpoint number */ |
||
| 547 | /* OUT: counter value */ |
||
| 548 | /*----------------------------------------------------------------*/ |
||
| 549 | #ifdef STR7xx /*STR7xx family*/ |
||
| 550 | #define _GetEPTxCount(bEpNum)((u16)(*_pEPTxCount(bEpNum)) & 0x3ff) |
||
| 551 | #define _GetEPRxCount(bEpNum)((u16)(*_pEPRxCount(bEpNum)) & 0x3ff) |
||
| 552 | #endif |
||
| 553 | |||
| 554 | #ifdef STR91x /*STR91x family*/ |
||
| 555 | #define _GetEPTxCount(bEpNum) (u16)(*_pEPBufCount(bEpNum)&0x3FF) |
||
| 556 | #define _GetEPRxCount(bEpNum) (u16)((*_pEPBufCount(bEpNum)&0x3FF0000)>>16) |
||
| 557 | #endif |
||
| 558 | /*----------------------------------------------------------------*/ |
||
| 559 | /* SetEPDblBuf0Addr / SetEPDblBuf1Addr */ |
||
| 560 | /* sets buffer 0/1 address in a double buffer endpoint */ |
||
| 561 | /* IN : bEpNum = endpoint number */ |
||
| 562 | /* wBuf0Addr = buffer 0 address */ |
||
| 563 | /* OUT: none */ |
||
| 564 | /*----------------------------------------------------------------*/ |
||
| 565 | #define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);} |
||
| 566 | #define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);} |
||
| 567 | |||
| 568 | /*----------------------------------------------------------------*/ |
||
| 569 | /* SetEPDblBuffAddr */ |
||
| 570 | /* sets addresses in a double buffer endpoint */ |
||
| 571 | /* IN : bEpNum = endpoint number */ |
||
| 572 | /* wBuf0Addr = buffer 0 address */ |
||
| 573 | /* wBuf1Addr = buffer 1 address */ |
||
| 574 | /* OUT: none */ |
||
| 575 | /*----------------------------------------------------------------*/ |
||
| 576 | #define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \ |
||
| 577 | _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\ |
||
| 578 | _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\ |
||
| 579 | } /* _SetEPDblBuffAddr */ |
||
| 580 | /*----------------------------------------------------------------*/ |
||
| 581 | /* GetEPDblBuf0Addr / GetEPDblBuf1Addr */ |
||
| 582 | /* gets buffer 0/1 address of a double buffer endpoint */ |
||
| 583 | /* IN : bEpNum = endpoint number */ |
||
| 584 | /* OUT: none */ |
||
| 585 | /*----------------------------------------------------------------*/ |
||
| 586 | #define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum)) |
||
| 587 | #define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum)) |
||
| 588 | /*----------------------------------------------------------------*/ |
||
| 589 | /* SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count */ |
||
| 590 | /* sets both buffers or buff0 or buff1 counter for double buffering */ |
||
| 591 | /* IN : bEpNum = endpoint number */ |
||
| 592 | /* bDir = endpoint dir EP_DBUF_OUT = OUT */ |
||
| 593 | /* EP_DBUF_IN = IN */ |
||
| 594 | /* wCount = counter value */ |
||
| 595 | /* OUT: none */ |
||
| 596 | /*----------------------------------------------------------------*/ |
||
| 597 | |||
| 598 | #ifdef STR7xx /*STR7xx family*/ |
||
| 599 | |||
| 600 | #define _SetEPDblBuf0Count(bEpNum, bDir, wCount) { \ |
||
| 601 | if(bDir == EP_DBUF_OUT)\ |
||
| 602 | /* OUT endpoint */ \ |
||
| 603 | {_SetEPRxDblBuf0Count(bEpNum,wCount);} \ |
||
| 604 | else if(bDir == EP_DBUF_IN)\ |
||
| 605 | /* IN endpoint */ \ |
||
| 606 | *_pEPTxCount(bEpNum) = (u32)wCount; \ |
||
| 607 | } /* SetEPDblBuf0Count*/ |
||
| 608 | |||
| 609 | #define _SetEPDblBuf1Count(bEpNum, bDir, wCount) { \ |
||
| 610 | if(bDir == EP_DBUF_OUT)\ |
||
| 611 | /* OUT endpoint */ \ |
||
| 612 | {_SetEPRxCount(bEpNum,wCount);}\ |
||
| 613 | else if(bDir == EP_DBUF_IN)\ |
||
| 614 | /* IN endpoint */\ |
||
| 615 | *_pEPRxCount(bEpNum) = (u32)wCount; \ |
||
| 616 | } /* SetEPDblBuf1Count */ |
||
| 617 | |||
| 618 | #define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\ |
||
| 619 | _SetEPDblBuf0Count(bEpNum, bDir, wCount); \ |
||
| 620 | _SetEPDblBuf1Count(bEpNum, bDir, wCount); \ |
||
| 621 | } /* _SetEPDblBuffCount */ |
||
| 622 | #endif |
||
| 623 | /*----------------------------------------------------------------*/ |
||
| 624 | /* GetEPDblBuf0Count / GetEPDblBuf1Count */ |
||
| 625 | /* gets buffer 0/1 rx/tx counter for double buffering */ |
||
| 626 | /* IN : bEpNum = endpoint number */ |
||
| 627 | /* OUT: none */ |
||
| 628 | /*----------------------------------------------------------------*/ |
||
| 629 | #define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum)) |
||
| 630 | #define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum)) |
||
| 631 | |||
| 632 | |||
| 633 | /* External variables --------------------------------------------------------*/ |
||
| 634 | extern volatile u16 wIstr; /* ISTR register last read value */ |
||
| 635 | |||
| 636 | /* Exported functions ------------------------------------------------------- */ |
||
| 637 | void SetCNTR(u16 /*wRegValue*/); |
||
| 638 | void SetISTR(u16 /*wRegValue*/); |
||
| 639 | void SetDADDR(u16 /*wRegValue*/); |
||
| 640 | void SetBTABLE(u16 /*wRegValue*/); |
||
| 641 | void SetBTABLE(u16 /*wRegValue*/); |
||
| 642 | u16 GetCNTR(void); |
||
| 643 | u16 GetISTR(void); |
||
| 644 | u16 GetFNR(void); |
||
| 645 | u16 GetDADDR(void); |
||
| 646 | u16 GetBTABLE(void); |
||
| 647 | void SetENDPOINT(u8 /*bEpNum*/,u16 /*wRegValue*/); |
||
| 648 | u16 GetENDPOINT(u8 /*bEpNum*/); |
||
| 649 | void SetEPType(u8 /*bEpNum*/,u16 /*wType*/); |
||
| 650 | u16 GetEPType(u8 /*bEpNum*/); |
||
| 651 | void SetEPTxStatus(u8 /*bEpNum*/,u16 /*wState*/); |
||
| 652 | void SetEPRxStatus(u8 /*bEpNum*/,u16 /*wState*/); |
||
| 653 | void SetDouBleBuffEPStall(u8 /*bEpNum*/,u8 bDir); |
||
| 654 | u16 GetEPTxStatus(u8 /*bEpNum*/); |
||
| 655 | u16 GetEPRxStatus(u8 /*bEpNum*/); |
||
| 656 | void SetEPTxValid(u8 /*bEpNum*/); |
||
| 657 | void SetEPRxValid(u8 /*bEpNum*/); |
||
| 658 | u16 GetTxStallStatus(u8 /*bEpNum*/); |
||
| 659 | u16 GetRxStallStatus(u8 /*bEpNum*/); |
||
| 660 | void SetEP_KIND(u8 /*bEpNum*/); |
||
| 661 | void ClearEP_KIND(u8 /*bEpNum*/); |
||
| 662 | void Set_Status_Out(u8 /*bEpNum*/); |
||
| 663 | void Clear_Status_Out(u8 /*bEpNum*/); |
||
| 664 | void SetEPDoubleBuff(u8 /*bEpNum*/); |
||
| 665 | void ClearEPDoubleBuff(u8 /*bEpNum*/); |
||
| 666 | void ClearEP_CTR_RX(u8 /*bEpNum*/); |
||
| 667 | void ClearEP_CTR_TX(u8 /*bEpNum*/); |
||
| 668 | void ToggleDTOG_RX(u8 /*bEpNum*/); |
||
| 669 | void ToggleDTOG_TX(u8 /*bEpNum*/); |
||
| 670 | void ClearDTOG_RX(u8 /*bEpNum*/); |
||
| 671 | void ClearDTOG_TX(u8 /*bEpNum*/); |
||
| 672 | void SetEPAddress(u8 /*bEpNum*/,u8 /*bAddr*/); |
||
| 673 | u8 GetEPAddress(u8 /*bEpNum*/); |
||
| 674 | void SetEPTxAddr(u8 /*bEpNum*/,u16 /*wAddr*/); |
||
| 675 | void SetEPRxAddr(u8 /*bEpNum*/,u16 /*wAddr*/); |
||
| 676 | u16 GetEPTxAddr(u8 /*bEpNum*/); |
||
| 677 | u16 GetEPRxAddr(u8 /*bEpNum*/); |
||
| 678 | void SetEPCountRxReg(u32 * /*pdwReg*/, u16 /*wCount*/); |
||
| 679 | void SetEPTxCount(u8 /*bEpNum*/,u16 /*wCount*/); |
||
| 680 | void SetEPRxCount(u8 /*bEpNum*/,u16 /*wCount*/); |
||
| 681 | u16 GetEPTxCount(u8 /*bEpNum*/); |
||
| 682 | u16 GetEPRxCount(u8 /*bEpNum*/); |
||
| 683 | void SetEPDblBuf0Addr(u8 /*bEpNum*/,u16 /*wBuf0Addr*/); |
||
| 684 | void SetEPDblBuf1Addr(u8 /*bEpNum*/,u16 /*wBuf1Addr*/); |
||
| 685 | void SetEPDblBuffAddr(u8 /*bEpNum*/,u16 /*wBuf0Addr*/,u16 /*wBuf1Addr*/); |
||
| 686 | u16 GetEPDblBuf0Addr(u8 /*bEpNum*/); |
||
| 687 | u16 GetEPDblBuf1Addr(u8 /*bEpNum*/); |
||
| 688 | void SetEPDblBuffCount(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
||
| 689 | void SetEPDblBuf0Count(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
||
| 690 | void SetEPDblBuf1Count(u8 /*bEpNum*/, u8 /*bDir*/, u16 /*wCount*/); |
||
| 691 | u16 GetEPDblBuf0Count(u8 /*bEpNum*/); |
||
| 692 | u16 GetEPDblBuf1Count(u8 /*bEpNum*/); |
||
| 693 | EP_DBUF_DIR GetEPDblBufDir(u8 /*bEpNum*/); |
||
| 694 | void FreeUserBuffer(u8 bEpNum/*bEpNum*/,u8 bDir); |
||
| 695 | u16 ToWord(u8,u8); |
||
| 696 | u16 ByteSwap(u16); |
||
| 697 | |||
| 698 | #ifdef STR91x /*STR91x family*/ |
||
| 699 | /* DMA Functions */ |
||
| 700 | void SetDMABurstTxSize(u8 /*DestBsize*/); |
||
| 701 | void SetDMABurstRxSize(u8 /*SrcBsize*/); |
||
| 702 | void DMAUnlinkedModeTxConfig(u8 /*bEpNum*/ ,u8 /*index*/); |
||
| 703 | void DMAUnlinkedModeTxEnable(u8 /*index*/); |
||
| 704 | void DMAUnlinkedModeTxDisable(u8 /*index*/); |
||
| 705 | void DMAUnlinkedModeRxEnable(u8 /*bEpNum*/); |
||
| 706 | void DMAUnlinkedModeRxDisable(u8 /*bEpNum*/); |
||
| 707 | void DMALinkedModeRxConfig(u8 /*bEpNum*/); |
||
| 708 | void DMALinkedModeTxConfig(u8 /*bEpNum*/); |
||
| 709 | void DMALinkedModeRxEnable(void); |
||
| 710 | void DMALinkedModeTxEnable(void); |
||
| 711 | void DMALinkedModeRxDisable(void); |
||
| 712 | void DMALinkedModeTxDisable(void); |
||
| 713 | void DMASynchEnable(void); |
||
| 714 | void DMASynchDisable(void); |
||
| 715 | void SetDMALLITxLength(u8 /*length*/); |
||
| 716 | void SetDMALLIRxLength(u8 /*length*/ ); |
||
| 717 | void SetDMALLIRxPacketNum(u8 /*PacketNum*/); |
||
| 718 | u8 GetDMALLIRxPacketNum(void); |
||
| 719 | #endif /* End of STR91x family*/ |
||
| 720 | |||
| 721 | #endif /* __USB_REGS_H */ |
||
| 722 | |||
| 723 | |||
| 724 | /******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ |