WebSVN - NaviCtrl - Blame - Rev 23 - /tags/V0.1/libstr91x/include/91x

Rev	Author	Line No.	Line
1	ingob	1	/****************** (C) COPYRIGHT 2006 STMicroelectronics ******************
		2	* File Name : 91x_map.h
		3	* Author : MCD Application Team
		4	* Date First Issued : 05/18/2006 : Version 1.0
		5	* Description : Peripherals registers definition and memory mapping.
		6	********************************************************************************
		7	* History:
		8	* 05/22/2007 : Version 1.2
		9	* 05/24/2006 : Version 1.1
		10	* 05/18/2006 : Version 1.0
		11	********************************************************************************
		12	* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
		13	* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS
		14	* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
		15	* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
		16	* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
		17	* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
		18	*******************************************************************************/
		19
		20	/* Define to prevent recursive inclusion ------------------------------------ */
		21	#ifndef __91x_MAP_H
		22	#define __91x_MAP_H
		23
		24	#ifndef EXT
		25	#define EXT extern
		26	#endif /* EXT */
		27
		28	/* Includes ------------------------------------------------------------------*/
		29	#include "91x_conf.h"
		30	#include "91x_type.h"
		31
		32	/******************************************************************************/
		33	/* IP registers structures */
		34	/******************************************************************************/
		35
		36	/------------------------------------ FMI -----------------------------------/
		37
		38	typedef struct
		39	{
		40	vu32 BBSR; /* Boot Bank Size Register */
		41	vu32 NBBSR; /* Non-Boot Bank Size Register */
		42	vu32 EMPTY1;
		43	vu32 BBADR; /* Boot Bank Base Address Register */
		44	vu32 NBBADR; /* Non-Boot Bank Base Address Register */
		45	vu32 EMPTY2;
		46	vu32 CR; /* Control Register */
		47	vu32 SR; /* Status Register */
		48	vu32 BCE5ADDR; /* BC Fifth Entry Target Address Register */
		49	} FMI_TypeDef;
		50
		51	/---------------------- Analog to Digital Convertor ------------------------/
		52
		53	typedef struct
		54	{
		55	vu16 CR; /* Control Register */
		56	vu16 EMPTY1;
		57	vu16 CCR; /* Channel Configuration Register */
		58	vu16 EMPTY2;
		59	vu16 HTR; /* Higher Threshold Register */
		60	vu16 EMPTY3;
		61	vu16 LTR; /* Lower Threshold Register */
		62	vu16 EMPTY4;
		63	vu16 CRR; /* Compare Result Register */
		64	vu16 EMPTY5;
		65	vu16 DR0; /* Data Register for Channel 0 */
		66	vu16 EMPTY6;
		67	vu16 DR1; /* Data Register for Channel 1 */
		68	vu16 EMPTY7;
		69	vu16 DR2; /* Data Register for Channel 2 */
		70	vu16 EMPTY8;
		71	vu16 DR3; /* Data Register for Channel 3 */
		72	vu16 EMPTY9;
		73	vu16 DR4; /* Data Register for Channel 4 */
		74	vu16 EMPTY10;
		75	vu16 DR5; /* Data Register for Channel 5 */
		76	vu16 EMPTY11;
		77	vu16 DR6; /* Data Register for Channel 6 */
		78	vu16 EMPTY12;
		79	vu16 DR7; /* Data Register for Channel 7 */
		80	vu16 EMPTY13;
		81	vu16 PRS; /* Prescaler Value Register */
		82	vu16 EMPTY14;
		83	} ADC_TypeDef;
		84
		85	/--------------------- AHB APB BRIDGE registers strcture --------------------/
		86
		87	typedef struct
		88	{
		89	vu32 BSR; /* Bridge Status Register */
		90	vu32 BCR; /* Bridge Configuration Register */
		91	vu32 PAER; /* Peripheral Address Error register */
		92	} AHBAPB_TypeDef;
		93
		94	/--------------- Controller Area Network Interface Register -----------------/
		95
		96	typedef struct
		97	{
		98	vu16 CRR; /* IFn Command request Register */
		99	vu16 EMPTY1;
		100	vu16 CMR; /* IFn Command Mask Register */
		101	vu16 EMPTY2;
		102	vu16 M1R; /* IFn Message Mask 1 Register */
		103	vu16 EMPTY3;
		104	vu16 M2R; /* IFn Message Mask 2 Register */
		105	vu16 EMPTY4;
		106	vu16 A1R; /* IFn Message Arbitration 1 Register */
		107	vu16 EMPTY5;
		108	vu16 A2R; /* IFn Message Arbitration 2 Register */
		109	vu16 EMPTY6;
		110	vu16 MCR; /* IFn Message Control Register */
		111	vu16 EMPTY7;
		112	vu16 DA1R; /* IFn DATA A 1 Register */
		113	vu16 EMPTY8;
		114	vu16 DA2R; /* IFn DATA A 2 Register */
		115	vu16 EMPTY9;
		116	vu16 DB1R; /* IFn DATA B 1 Register */
		117	vu16 EMPTY10;
		118	vu16 DB2R; /* IFn DATA B 2 Register */
		119	vu16 EMPTY11[27];
		120	} CAN_MsgObj_TypeDef;
		121
		122	typedef struct
		123	{
		124	vu16 CR; /* Control Register */
		125	vu16 EMPTY1;
		126	vu16 SR; /* Status Register */
		127	vu16 EMPTY2;
		128	vu16 ERR; /* Error counter Register */
		129	vu16 EMPTY3;
		130	vu16 BTR; /* Bit Timing Register */
		131	vu16 EMPTY4;
		132	vu16 IDR; /* Interrupt Identifier Register */
		133	vu16 EMPTY5;
		134	vu16 TESTR; /* Test Register */
		135	vu16 EMPTY6;
		136	vu16 BRPR; /* BRP Extension Register */
		137	vu16 EMPTY7[3];
		138	CAN_MsgObj_TypeDef sMsgObj[2];
		139	vu16 EMPTY8[16];
		140	vu16 TXR1R; /* Transmission request 1 Register */
		141	vu16 EMPTY9;
		142	vu16 TXR2R; /* Transmission Request 2 Register */
		143	vu16 EMPTY10[13];
		144	vu16 ND1R; /* New Data 1 Register */
		145	vu16 EMPTY11;
		146	vu16 ND2R; /* New Data 2 Register */
		147	vu16 EMPTY12[13];
		148	vu16 IP1R; /* Interrupt Pending 1 Register */
		149	vu16 EMPTY13;
		150	vu16 IP2R; /* Interrupt Pending 2 Register */
		151	vu16 EMPTY14[13];
		152	vu16 MV1R; /* Message Valid 1 Register */
		153	vu16 EMPTY15;
		154	vu16 MV2R; /* Message VAlid 2 Register */
		155	vu16 EMPTY16;
		156	} CAN_TypeDef;
		157
		158	/----------------------- System Control Unit---------------------------------/
		159
		160	typedef struct
		161	{
		162	vu32 CLKCNTR; /* Clock Control Register */
		163	vu32 PLLCONF; /* PLL Configuration Register */
		164	vu32 SYSSTATUS; /* System Status Register */
		165	vu32 PWRMNG; /* Power Management Register */
		166	vu32 ITCMSK; /* Interrupt Mask Register */
		167	vu32 PCGRO; /* Peripheral Clock Gating Register 0 */
		168	vu32 PCGR1; /* Peripheral Clock Gating Register 1 */
		169	vu32 PRR0; /* Peripheral Reset Register 0 */
		170	vu32 PRR1; /* Peripheral Reset Register 1 */
		171	vu32 MGR0; /* Idle Mode Mask Gating Register 0 */
		172	vu32 MGR1; /* Idle Mode Mask Gating Register 1 */
		173	vu32 PECGR0; /* Peripheral Emulation Clock Gating Register 0 */
		174	vu32 PECGR1; /* Peripheral Emulation Clock Gating Register 1 */
		175	vu32 SCR0; /* System Configuration Register 0 */
		176	vu32 SCR1; /* System Configuration Register 1 */
		177	vu32 SCR2; /* System Configuration Register 2 */
		178	u32 EMPTY1;
		179	vu32 GPIOOUT[8]; /* GPIO Output Registers */
		180	vu32 GPIOIN[8]; /* GPIO Input Registers */
		181	vu32 GPIOTYPE[10]; /* GPIO Type Registers */
		182	vu32 GPIOEMI; /* GPIO EMI Selector Register */
		183	vu32 WKUPSEL; /* Wake-Up Selection Register */
		184	u32 EMPTY2[2];
		185	vu32 GPIOANA; /* GPIO Analag mode Register */
		186	} SCU_TypeDef;
		187
		188	/------------------------- DMA Channelx Registers ---------------------------/
		189
		190	typedef struct
		191	{
		192	vu32 SRC; /* Channelx Source Address Register */
		193	vu32 DES; /* Channelx Destination Address Register */
		194	vu32 LLI; /* Channelx Lincked List Item Register */
		195	vu32 CC; /* Channelx Contol Register */
		196	vu32 CCNF; /* Channelx Configuration Register */
		197	} DMA_Channel_TypeDef;
		198
		199	/* x can be ,0,1,2,3,4,5,6 or 7. There are eight Channels AHB BUS Master */
		200
		201	/----------------------------- DMA Controller -------------------------------/
		202
		203	typedef struct
		204	{
		205	vu32 ISR; /* Interrupt Status Register */
		206	vu32 TCISR; /* Terminal Count Interrupt Status Register */
		207	vu32 TCICR; /* Terminal CountInterrupt Clear Register */
		208	vu32 EISR; /* Error Interrupt Status Register */
		209	vu32 EICR; /* Error Interrupt Clear Register */
		210	vu32 TCRISR; /* Terminal Count Raw Interrupt Status Register */
		211	vu32 ERISR; /* Raw Error Interrupt Status Register */
		212	vu32 ENCSR; /* Enabled Channel Status Register */
		213	vu32 SBRR; /* Software Burst Request Register */
		214	vu32 SSRR; /* Software Single Request Register */
		215	vu32 SLBRR; /* Software Last Burst Request Register */
		216	vu32 SLSRR; /* Software Last Single Request Register */
		217	vu32 CNFR; /* Configuration Register */
		218	vu32 SYNR; /* Syncronization Register */
		219	} DMA_TypeDef;
		220
		221	/--------------------------------- TIM Timer --------------------------------/
		222
		223	typedef struct
		224	{
		225	vu16 IC1R; /* Input Capture 1 Register */
		226	vu16 EMPTY1;
		227	vu16 IC2R; /* Input Capture 2 Register */
		228	vu16 EMPTY2;
		229	vu16 OC1R; /* Output Compare 1 Register */
		230	vu16 EMPTY3;
		231	vu16 OC2R; /* Output Compare 2 Register */
		232	vu16 EMPTY4;
		233	vu16 CNTR; /* Counter Register */
		234	vu16 EMPTY5;
		235	vu16 CR1; /* Control Register 1 */
		236	vu16 EMPTY6;
		237	vu16 CR2; /* Control Register 2 */
		238	vu16 EMPTY7;
		239	vu16 SR; /* Status Register */
		240	vu16 EMPTY8;
		241	} TIM_TypeDef;
		242
		243	/---------------------------- EMI Bankx Registers ---------------------------/
		244
		245	typedef struct
		246	{
		247	vu32 ICR; /* Bankx Idle Cycle Control Register */
		248	vu32 RCR; /* Bankx Read Wait State Control Register */
		249	vu32 WCR; /* Bankx Write Wait State Control Register */
		250	vu32 OECR; /* Bankx Output Enable Assertion Delay Control Register */
		251	vu32 WECR; /* Bankx Write Enable Assertion Delay Control Register */
		252	vu32 BCR; /* Bankx Control Register */
		253	} EMI_Bank_TypeDef;
		254
		255	/---------------------------- Ethernet Controller ---------------------------/
		256
		257	/* MAC Registers */
		258	typedef struct
		259	{
		260	vu32 MCR; /* ENET Control Register */
		261	vu32 MAH; /* ENET Address High Register */
		262	vu32 MAL; /* ENET Address Low Register */
		263	vu32 MCHA; /* Multicast Address High Register */
		264	vu32 MCLA; /* Multicast Address Low Register */
		265	vu32 MIIA; /* MII Address Register */
		266	vu32 MIID; /* MII Data Register */
		267	vu32 MCF; /* ENET Control Frame Register */
		268	vu32 VL1; /* VLAN1 Register */
		269	vu32 VL2; /* VLAN2 register */
		270	vu32 MTS; /* ENET Transmission Status Register */
		271	vu32 MRS; /* ENET Reception Status Register */
		272	} ENET_MAC_TypeDef;
		273
		274	/* DMA Registers */
		275	typedef struct
		276	{
		277	vu32 SCR; /* DMA Status and Control Register */
		278	vu32 IER; /* DMA Interrupt Sources Enable Register */
		279	vu32 ISR; /* DMA Interrupt Status Register */
		280	vu32 CCR; /* Clock Control Relation : HCLK, PCLK and
		281	ENET_CLK phase relations */
		282	vu32 RXSTR; /* Rx DMA start Register */
		283	vu32 RXCR; /* Rx DMA Control Register */
		284	vu32 RXSAR; /* Rx DMA Base Address Register */
		285	vu32 RXNDAR; /* Rx DMA Next Descriptor Address Register */
		286	vu32 RXCAR; /* Rx DMA Current Address Register */
		287	vu32 RXCTCR; /* Rx DMA Current Transfer Count Register */
		288	vu32 RXTOR; /* Rx DMA FIFO Time Out Register */
		289	vu32 RXSR; /* Rx DMA FIFO Status Register */
		290	vu32 TXSTR; /* Tx DMA start Register */
		291	vu32 TXCR; /* Tx DMA Control Register */
		292	vu32 TXSAR; /* Tx DMA Base Address Register */
		293	vu32 TXNDAR; /* Tx DMA Next Descriptor Address Register */
		294	vu32 TXCAR; /* Tx DMA Current Address Register */
		295	vu32 TXTCR; /* Tx DMA Current Transfer Count Register */
		296	vu32 TXTOR; /* Tx DMA FIFO Time Out Register */
		297	vu32 TXSR; /* Tx DMA FIFO Status Register */
		298	} ENET_DMA_TypeDef;
		299
		300	/------------------------------------- GPIO ---------------------------------/
		301
		302	typedef struct
		303	{
		304	vu8 DR[1021]; /* Data Register */
		305	vu32 DDR; /* Data Direction Register */
		306	} GPIO_TypeDef;
		307
		308	/-------------------------------- I2C interface -----------------------------/
		309
		310	typedef struct
		311	{
		312	vu8 CR; /* Control Register */
		313	vu8 EMPTY1[3];
		314	vu8 SR1; /* Status Register 1 */
		315	vu8 EMPTY2[3];
		316	vu8 SR2; /* Status Register 2 */
		317	vu8 EMPTY3[3];
		318	vu8 CCR; /* Clock Control Register */
		319	vu8 EMPTY4[3];
		320	vu8 OAR1; /* Own Address Register 1 */
		321	vu8 EMPTY5[3];
		322	vu8 OAR2; /* Own Address Register 2 */
		323	vu8 EMPTY6[3];
		324	vu8 DR; /* Data Register */
		325	vu8 EMPTY7[3];
		326	vu8 ECCR; /* Extended Clock Control Register */
		327	vu8 EMPTY8[3];
		328	} I2C_TypeDef;
		329
		330	/------------------------------------- VIC ----------------------------------/
		331
		332	typedef struct
		333	{
		334	vu32 ISR; /* IRQ Status Register */
		335	vu32 FSR; /* FIQ Status Register */
		336	vu32 RINTSR; /* Raw Interrupt Status Register */
		337	vu32 INTSR; /* Interrupt Select Register */
		338	vu32 INTER; /* Interrupt Enable Register */
		339	vu32 INTECR; /* Interrupt Enable Clear Register */
		340	vu32 SWINTR; /* Software Interrupt Register */
		341	vu32 SWINTCR; /* Software Interrupt clear Register */
		342	vu32 PER; /* Protection Enable Register */
		343	vu32 EMPTY1[3];
		344	vu32 VAR; /* Vector Address Register */
		345	vu32 DVAR; /* Default Vector Address Register */
		346	vu32 EMPTY2[50];
		347	vu32 VAiR[16]; /* Vector Address 0-15 Register */
		348	vu32 EMPTY3[48];
		349	vu32 VCiR[16]; /* Vector Control 0-15 Register */
		350	} VIC_TypeDef;
		351
		352	/-------------------------------- Motor Control -----------------------------/
		353
		354	typedef struct
		355	{
		356	vu16 TCPT; /* Tacho Capture Register */
		357	vu16 EMPTY1;
		358	vu16 TCMP; /* Tacho Compare Register */
		359	vu16 EMPTY2;
		360	vu16 IPR; /* Input Pending Register */
		361	vu16 EMPTY3;
		362	vu16 TPRS; /* Tacho Prescaler Register */
		363	vu16 EMPTY4;
		364	vu16 CPRS; /* PWM Counter Prescaler Register */
		365	vu16 EMPTY5;
		366	vu16 REP; /* Repetition Counter Register */
		367	vu16 EMPTY6;
		368	vu16 CMPW; /* Compare Phase W Preload Register */
		369	vu16 EMPTY7;
		370	vu16 CMPV; /* Compare Phase V Preload Register */
		371	vu16 EMPTY8;
		372	vu16 CMPU; /* Compare Phase U Preload Register */
		373	vu16 EMPTY9;
		374	vu16 CMP0; /* Compare 0 Preload Register */
		375	vu16 EMPTY10;
		376	vu16 PCR0; /* Peripheral Control Register 0 */
		377	vu16 EMPTY11;
		378	vu16 PCR1; /* Peripheral Control Register 1 */
		379	vu16 EMPTY12;
		380	vu16 PCR2; /* Peripheral Control Register 2 */
		381	vu16 EMPTY13;
		382	vu16 PSR; /* Polarity Selection Register */
		383	vu16 EMPTY14;
		384	vu16 OPR; /* Output Peripheral Register */
		385	vu16 EMPTY15;
		386	vu16 IMR; /* Interrupt Mask Register */
		387	vu16 EMPTY16;
		388	vu16 DTG; /* Dead Time Generator Register */
		389	vu16 EMPTY17;
		390	vu16 ESC; /* Emergency Stop Clear Register */
		391	vu16 EMPTY18;
		392	}MC_TypeDef;
		393
		394	/------------------------------------- RTC ----------------------------------/
		395
		396	typedef struct
		397	{
		398	vu32 TR; /* Time Register */
		399	vu32 DTR; /* Date Register */
		400	vu32 ATR; /* Alarm time Register */
		401	vu32 CR; /* Control Register */
		402	vu32 SR; /* Status Register */
		403	vu32 MILR; /* Millisec Register */
		404	}RTC_TypeDef;
		405
		406	/------------------------------------- SSP ----------------------------------/
		407
		408	typedef struct
		409	{
		410	vu16 CR0; /* Control Register 1 */
		411	vu16 EMPTY1;
		412	vu16 CR1; /* Control Register 2 */
		413	vu16 EMPTY2;
		414	vu16 DR; /* Data Register */
		415	vu16 EMPTY3;
		416	vu16 SR; /* Status Register */
		417	vu16 EMPTY4;
		418	vu16 PR; /* Clock Prescale Register */
		419	vu16 EMPTY5;
		420	vu16 IMSCR; /* Interrupt Mask Set or Clear Register */
		421	vu16 EMPTY6;
		422	vu16 RISR; /* Raw Interrupt Status Register */
		423	vu16 EMPTY7;
		424	vu16 MISR; /* Masked Interrupt Status Register */
		425	vu16 EMPTY8;
		426	vu16 ICR; /* Interrupt Clear Register */
		427	vu16 EMPTY9;
		428	vu16 DMACR; /* DMA Control Register */
		429	vu16 EMPTY10;
		430	}SSP_TypeDef;
		431
		432	/------------------------------------ UART ----------------------------------/
		433
		434	typedef struct
		435	{
		436	vu16 DR; /* Data Register */
		437	vu16 EMPTY1;
		438	vu16 RSECR; /* Receive Status Register (read)/Error Clear Register (write) */
		439	vu16 EMPTY2[9];
		440	vu16 FR; /* Flag Register */
		441	vu16 EMPTY3[3];
		442	vu16 ILPR; /* IrDA Low-Power counter Register */
		443	vu16 EMPTY4;
		444	vu16 IBRD; /* Integer Baud Rate Divisor Register */
		445	vu16 EMPTY5;
		446	vu16 FBRD; /* Fractional Baud Rate Divisor Register */
		447	vu16 EMPTY6;
		448	vu16 LCR; /* Line Control Register, High byte */
		449	vu16 EMPTY7;
		450	vu16 CR; /* Control Register */
		451	vu16 EMPTY8;
		452	vu16 IFLS; /* Interrupt FIFO Level Select Register */
		453	vu16 EMPTY9;
		454	vu16 IMSC; /* Interrupt Mask Set/Clear Register */
		455	vu16 EMPTY10;
		456	vu16 RIS; /* Raw Interrupt Status Register */
		457	vu16 EMPTY11;
		458	vu16 MIS; /* Masked Interrupt Status Register */
		459	vu16 EMPTY12;
		460	vu16 ICR; /* Interrupt Clear Register */
		461	vu16 EMPTY13;
		462	vu16 DMACR; /* DMA Control Register */
		463	vu16 EMPTY14;
		464	}UART_TypeDef;
		465
		466	/------------------------------- Wake-up System -----------------------------/
		467
		468	typedef struct
		469	{
		470	vu32 CTRL; /* Control Register */
		471	vu32 MR; /* Mask Register */
		472	vu32 TR; /* Trigger Register */
		473	vu32 PR; /* Pending Register */
		474	vu32 INTR; /* Software Interrupt Register */
		475	} WIU_TypeDef;
		476
		477	/------------------------------- WatchDog Timer -----------------------------/
		478
		479	typedef struct
		480	{
		481	vu16 CR; /* Control Register */
		482	vu16 EMPTY1;
		483	vu16 PR; /* Presclar Register */
		484	vu16 EMPTY2;
		485	vu16 VR; /* Pre-load Value Register */
		486	vu16 EMPTY3;
		487	vu16 CNT; /* Counter Register */
		488	vu16 EMPTY4;
		489	vu16 SR; /* Status Register */
		490	vu16 EMPTY5;
		491	vu16 MR; /* Mask Register */
		492	vu16 EMPTY6;
		493	vu16 KR; /* Key Register */
		494	vu16 EMPTY7;
		495	} WDG_TypeDef;
		496
		497	/*******************************************************************************
		498	* Memory Mapping of STR91x *
		499	*******************************************************************************/
		500
		501	#define AHB_APB_BRDG0_U (0x58000000) /* AHB/APB Bridge 0 UnBuffered Space */
		502	#define AHB_APB_BRDG0_B (0x48000000) /* AHB/APB Bridge 0 Buffered Space */
		503
		504	#define AHB_APB_BRDG1_U (0x5C000000) /* AHB/APB Bridge 1 UnBuffered Space */
		505	#define AHB_APB_BRDG1_B (0x4C000000) /* AHB/APB Bridge 1 Buffered Space */
		506
		507	#define AHB_EMI_U (0x74000000) /* EMI UnBuffered Space */
		508	#define AHB_EMI_B (0x64000000) /* EMI Buffered Space */
		509
		510	#define AHB_DMA_U (0x78000000) /* DMA UnBuffered Space */
		511	#define AHB_DMA_B (0x68000000) /* DMA Buffered Space */
		512
		513	#define AHB_ENET_MAC_U (0x7C000400) /* ENET_MAC UnBuffered Space */
		514	#define AHB_ENET_MAC_B (0x6C000000) /* ENET_MAC Buffered Space */
		515
		516	#define AHB_ENET_DMA_U (0x7C000000) /* ENET_DMA Unbuffered Space */
		517	#define AHB_ENET_DMA_B (0x6C000400) /* ENET_DMA Buffered Space */
		518
		519	#define AHB_VIC1_U (0xFC000000) /* Secondary VIC1 UnBuffered Space */
		520	#define AHB_VIC0_U (0xFFFFF000) /* Primary VIC0 UnBuffered Space */
		521
		522	#define AHB_FMI_U (0x54000000) /* FMI Unbuffered Space */
		523	#define AHB_FMI_B (0x44000000) /* FMI buffered Space */
		524
		525	/*******************************************************************************
		526	* Addresses related to the VICs' peripherals *
		527	*******************************************************************************/
		528
		529	#define VIC0_BASE (AHB_VIC0_U)
		530	#define VIC1_BASE (AHB_VIC1_U)
		531
		532	/*******************************************************************************
		533	* Addresses related to the EMI banks *
		534	*******************************************************************************/
		535
		536	#define AHB_EMIB3_OFST (0x00000040) /* Offset of EMI bank3 */
		537	#define AHB_EMIB2_OFST (0x00000020) /* Offset of EMI bank2 */
		538	#define AHB_EMIB1_OFST (0x00000000) /* Offset of EMI bank1 */
		539	#define AHB_EMIB0_OFST (0x000000E0) /* Offset of EMI bank0 */
		540
		541	/*******************************************************************************
		542	* Addresses related to the DMA peripheral *
		543	*******************************************************************************/
		544
		545	#define AHB_DMA_Channel0_OFST (0x00000100) /* Offset of Channel 0 */
		546	#define AHB_DMA_Channel1_OFST (0x00000120) /* Offset of Channel 1 */
		547	#define AHB_DMA_Channel2_OFST (0x00000140) /* Offset of Channel 2 */
		548	#define AHB_DMA_Channel3_OFST (0x00000160) /* Offset of Channel 3 */
		549	#define AHB_DMA_Channel4_OFST (0x00000180) /* Offset of Channel 4 */
		550	#define AHB_DMA_Channel5_OFST (0x000001A0) /* Offset of Channel 5 */
		551	#define AHB_DMA_Channel6_OFST (0x000001C0) /* Offset of Channel 6 */
		552	#define AHB_DMA_Channel7_OFST (0x000001E0) /* Offset of Channel 7 */
		553
		554	/*******************************************************************************
		555	* Addresses related to the APB0 sub-system *
		556	*******************************************************************************/
		557
		558	#define APB_WIU_OFST (0x00001000) /* Offset of WIU */
		559	#define APB_TIM0_OFST (0x00002000) /* Offset of TIM0 */
		560	#define APB_TIM1_OFST (0x00003000) /* Offset of TIM1 */
		561	#define APB_TIM2_OFST (0x00004000) /* Offset of TIM2 */
		562	#define APB_TIM3_OFST (0x00005000) /* Offset of TIM3 */
		563	#define APB_GPIO0_OFST (0x00006000) /* Offset of GPIO0 */
		564	#define APB_GPIO1_OFST (0x00007000) /* Offset of GPIO1 */
		565	#define APB_GPIO2_OFST (0x00008000) /* Offset of GPIO2 */
		566	#define APB_GPIO3_OFST (0x00009000) /* Offset of GPIO3 */
		567	#define APB_GPIO4_OFST (0x0000A000) /* Offset of GPIO4 */
		568	#define APB_GPIO5_OFST (0x0000B000) /* Offset of GPIO5 */
		569	#define APB_GPIO6_OFST (0x0000C000) /* Offset of GPIO6 */
		570	#define APB_GPIO7_OFST (0x0000D000) /* Offset of GPIO7 */
		571	#define APB_GPIO8_OFST (0x0000E000) /* Offset of GPIO8 */
		572	#define APB_GPIO9_OFST (0x0000F000) /* Offset of GPIO9 */
		573
		574	/*******************************************************************************
		575	* Addresses related to the APB1 sub-system *
		576	*******************************************************************************/
		577
		578	#define APB_RTC_OFST (0x00001000) /* Offset of RTC */
		579	#define APB_SCU_OFST (0x00002000) /* Offset of System Controller */
		580	#define APB_MC_OFST (0x00003000) /* Offset of Motor Control */
		581	#define APB_UART0_OFST (0x00004000) /* Offset of UART0 */
		582	#define APB_UART1_OFST (0x00005000) /* Offset of UART1 */
		583	#define APB_UART2_OFST (0x00006000) /* Offset of UART2 */
		584	#define APB_SSP0_OFST (0x00007000) /* Offset of SSP0 */
		585	#define APB_SSP1_OFST (0x00008000) /* Offset of SSPI */
		586	#define APB_CAN_OFST (0x00009000) /* Offset of CAN */
		587	#define APB_ADC_OFST (0x0000A000) /* Offset of ADC */
		588	#define APB_WDG_OFST (0x0000B000) /* Offset of WDG */
		589	#define APB_I2C0_OFST (0x0000C000) /* Offset of I2C0 */
		590	#define APB_I2C1_OFST (0x0000D000) /* Offset of I2C1 */
		591
		592	/----------------------------------------------------------------------------/
		593	/----------------------------- Unbuffered Mode ------------------------------/
		594	/----------------------------------------------------------------------------/
		595
		596	#ifndef LIBUFF
		597
		598	/*******************************************************************************
		599	* AHBAPB peripheral Unbuffered Base Address *
		600	*******************************************************************************/
		601
		602	#define AHBAPB0_BASE (AHB_APB_BRDG0_U)
		603	#define AHBAPB1_BASE (AHB_APB_BRDG1_U)
		604
		605	/*******************************************************************************
		606	* ENET peripheral Unbuffered Base Address *
		607	*******************************************************************************/
		608
		609	#define ENET_MAC_BASE (AHB_ENET_MAC_U)
		610	#define ENET_DMA_BASE (AHB_ENET_DMA_U)
		611
		612	/*******************************************************************************
		613	* DMA peripheral Unbuffered Base Address *
		614	*******************************************************************************/
		615
		616	#define DMA_BASE (AHB_DMA_U)
		617
		618	/*******************************************************************************
		619	* EMI peripheral Unbuffered Base Address *
		620	*******************************************************************************/
		621
		622	#define EMI_BASE (AHB_EMI_U)
		623
		624	/*******************************************************************************
		625	* FMI peripheral Unbuffered Base Address *
		626	*******************************************************************************/
		627
		628	#define FMI_BASE (AHB_FMI_U)
		629
		630
		631	#else /* LIBUFF */
		632
		633	/----------------------------------------------------------------------------/
		634	/------------------------------ Buffered Mode -------------------------------/
		635	/----------------------------------------------------------------------------/
		636
		637	/*******************************************************************************
		638	* AHBAPB peripheral Buffered Base Address *
		639	*******************************************************************************/
		640
		641	#define AHBAPB0_BASE (AHB_APB_BRDG0_B)
		642	#define AHBAPB1_BASE (AHB_APB_BRDG1_B)
		643
		644	/*******************************************************************************
		645	* ENET peripheral Unbuffered Base Address *
		646	*******************************************************************************/
		647
		648	#define ENET_MAC_BASE (AHB_ENET_MAC_B)
		649	#define ENET_DMA_BASE (AHB_ENET_DMA_B)
		650
		651	/*******************************************************************************
		652	* DMA peripheral Buffered Base Address *
		653	*******************************************************************************/
		654
		655	#define DMA_BASE (AHB_DMA_B)
		656
		657	/*******************************************************************************
		658	* EMI peripheral Buffered Base Address *
		659	*******************************************************************************/
		660
		661	#define EMI_BASE (AHB_EMI_B)
		662
		663	/*******************************************************************************
		664	* FMI peripheral Buffered Base Address *
		665	*******************************************************************************/
		666
		667	#define FMI_BASE (AHB_FMI_B)
		668
		669	#endif /* LIBUFF */
		670
		671	/*******************************************************************************
		672	* DMA channels Base Address *
		673	*******************************************************************************/
		674	#define DMA_Channel0_BASE (DMA_BASE + AHB_DMA_Channel0_OFST)
		675	#define DMA_Channel1_BASE (DMA_BASE + AHB_DMA_Channel1_OFST)
		676	#define DMA_Channel2_BASE (DMA_BASE + AHB_DMA_Channel2_OFST)
		677	#define DMA_Channel3_BASE (DMA_BASE + AHB_DMA_Channel3_OFST)
		678	#define DMA_Channel4_BASE (DMA_BASE + AHB_DMA_Channel4_OFST)
		679	#define DMA_Channel5_BASE (DMA_BASE + AHB_DMA_Channel5_OFST)
		680	#define DMA_Channel6_BASE (DMA_BASE + AHB_DMA_Channel6_OFST)
		681	#define DMA_Channel7_BASE (DMA_BASE + AHB_DMA_Channel7_OFST)
		682
		683	/*******************************************************************************
		684	* EMI Banks peripheral Base Address *
		685	*******************************************************************************/
		686
		687	#define EMI_Bank0_BASE (EMI_BASE + AHB_EMIB0_OFST)
		688	#define EMI_Bank1_BASE (EMI_BASE + AHB_EMIB1_OFST)
		689	#define EMI_Bank2_BASE (EMI_BASE + AHB_EMIB2_OFST)
		690	#define EMI_Bank3_BASE (EMI_BASE + AHB_EMIB3_OFST)
		691
		692	/*******************************************************************************
		693	* APB0 Peripherals' Base addresses *
		694	*******************************************************************************/
		695
		696	#define WIU_BASE (AHBAPB0_BASE + APB_WIU_OFST)
		697	#define TIM0_BASE (AHBAPB0_BASE + APB_TIM0_OFST)
		698	#define TIM1_BASE (AHBAPB0_BASE + APB_TIM1_OFST)
		699	#define TIM2_BASE (AHBAPB0_BASE + APB_TIM2_OFST)
		700	#define TIM3_BASE (AHBAPB0_BASE + APB_TIM3_OFST)
		701	#define GPIO0_BASE (AHBAPB0_BASE + APB_GPIO0_OFST)
		702	#define GPIO1_BASE (AHBAPB0_BASE + APB_GPIO1_OFST)
		703	#define GPIO2_BASE (AHBAPB0_BASE + APB_GPIO2_OFST)
		704	#define GPIO3_BASE (AHBAPB0_BASE + APB_GPIO3_OFST)
		705	#define GPIO4_BASE (AHBAPB0_BASE + APB_GPIO4_OFST)
		706	#define GPIO5_BASE (AHBAPB0_BASE + APB_GPIO5_OFST)
		707	#define GPIO6_BASE (AHBAPB0_BASE + APB_GPIO6_OFST)
		708	#define GPIO7_BASE (AHBAPB0_BASE + APB_GPIO7_OFST)
		709	#define GPIO8_BASE (AHBAPB0_BASE + APB_GPIO8_OFST)
		710	#define GPIO9_BASE (AHBAPB0_BASE + APB_GPIO9_OFST)
		711
		712	/*******************************************************************************
		713	* APB1 Peripherals' Base addresses *
		714	*******************************************************************************/
		715
		716	#define RTC_BASE (AHBAPB1_BASE + APB_RTC_OFST)
		717	#define SCU_BASE (AHBAPB1_BASE + APB_SCU_OFST)
		718	#define MC_BASE (AHBAPB1_BASE + APB_MC_OFST)
		719	#define UART0_BASE (AHBAPB1_BASE + APB_UART0_OFST)
		720	#define UART1_BASE (AHBAPB1_BASE + APB_UART1_OFST)
		721	#define UART2_BASE (AHBAPB1_BASE + APB_UART2_OFST)
		722	#define SSP0_BASE (AHBAPB1_BASE + APB_SSP0_OFST)
		723	#define SSP1_BASE (AHBAPB1_BASE + APB_SSP1_OFST)
		724	#define CAN_BASE (AHBAPB1_BASE + APB_CAN_OFST)
		725	#define ADC_BASE (AHBAPB1_BASE + APB_ADC_OFST)
		726	#define WDG_BASE (AHBAPB1_BASE + APB_WDG_OFST)
		727	#define I2C0_BASE (AHBAPB1_BASE + APB_I2C0_OFST)
		728	#define I2C1_BASE (AHBAPB1_BASE + APB_I2C1_OFST)
		729
		730	/*******************************************************************************
		731	* IPs' declaration *
		732	*******************************************************************************/
		733
		734	/------------------------------ Non Debug Mode ------------------------------/
		735
		736	#ifndef LIBDEBUG
		737
		738	/********************************* AHBAPB *********************************/
		739
		740	#define AHBAPB0 ((AHBAPB_TypeDef *)AHBAPB0_BASE)
		741	#define AHBAPB1 ((AHBAPB_TypeDef *)AHBAPB1_BASE)
		742
		743	/*********************************** EMI **********************************/
		744
		745	#define EMI ((EMI_TypeDef *)EMI_BASE)
		746
		747	/*********************************** DMA **********************************/
		748
		749	#define DMA ((DMA_TypeDef *)DMA_BASE)
		750	#define DMA_Channel0 ((DMA_Channel_TypeDef *)DMA_Channel0_BASE)
		751	#define DMA_Channel1 ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
		752	#define DMA_Channel2 ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
		753	#define DMA_Channel3 ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
		754	#define DMA_Channel4 ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
		755	#define DMA_Channel5 ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
		756	#define DMA_Channel6 ((DMA_Channel_TypeDef *)DMA_Channel6_BASE)
		757	#define DMA_Channel7 ((DMA_Channel_TypeDef *)DMA_Channel7_BASE)
		758
		759	/*********************************** EMI **********************************/
		760
		761	#define EMI_Bank0 ((EMI_Bank_TypeDef *)EMI_Bank0_BASE)
		762	#define EMI_Bank1 ((EMI_Bank_TypeDef *)EMI_Bank1_BASE)
		763	#define EMI_Bank2 ((EMI_Bank_TypeDef *)EMI_Bank2_BASE)
		764	#define EMI_Bank3 ((EMI_Bank_TypeDef *)EMI_Bank3_BASE)
		765
		766	/*********************************** ENET_MAC **********************************/
		767
		768	#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
		769
		770	/*********************************** ENET_DMA **********************************/
		771
		772	#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
		773
		774	/*********************************** FMI **********************************/
		775
		776	#define FMI ((FMI_TypeDef *)FMI_BASE)
		777
		778	/*********************************** VIC **********************************/
		779
		780	#define VIC0 ((VIC_TypeDef *)VIC0_BASE)
		781	#define VIC1 ((VIC_TypeDef *)VIC1_BASE)
		782
		783	/*******************************************************************************
		784	* APB0 Peripherals' *
		785	*******************************************************************************/
		786	#define WIU ((WIU_TypeDef *)WIU_BASE)
		787	#define TIM0 ((TIM_TypeDef *)TIM0_BASE)
		788	#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
		789	#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
		790	#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
		791	#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)
		792	#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)
		793	#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)
		794	#define GPIO3 ((GPIO_TypeDef *)GPIO3_BASE)
		795	#define GPIO4 ((GPIO_TypeDef *)GPIO4_BASE)
		796	#define GPIO5 ((GPIO_TypeDef *)GPIO5_BASE)
		797	#define GPIO6 ((GPIO_TypeDef *)GPIO6_BASE)
		798	#define GPIO7 ((GPIO_TypeDef *)GPIO7_BASE)
		799	#define GPIO8 ((GPIO_TypeDef *)GPIO8_BASE)
		800	#define GPIO9 ((GPIO_TypeDef *)GPIO9_BASE)
		801	/*******************************************************************************
		802	* APB1 Peripherals' *
		803	*******************************************************************************/
		804	#define RTC ((RTC_TypeDef *)RTC_BASE)
		805	#define SCU ((SCU_TypeDef *)SCU_BASE)
		806	#define MC ((MC_TypeDef *)MC_BASE)
		807	#define UART0 ((UART_TypeDef *)UART0_BASE)
		808	#define UART1 ((UART_TypeDef *)UART1_BASE)
		809	#define UART2 ((UART_TypeDef *)UART2_BASE)
		810	#define SSP0 ((SSP_TypeDef *)SSP0_BASE)
		811	#define SSP1 ((SSP_TypeDef *)SSP1_BASE)
		812	#define CAN ((CAN_TypeDef *)CAN_BASE)
		813	#define ADC ((ADC_TypeDef *)ADC_BASE)
		814	#define WDG ((WDG_TypeDef *)WDG_BASE)
		815	#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
		816	#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
		817	#define ENET_MAC ((ENET_MAC_TypeDef *)ENET_MAC_BASE)
		818	#define ENET_DMA ((ENET_DMA_TypeDef *)ENET_DMA_BASE)
		819
		820	#else /* LIBDEBUG */
		821
		822	/-------------------------------- Debug Mode --------------------------------/
		823
		824	#ifdef _AHBAPB0
		825	EXT AHBAPB_TypeDef *AHBAPB0;
		826	#endif /* _AHBAPB0 */
		827
		828	#ifdef _AHBAPB1
		829	EXT AHBAPB_TypeDef *AHBAPB1;
		830	#endif /_AHBAPB1 /
		831
		832
		833	#ifdef _DMA
		834	EXT DMA_TypeDef *DMA;
		835	#endif /* _DMA */
		836
		837	#ifdef _DMA_Channel0
		838	EXT DMA_Channel_TypeDef *DMA_Channel0;
		839	#endif /* _DMA_Channel0 */
		840
		841	#ifdef _DMA_Channel1
		842	EXT DMA_Channel_TypeDef *DMA_Channel1;
		843	#endif /* _DMA_Channel1 */
		844
		845	#ifdef _DMA_Channel2
		846	EXT DMA_Channel_TypeDef *DMA_Channel2;
		847	#endif /* _DMA_Channel0 */
		848
		849	#ifdef _DMA_Channel3
		850	EXT DMA_Channel_TypeDef *DMA_Channel3;
		851	#endif /* _DMA_Channel0 */
		852
		853	#ifdef _DMA_Channel4
		854	EXT DMA_Channel_TypeDef *DMA_Channel4;
		855	#endif /* _DMA_Channel4 */
		856
		857	#ifdef _DMA_Channel5
		858	EXT DMA_Channel_TypeDef *DMA_Channel5;
		859	#endif /* _DMA_Channel5 */
		860
		861	#ifdef _DMA_Channel6
		862	EXT DMA_Channel_TypeDef *DMA_Channel6;
		863	#endif /* _DMA_Channel6 */
		864
		865	#ifdef _DMA_Channel7
		866	EXT DMA_Channel_TypeDef *DMA_Channel7;
		867	#endif /* _DMA_Channel7 */
		868
		869	#ifdef _EMI_Bank0
		870	EXT EMI_Bank_TypeDef *EMI_Bank0;
		871	#endif /* _EMI_Bank0 */
		872
		873	#ifdef _EMI_Bank1
		874	EXT EMI_Bank_TypeDef *EMI_Bank1;
		875	#endif /* _EMI_Bank1 */
		876
		877	#ifdef _EMI_Bank2
		878	EXT EMI_Bank_TypeDef *EMI_Bank2;
		879	#endif /* _EMI_Bank2 */
		880
		881	#ifdef _EMI_Bank3
		882	EXT EMI_Bank_TypeDef *EMI_Bank3;
		883	#endif /* _EMI_Bank3 */
		884
		885	#ifdef _FMI
		886	EXT FMI_TypeDef *FMI;
		887	#endif /* _FMI */
		888
		889	#ifdef _VIC0
		890	EXT VIC_TypeDef *VIC0;
		891	#endif /* _VIC0 */
		892
		893	#ifdef _VIC1
		894	EXT VIC_TypeDef *VIC1;
		895	#endif /* _VIC1 */
		896
		897	#ifdef _WIU
		898	EXT WIU_TypeDef *WIU;
		899	#endif /* _WIU */
		900
		901	#ifdef _TIM0
		902	EXT TIM_TypeDef *TIM0;
		903	#endif /* _TIM0 */
		904
		905	#ifdef _TIM1
		906	EXT TIM_TypeDef *TIM1;
		907	#endif /* _TIM1 */
		908
		909	#ifdef _TIM2
		910	EXT TIM_TypeDef *TIM2;
		911	#endif /* _TIM2 */
		912
		913	#ifdef _TIM3
		914	EXT TIM_TypeDef *TIM3;
		915	#endif /* _TIM3 */
		916
		917	#ifdef _GPIO0
		918	EXT GPIO_TypeDef *GPIO0;
		919	#endif /* _GPIO0 */
		920
		921	#ifdef _GPIO1
		922	EXT GPIO_TypeDef *GPIO1;
		923	#endif /* _GPIO1 */
		924
		925	#ifdef _GPIO2
		926	EXT GPIO_TypeDef *GPIO2;
		927	#endif /* _GPIO2 */
		928
		929	#ifdef _GPIO3
		930	EXT GPIO_TypeDef *GPIO3;
		931	#endif /* _GPIO3 */
		932
		933
		934	#ifdef _GPIO4
		935	EXT GPIO_TypeDef *GPIO4;
		936	#endif /* _GPIO4 */
		937
		938	#ifdef _GPIO5
		939	EXT GPIO_TypeDef *GPIO5;
		940	#endif /* _GPIO5 */
		941
		942	#ifdef _GPIO6
		943	EXT GPIO_TypeDef *GPIO6;
		944	#endif /* _GPIO6 */
		945
		946
		947	#ifdef _GPIO7
		948	EXT GPIO_TypeDef *GPIO7;
		949	#endif /* _GPIO7 */
		950
		951	#ifdef _GPIO8
		952	EXT GPIO_TypeDef *GPIO8;
		953	#endif /* _GPIO8 */
		954
		955	#ifdef _GPIO9
		956	EXT GPIO_TypeDef *GPIO9;
		957	#endif /* _GPIO9 */
		958
		959	#ifdef _RTC
		960	EXT RTC_TypeDef *RTC;
		961	#endif /* _RTC */
		962
		963
		964	#ifdef _SCU
		965	EXT SCU_TypeDef *SCU;
		966	# endif /* _SCU */
		967
		968	#ifdef _MC
		969	EXT MC_TypeDef *MC;
		970	#endif /* _MC */
		971
		972	#ifdef _UART0
		973	EXT UART_TypeDef *UART0;
		974	#endif /* _UART0 */
		975
		976	#ifdef _UART1
		977	EXT UART_TypeDef *UART1;
		978	#endif /* _UART1 */
		979
		980	#ifdef _UART2
		981	EXT UART_TypeDef *UART2;
		982	#endif /* _UART2*/
		983
		984	#ifdef _SSP0
		985	EXT SSP_TypeDef *SSP0;
		986	#endif /* _SSP0 */
		987
		988	#ifdef _SSP1
		989	EXT SSP_TypeDef *SSP1;
		990	#endif /* _SSP1 */
		991
		992	#ifdef _CAN
		993	EXT CAN_TypeDef *CAN;
		994	#endif /* _CAN */
		995
		996	#ifdef _ADC
		997	EXT ADC_TypeDef *ADC;
		998	#endif /* _ADC */
		999
		1000	#ifdef _WDG
		1001	EXT WDG_TypeDef *WDG;
		1002	#endif /* _WDG */
		1003
		1004	#ifdef _I2C0
		1005	EXT I2C_TypeDef *I2C0;
		1006	#endif /* _I2C0 */
		1007
		1008	#ifdef _I2C1
		1009	EXT I2C_TypeDef *I2C1;
		1010	#endif /* _I2C1 */
		1011
		1012	#ifdef _ENET
		1013	EXT ENET_MAC_TypeDef *ENET_MAC;
		1014	EXT ENET_DMA_TypeDef *ENET_DMA;
		1015	#endif /* _ENET */
		1016
		1017	#endif /* LIBDEBUG */
		1018	#endif /* __91x_MAP_H*/
		1019
		1020	/***************** (C) COPYRIGHT 2006 STMicroelectronics *END OF FILE**/
		1021

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(root)/tags/V0.1/libstr91x/include/91x_map.h - Rev 23