Rev 1 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1 | ingob | 1 | /******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** |
2 | * File Name : template.h |
||
3 | * Author : MCD Application Team |
||
4 | * Date First Issued : 05/18/2006 : Version 1.0 |
||
5 | * Description : provide a short description of the source file indicating |
||
6 | * its purpose. |
||
7 | ******************************************************************************** |
||
8 | * History: |
||
9 | * 05/22/2007 : Version 1.2 |
||
10 | * 05/24/2006 : Version 1.1 |
||
11 | * 05/18/2006 : Version 1.0 |
||
12 | ******************************************************************************** |
||
13 | * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS |
||
14 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. |
||
15 | * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, |
||
16 | * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE |
||
17 | * CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING |
||
18 | * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. |
||
19 | *******************************************************************************/ |
||
20 | |||
21 | /* Define to prevent recursive inclusion -------------------------------------*/ |
||
22 | #ifndef __91x_DMA_H |
||
23 | #define __91x_DMA_H |
||
24 | |||
25 | /* Includes ------------------------------------------------------------------*/ |
||
26 | #include"91x_map.h" |
||
27 | |||
28 | |||
29 | /* Exported types ------------------------------------------------------------*/ |
||
30 | |||
31 | typedef struct |
||
32 | { |
||
33 | u32 DMA_Channel_SrcAdd; /* The current source address (byte-aligned) of the data to be transferred.*/ |
||
34 | |||
35 | u32 DMA_Channel_DesAdd; /* The current destination address (byte-aligned) of the data to be transferred.*/ |
||
36 | |||
37 | u32 DMA_Channel_LLstItm; /* The word- aligned address for the next Linked List Item. */ |
||
38 | |||
39 | u32 DMA_Channel_DesWidth; /* Destination transfer width. */ |
||
40 | |||
41 | u32 DMA_Channel_SrcWidth; /* Source transfer width. */ |
||
42 | |||
43 | u32 DMA_Channel_DesBstSize; /* The destination burst size which indicates the number of transfers that make up a destination burst transfer request.*/ |
||
44 | |||
45 | u32 DMA_Channel_SrcBstSize; /* The source burst size.Indicates the number of transfers that make up a source burst */ |
||
46 | |||
47 | u32 DMA_Channel_TrsfSize; /* Transfer size which indicates the size of the transfer when the DMA controller is the flow controller*/ |
||
48 | |||
49 | u32 DMA_Channel_FlowCntrl; /* Flow control and transfer type. */ |
||
50 | |||
51 | u32 DMA_Channel_Src; /* Source peripheral: selects the DMA source request peripheral. */ |
||
52 | |||
53 | u32 DMA_Channel_Des; /* Destination peripheral:selects the DMA destination request peripheral. */ |
||
54 | |||
55 | } DMA_InitTypeDef; |
||
56 | |||
57 | /* Exported constants --------------------------------------------------------*/ |
||
58 | |||
59 | /* Interrupts masks */ |
||
60 | |||
61 | #define DMA_ITMask_IE 0x4000 /* Interrupt error mask. */ |
||
62 | #define DMA_ITMask_ITC 0x8000 /* Terminal count interrupt mask.*/ |
||
63 | #define DMA_ITMask_ALL 0xC000 /* All DMA_Channelx interrupts enable/disable mask*/ |
||
64 | |||
65 | /* Sources Request (used as masks) */ |
||
66 | |||
67 | #define DMA_USB_RX_Mask 0x0001 |
||
68 | #define DMA_USB_TX_Mask 0x0002 |
||
69 | #define DMA_TIM0_Mask 0x0004 |
||
70 | #define DMA_TIM1_Mask 0x0008 |
||
71 | #define DMA_UART0_RX_Mask 0x0010 |
||
72 | #define DMA_UART0_TX_Mask 0x0020 |
||
73 | #define DMA_UART1_RX_Mask 0x0040 |
||
74 | #define DMA_UART1_TX_Mask 0x0080 |
||
75 | #define DMA_External_Req0_Mask 0x0100 |
||
76 | #define DMA_External_Req1_Mask 0x0200 |
||
77 | #define DMA_I2C0_Mask 0x0400 |
||
78 | #define DMA_I2C1_Mask 0x0800 |
||
79 | #define DMA_SSP0_RX_Mask 0x1000 |
||
80 | #define DMA_SSP0_TX_Mask 0x2000 |
||
81 | #define DMA_SSP1_RX_Mask 0x4000 |
||
82 | #define DMA_SSP1_TX_Mask 0x8000 |
||
83 | |||
84 | |||
85 | /* Previleged Mode and user mode */ |
||
86 | |||
87 | #define DMA_PrevilegedMode 0x10000000 |
||
88 | #define DMA_UserMode 0xEFFFFFFF |
||
89 | |||
90 | |||
91 | /* Error and Terminal Count interrupts Status, after and before"raw" masking */ |
||
92 | #define DMA_IS 0x01 |
||
93 | #define DMA_TCS 0x02 |
||
94 | #define DMA_ES 0x03 |
||
95 | #define DMA_TCRS 0x04 |
||
96 | #define DMA_ERS 0x05 |
||
97 | |||
98 | |||
99 | /* interrupt clear: Terminal Count flag Clear and Error flag clear*/ |
||
100 | |||
101 | #define DMA_TCC 0x01 |
||
102 | #define DMA_EC 0x02 |
||
103 | |||
104 | /* channel index "0...7"*/ |
||
105 | |||
106 | #define Channel0 0 |
||
107 | #define Channel1 1 |
||
108 | #define Channel2 2 |
||
109 | #define Channel3 3 |
||
110 | #define Channel4 4 |
||
111 | #define Channel5 5 |
||
112 | #define Channel6 6 |
||
113 | #define Channel7 7 |
||
114 | |||
115 | |||
116 | |||
117 | /* Destination request selection: selects the DMA Destination request peripheral */ |
||
118 | |||
119 | #define DMA_DES_USB_RX 0x00 |
||
120 | #define DMA_DES_USB_TX 0x40 |
||
121 | #define DMA_DES_TIM0 0x80 |
||
122 | #define DMA_DES_TIM1 0xC0 |
||
123 | #define DMA_DES_UART0_RX 0x100 |
||
124 | #define DMA_DES_UART0_TX 0x140 |
||
125 | #define DMA_DES_UART1_RX 0x180 |
||
126 | #define DMA_DES_UART1_TX 0x1C0 |
||
127 | #define DMA_DES_External_Req0 0x200 |
||
128 | #define DMA_DES_External_Req1 0x240 |
||
129 | #define DMA_DES_I2C0 0x280 |
||
130 | #define DMA_DES_I2C1 0x2C0 |
||
131 | #define DMA_DES_SSP0_RX 0x300 |
||
132 | #define DMA_DES_SSP0_TX 0x340 |
||
133 | #define DMA_DES_SSP1_RX 0x380 |
||
134 | #define DMA_DES_SSP1_TX 0x3C0 |
||
135 | |||
136 | |||
137 | |||
138 | |||
139 | /* Source request selection: selects the DMA Source request peripheral */ |
||
140 | |||
141 | #define DMA_SRC_USB_RX 0x00 |
||
142 | #define DMA_SRC_USB_TX 0x02 |
||
143 | #define DMA_SRC_TIM0 0x04 |
||
144 | #define DMA_SRC_TIM1 0x06 |
||
145 | #define DMA_SRC_UART0_RX 0x08 |
||
146 | #define DMA_SRC_UART0_TX 0x0A |
||
147 | #define DMA_SRC_UART1_RX 0x0C |
||
148 | #define DMA_SRC_UART1_TX 0x0E |
||
149 | #define DMA_SRC_External_Req0 0x10 |
||
150 | #define DMA_SRC_External_Req1 0x12 |
||
151 | #define DMA_SRC_I2C0 0x14 |
||
152 | #define DMA_SRC_I2C1 0x16 |
||
153 | #define DMA_SRC_SSP0_RX 0x18 |
||
154 | #define DMA_SRC_SSP0_TX 0x1A |
||
155 | #define DMA_SRC_SSP1_RX 0x1C |
||
156 | #define DMA_SRC_SSP1_TX 0x1E |
||
157 | |||
158 | |||
159 | |||
160 | |||
161 | |||
162 | #define DMA_FlowCntrlt0_DMA 0x00000000 /* transfer type :Memory-to-memory, flow controller:DMA */ |
||
163 | #define DMA_FlowCntrl1_DMA 0x00000800 /* transfer type :Memory-to-peripheral, flow controller:DMA */ |
||
164 | #define DMA_FlowCntrl2_DMA 0x00001000 /* transfer type :Peripheral-to-memory, flow controller:DMA */ |
||
165 | #define DMA_FlowCntrl3_DMA 0x00001800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:DMA */ |
||
166 | #define DMA_FlowCntrl_DestPerip 0x00002000 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Destination peripheral */ |
||
167 | #define DMA_FlowCntrl_Perip1 0x00002800 /* transfer type :Memory-to-peripheral, flow controller:peripheral */ |
||
168 | #define DMA_FlowCntrl_Perip2 0x00003000 /* transfer type : Peripheral-to-memory, flow controller:peripheral */ |
||
169 | #define DMA_FlowCntrl_SrcPerip 0x00003800 /* transfer type :Source peripheral-to-destination peripheral, flow controller:Source peripheral */ |
||
170 | |||
171 | |||
172 | |||
173 | |||
174 | #define DMA_SrcBst_1Data 0x00000000 /* Source Burst transfer request IS 1 Data ( DATA = Source transfer width ) */ |
||
175 | #define DMA_SrcBst_4Data 0x00001000 /* Source Burst transfer request IS 4 Data */ |
||
176 | #define DMA_SrcBst_8Data 0x00002000 /* Source Burst transfer request IS 8 Data */ |
||
177 | #define DMA_SrcBst_16Data 0x00003000 /* Source Burst transfer request IS 16 Data */ |
||
178 | #define DMA_SrcBst_32Data 0x00004000 /* Source Burst transfer request IS 32 Data */ |
||
179 | #define DMA_SrcBst_64Data 0x00005000 /* Source Burst transfer request IS 64Data */ |
||
180 | #define DMA_SrcBst_128Data 0x00006000 /* Source Burst transfer request IS 128 Data */ |
||
181 | #define DMA_SrcBst_256Data 0x00007000 /* Source Burst transfer request IS 256 Data */ |
||
182 | |||
183 | |||
184 | |||
185 | |||
186 | #define DMA_DesBst_1Data 0x00000000 /*Destination Burst transfer request IS 1Data ( DATA = destination transfer width ) */ |
||
187 | #define DMA_DesBst_4Data 0x00008000 /*Destination Burst transfer request IS 1 Data */ |
||
188 | #define DMA_DesBst_8Data 0x00010000 /*Destination Burst transfer request IS 4 Data */ |
||
189 | #define DMA_DesBst_16Data 0x00018000 /*Destination Burst transfer request IS 8 Data */ |
||
190 | #define DMA_DesBst_32Data 0x00020000 /*Destination Burst transfer request IS 16 Data */ |
||
191 | #define DMA_DesBst_64Data 0x00028000 /*Destination Burst transfer request IS 32 Data */ |
||
192 | #define DMA_DesBst_128Data 0x00030000 /*Destination Burst transfer request IS 128 Data */ |
||
193 | #define DMA_DesBst_256Data 0x00038000 /*Destination Burst transfer request IS 256 Data */ |
||
194 | |||
195 | |||
196 | |||
197 | |||
198 | |||
199 | #define DMA_SrcWidth_Byte 0x00000000 /* source Width is one Byte */ |
||
200 | #define DMA_SrcWidth_HalfWord 0x00040000 /* source Width is one HalfWord */ |
||
201 | #define DMA_SrcWidth_Word 0x00080000 /* source Width is one Word */ |
||
202 | |||
203 | |||
204 | |||
205 | |||
206 | #define DMA_DesWidth_Byte 0x00000000 /* Destination Width is one Byte */ |
||
207 | #define DMA_DesWidth_HalfWord 0x00200000 /* Destination Width is one HalfWord */ |
||
208 | #define DMA_DesWidth_Word 0x00400000 /* Destination Width is one Word */ |
||
209 | |||
210 | |||
211 | |||
212 | |||
213 | |||
214 | |||
215 | /* Exported macro ------------------------------------------------------------*/ |
||
216 | /* Exported functions ------------------------------------------------------- */ |
||
217 | |||
218 | void DMA_DeInit(void); |
||
219 | void DMA_Init(DMA_Channel_TypeDef * DMA_Channelx, DMA_InitTypeDef * DMA_InitStruct); |
||
220 | void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); |
||
221 | void DMA_Cmd(FunctionalState NewState); |
||
222 | void DMA_ITMaskConfig(DMA_Channel_TypeDef * DMA_Channelx, u16 DMA_ITMask, FunctionalState NewState); |
||
223 | void DMA_ITConfig(DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); |
||
224 | FlagStatus DMA_GetChannelStatus(u8 ChannelIndx ); |
||
225 | ITStatus DMA_GetITStatus(u8 ChannelIndx,u8 DMA_ITReq); |
||
226 | void DMA_ClearIT(u8 ChannelIndx,u8 DMA_ITClr); |
||
227 | void DMA_SyncConfig(u16 DMA_SrcReq, FunctionalState NewState); |
||
228 | FlagStatus DMA_GetSReq(u16 DMA_SrcReq); |
||
229 | FlagStatus DMA_GetLSReq(u16 DMA_SrcReq); |
||
230 | FlagStatus DMA_GetBReq(u16 DMA_SrcReq); |
||
231 | FlagStatus DMA_GetLBReq(u16 DMA_SrcReq); |
||
232 | FlagStatus DMA_GetChannelActiveStatus( DMA_Channel_TypeDef * DMA_Channelx); |
||
233 | void DMA_SetSReq(u16 DMA_SrcReq); |
||
234 | void DMA_SetLSReq(u16 DMA_SrcReq); |
||
235 | void DMA_SetBReq(u16 DMA_SrcReq); |
||
236 | void DMA_SetLBReq(u16 DMA_SrcReq); |
||
237 | void DMA_ChannelCmd (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); |
||
238 | void DMA_ChannelHalt (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); |
||
239 | void DMA_ChannelBuffering (DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); |
||
240 | void DMA_ChannelLockTrsf(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); |
||
241 | void DMA_ChannelCache(DMA_Channel_TypeDef * DMA_Channelx,FunctionalState NewState); |
||
242 | void DMA_ChannelProt0Mode(DMA_Channel_TypeDef * DMA_Channelx,u32 Prot0Mode); |
||
243 | void DMA_ChannelSRCIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); |
||
244 | void DMA_ChannelDESIncConfig (DMA_Channel_TypeDef * DMA_Channelx, FunctionalState NewState); |
||
245 | |||
246 | #endif /* __91x_DMA_H */ |
||
247 | |||
248 | /******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE****/ |